Quest for the Optimum Power Distribution Architecture
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- Tracy Maxwell
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2 Quest for the Optimum Power Distribution Architecture Which power distribution architectures can efficiently support power systems from wall plugs, AC or DC outlets, through capacitors, super-capacitors or batteries, to processor cores in the home, in the office, in the factory and everywhere in between? Centralized Power Architecture (CPA) Distributed Power Architecture (DPA) Intermediate Bus Architecture (IBA) Factorized Power Architecture (FPA) 2
3 Power Architecture Evolution Centralized Power (CPA) AC in Central Power Supply 5 V AC in Central Power Supply 5 V 1.0 V 3
4 Centralized Power Architecture Centralized power remains pervasive in smaller systems due to its simplicity and low cost But is unable to efficiently deliver high currents at low voltages 4
5 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Isolated DC-DC converter DC bus System boards 5
6 Distributed Power Architecture Distributed power addresses architectural limitations of CPA Provides efficient power distribution at higher voltages Puts bricks at the Point of Load (POL) But DPA comes at a price Board real estate System cost 6
7 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Isolated intermediate bus converter Non-isolated POL converters (nipols) Semi-regulated DC bus System board 7
8 Intermediate Bus Architecture Intermediate bus deals with the proliferation of load voltages Puts inexpensive non-isolated buck converters at the POL But IBA is limited by Inability to transform V and I Having to decrease a duty cycle to reduce output voltage Inductive inertia standing in the way of dynamic loads 8
9 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) Non-isolated pre-regulators (PRMs) Isolated POL converters (VTMs) DC bus System board 9
10 Factorized Power Architecture Factorized power addresses demanding POL current and voltage requirements: Puts a fast current multiplier at POL nodes Transforms V and I down to fractional POL voltages 100% effective duty cycle 10
11 IBA Inherent Duty Cycle Limitations Duty cycle here is only 7% IBC Isolation & Transformation nipol Regulation & Step Down At 0.8 Vout N P N S L Regulated load voltage Distribution bus e.g. Semi-regulated 48 Vdc Isolates steps down Semi-regulated Intermediate Bus Steps down regulates e.g. 12 Vdc 11
12 FPA No Duty Cycle Limitations PRM Regulation VTM Isolation & Transformation 100% effective duty cycle at any Vout Wide range DC bus e.g Vdc L N P N S Regulated load voltage K = N S / N P Factorized bus 12
13 IBA Inherent Step-Down Limitations nipol IBA IBA IBA 48 Vdc 48 Vdc 48 Vdc 48 Vdc IBC IBC 12 Vdc 3.0 Vdc IBC 2.0 Vdc 2% nipol 7% nipol 26% nipol 40% nipol 0.8 Vdc 0.8 Vdc 0.8 Vdc 0.8 Vdc 13
14 nipol FPA No Step-Down Limitations IBA IBA IBA FPA 48 Vdc 48 Vdc 48 Vdc 48 Vdc 48 Vdc IBC IBC 12 Vdc 3.0 Vdc IBC 2.0 Vdc 48 Vf 2% nipol 7% nipol 26% nipol 40% nipol 100% 0.8 Vdc 0.8 Vdc 0.8 Vdc 0.8 Vdc 0.8 Vdc 14
15 IBA Inherent Energy Storage & Dynamic Response Limitations IBC Upstream storage ineffective as load bypass Isolation & Transformation L in wrong place nipol Regulation & Step Down Bulk storage required N P N S L 15
16 FPA No Energy Storage or Dynamic Response Limitations Upstream storage 1/K 2 times more effective PRM Regulation No intervening L No bulk storage needed VTM Isolation & Transformation L N P N S X K = N S / N P 16
17 Energy Storage in the Wrong Place 48 Vdc N P IBC N S nipol L 10,000 µf here 0.8 Vdc Energy Storage in the Right Place PRM L N P N S can be replaced by 10 µf here VTM 48 Vdc 0.8 Vdc K = N S / N P 17
18 V I Chips (VICs) The Building Blocks of Factorized Power Full VIC ~ 1.0 in 2 surface mount package PRM Pre-Regulator Module VTM Voltage Transformation Module 18
19 Basic FPA with PRM & VTM Local Loop Wide range Input bus Factorized bus V f V f K Load PRM controls the factorized bus voltage (V f ) to regulate the VTM output VTM transforms and isolates at the POL Combination: efficient distribution, regulation, transformation and isolation Patents and Patents Pending 19
20 FPA Example Adaptive Loop with PRM Vdc Telecom bus V f = 48 Vdc K = 1/ Vdc Load 1 12 Vdc Load 2 K = 1/4 Patents and Patents Pending 20
21 FPA Example Independently Regulated Outputs V f = 26 Vdc K = 1/ Vdc Load Vdc Telecom bus Isolated Remote Loop POLIC Adaptive Loop V f = 40 Vdc K = 1/8-5 Vdc Load 2 Patents and Patents Pending 21
22 The Engine Under the Hood PRM 22
23 Full VIC PRM Capabilities ZVS buck / boost regulator Input voltage: V (up to 5:1 range) Step-up/step-down range: up to 5:1 Output power: up to 300 W Conversion efficiency: up to 98% Frequency: up to 2 MHz 23
24 Full VIC PRM Capabilities ZVS buck / boost regulator Input voltage: V (up to 5:1 range) Step-up/step-down range: up to 5:1 Output power: up to 300 W Conversion efficiency: up to 98% Frequency: up to 2 MHz 24
25 PRM ZVS Buck/Boost Engine ZVS buck-boost topology and control architecture High frequency operation Patents and Patents Pending 25
26 Power cycle comprises four conduction phases 1. Input phase PRM Conduction Phases Patents and Patents Pending 26
27 Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase PRM Conduction Phases Patents and Patents Pending 27
28 Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase 3. Free-wheeling phase PRM Conduction Phases Patents and Patents Pending 28
29 Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase 3. Free-wheeling phase 4. Clamp phase PRM Conduction Phases Patents and Patents Pending 29
30 Vin < Vout Patents and Patents Pending 30
31 Vin < Vout Patents and Patents Pending 31
32 Vin < Vout Patents and Patents Pending 32
33 Vin < Vout Patents and Patents Pending 33
34 Vin < Vout Patents and Patents Pending 34
35 Vin < Vout Patents and Patents Pending 35
36 Vin < Vout Patents and Patents Pending 36
37 Vin < Vout Patents and Patents Pending 37
38 Vin < Vout Patents and Patents Pending 38
39 Vin Vout Patents and Patents Pending 39
40 Vin Vout Patents and Patents Pending 40
41 Vin Vout Patents and Patents Pending 41
42 Vin Vout Patents and Patents Pending 42
43 Vin Vout Patents and Patents Pending 43
44 Vin Vout Patents and Patents Pending 44
45 Vin Vout Patents and Patents Pending 45
46 Vin Vout Patents and Patents Pending 46
47 Vin Vout Patents and Patents Pending 47
48 Vin > Vout Patents and Patents Pending 48
49 Vin > Vout Patents and Patents Pending 49
50 Vin > Vout Patents and Patents Pending 50
51 Vin > Vout Patents and Patents Pending 51
52 Vin > Vout Patents and Patents Pending 52
53 Vin > Vout Patents and Patents Pending 53
54 Vin > Vout Patents and Patents Pending 54
55 Vin > Vout Patents and Patents Pending 55
56 The Engine Under the Hood VTM 56
57 Full VIC VTM Capabilities ZCS / ZVS Sine Amplitude Converter (SAC) Input voltage: V (up to 2:1 range) Output voltage: V Transformation ratio (K): 1/200 to 200 Output current or power: up to 100 A or 300 W Conversion efficiency: up to 97% Conversion frequency: up to 4 MHz, fixed 57
58 VTM / BCM SAC Power Train Primary Engine is a Low Q oscillator formed by CRES and the leakage inductance of T1 Patents and Patents Pending 58
59 VTM / BCM SAC Power Train The Low Q oscillator is driven by an H-bridge Patents and Patents Pending 59
60 VTM / BCM SAC Power Train In this particular example, secondary rectification is also performed using an H-bridge Patents and Patents Pending 60
61 VTM/BCM SAC Power Train Load current drives the Low Q oscillator by pulling primary current Patents and Patents Pending 61
62 VTM / BCM Sine Amplitude Converter (SAC) The amplitude of the Low Q oscillator is proportional to the load current as reflected back to the primary Patents and Patents Pending 62
63 VTM / BCM Level 2 Behavioral Model 48 V to 1.5 V 100 A VTM Patents and Patents Pending 63
64 VTM / BCM SAC Control The controller locks to the natural frequency of the Low Q oscillator and turns all switches ON and OFF under ZCS/ZVS conditions Conduction states result in a 100% effective duty cycle Control circuitry recycles the gate drive energy from each pair of switches Patents and Patents Pending 64
65 VTM / BCM SAC Control Control Servo locks to Sine Amplitude Converter resonant frequency and phase, compensating for power train parametric variabilities Soft start, inrush control and Adaptive Loop Compensation of Rout Patents and Patents Pending 65
66 VTM Operation Phases Patents and Patents Pending 66
67 VTM Operation Phases Patents and Patents Pending 67
68 VTM Operation Phases Patents and Patents Pending 68
69 VTM Operation Phases Patents and Patents Pending 69
70 VTM Operation Phases #1 Patents and Patents Pending 70
71 VTM / BCM SAC Engine Additional Features Bi-directional power transfer Flexibility of topology Common-mode cancellation 71
72 Superior System Performance Higher power/current density Power conversion building blocks occupy less space Higher efficiency Power conversion building blocks generate less heat Faster transient response Overcomes processor/power technology gap Lower input and output noise Reduced filtering frees up board space 72
73 SAC: Highest Power Density High fixed switching frequency (up to 4 MHz) Reduces size of all reactive components Zero-current & zero-voltage switching (ZCS/ZVS) Reduces stresses, losses and heat No serial energy storage No output inductor 100% effective transformation duty cycle Efficient power train utilization 73
74 From nipols to VICs 16 A / 80 W nipol Surface mount Efficiency: 12 Vin to 1.2 Vout = 83% 1.30" x 0.53" x 0.37" (33,0 mm x 13,5 mm x 9,3 mm) Area: 0.7 in 2 (4,5 cm 2 ) Volume: 0.25 in 3 (4,1 cm 3 ) 100 A / 300 W V I Chip Surface mount Efficiency: 48 Vin to 1.2 Vout = 91% 1.26 " x 0.85" x 0.24" (32,0 mm x 21,5 mm x 6,0 mm) Area: 1.1 in 2 (6,9 cm 2 ) Volume: 0.26 in 3 (4,1 cm 3 ) 74
75 From nipols to VICs 16 A / 80 W nipol 100 A / 300 W V I Chip 320 W/in 3 1,095 W/in 3 64 A/in A/in W/in W/in 2 23 A/in 2 91 A/in 2 75
76 SAC: Highest Efficiency ZCS / ZVS No switching losses Low Q transformer Reduced winding losses No serial energy storage No inductor losses 100% effective transformation duty cycle Efficient power train utilization 76
77 Efficiency 77
78 Efficiency 78
79 SAC: Fastest Dynamic Response No serial energy storage & Low Q transformer No current inertia & quick settling High fixed switching frequency (up to 4 MHz) Minimal cycle-to-cycle delay Load independent control No lag due to control loop Bi-directional power processing Load dump energy recycled to input Capacitance multiplication High effective POL capacitance: Cout (eff) ~ Cin (1/K) 2 + Cout 79
80 Dynamic Response K = 1/32 Vout = 1 V A load step with 100 µf input capacitance and NO output capacitance A load step with 100 µf input capacitance and NO output capacitance 80
81 ZCS/ZVS SAC: Lowest Noise Order of magnitude reduction in di/dt Significant reduction in dv/dt Symmetric power train Cancellation of common-mode noise High fixed switching frequency (up to 4 MHz) Easy to filter 81
82 Output Noise K = 1/ V & 100 A Output voltage 100 A with NO bypass capacitance Output voltage 100 A with 200 µf ceramic bypass capacitance and 20 nh distribution inductance 82
83 The Flexibility of FPA Most contemporary power systems are a hybrid of centralized, distributed and intermediate bus Factorized power building blocks support existing power distribution architectures 83
84 V I Chip Package Flexibility Surface mount BGA package for in-board mounting Surface mount J-Lead package for on-board mounting Surface mount extended J-Lead package for on-board mounting 84
85 Intermediate Bus VTMs function as intermediate bus converters (BCMs) More power and more performance in less space 85
86 Distributed Power A PRM and VTM pair can replace bricks Superior performance at less cost 86
87 VICBrick Up to 100 A in a 0.25" High Quarter-brick Package 87
88 Centralized Power PRMs can be remotely located Low current factorized buses can be easily routed throughout the system Central Power Supply 1.8 V +5 V -12 V Central Power Supply 12 PRM 12 PRM 12 PRM V F3 V F2 V F1 12 VTM 12 VTM 12 VTM 88
89 From the Wall Plug to the Processor Core Watt FPA Solution 89
90 Conventional Power System Architecture 12 V Intermediate Bus ~ AC Front-end 12 V 176 W 12 V 110 W VR10 Multi-phase Buck Converter P4 Processor P diss 29 W 86% efficiency P diss 14 W 87% efficiency nipol Linear Reg. nipol Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 90
91 12 V Input PRM/VTM Sub-system ~ AC Front-end 12 V 176 W V f P4 Processor P diss 29 W 86% efficiency P diss 12 W 89% efficiency nipol nipol Linear Reg. Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 91
92 Advanced Processor FPA System ~ Vicor AC Front-end V f 103 W P4 Processor P diss 17 W 91% efficiency 12 V P diss 7 W 93% efficiency nipol nipol Linear Reg. Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 92
93 Front-end Comparative Benchmark Conventional 12 V Input Advanced Pentium 4 PRM / VTM Processor Power System Sub-System FPA System Efficiency 86% 86% 91% Power dissipation 18 W 18 W 11 W Power density 6.6 W/in W/in 3 25 W/in 3 POL (processor) Efficiency 80 A) 87% 89% 93% Power dissipation 14 W 12 W 7 W Power density 23 W/in 3 59 W/in W/in 3 Total (without auxiliary outputs) Efficiency 75% 77% 85% Power dissipation 32 W 30 W 18 W Power density 3.2 W/in W/in W/in 3 93
94 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) Which is the Future? 94
95 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) OHMS LAW & VANISHING DUTY CYCLE Limited Applicability Fast! Efficient! Dense! From the Wall Plug to the Processor Core! 95
96 FPA & V I Chips Power Paradigm of the Future Questions? 96
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