Stability Analysis of Bus Architecture

Transcription

1 24 IBM Power Technology Symposium Stability Analysis of Bus Architecture 9/14-15/24 TDK Innoveta Inc. TDK Corporation 1

2 Agenda Trend/Evolution of Distributed Power Architecture (DPA), and Type of Bus Architectures Stability Analysis of Bus Architecture 2

3 Trend/Evolution of DPA and Type of Bus Architecture 3

4 Trend of DPA (Distributed Power Architecture) 197 DPA level Level 2 5V 3.3V Level 3 (Isolated solution) Level 4 (Bus Architecture) 48Vin 1V 5V 48V 48Vin AC Unit type DC-DC Card type Board Mounted Type DC-DC (Brick Converter) Bus converter Non-isolated (POL) Shelf/Unit 4

5 Example(1) Fully-regulated (Brick) POL Brick 3.3/5Vin POL Front end/ Battery plant 48V 5V, 3.3Vbus OPT/IF OPT/IF 3.3V 3-5W Capacitors Memory Memory 2.5V 1.8V-1.1V ASIC/FPGA ASIC/FPGA Regulated Intermediate Bus (3.3V/5V) 5

6 Example(2): Un-regulated bus converter Wide input POL- Front end Bus converter (Narrow input) 48V Wide input POL OPT/IF OPT/IF 3.3V 3-5W Capacitors FPGA/ FPGA/ ASIC ASIC 1.8V-1.2V up 1.5V-1.1V Un-regulated 12V, 9.6V 6

7 Example(3): Fully-regulated bus converter (Brick) POL- Brick Narrow/Wide input POL Front end/ Battery plant 48V OPT/IF OPT/IF 3.3V 3-5W Capacitors FPGA/ FPGA/ ASIC ASIC 1.8V-1.2V up 1.5V-1.1V Regulated 12V 7

8 Variation of Bus Architecture -Application point of view- Fully-regulated bus ATCA (36-72Vin) Fully/Semi-regulated bus Telecom normal input 36-6Vin Telecom wide input 36-72Vin Un-regulated bus Server, Storage Datacom. Narrow input (43-53Vin) 8

9 Relation between Input Sources and Bus Converters, and Bus Voltages Input sources Bus converters Bus voltages Narrow input (43-53Vin) Un-regulated 4:1 Un-regulated 12V 5:1 Un-regulated 9.6V Telecom normal input (36-6Vin) Semi-regulated Semi-regulated 12V Semi-regulated 9.6V Telecom wide input, ATCA input (36-72Vin) Fully-regulated Fully-regulated 12V Fully-regulated 9.6V Fully-regulated 5V Fully-regulated 3.3V 9

10 POL Input Range of Bus Voltage Bus Voltage Un-regu 4:1 Un-regu 5:1 3-5V input POL cover Vin (V) 12V fully-regu 12V wide input POL cover 5V fully-regu 3.3V fully-regu 1

11 Stability Analysis of Bus Architecture 11

12 Considerations Evolution of the bus architecture allows flexibility and low cost concept in different applications. Because of many different types of bus architecture, the stability of the system has become an important issue. This report discusses stability for 3 types of bus converter and POL based on impedance analysis. To simplify the comparison, we have ignored the impact from internal interference between bus converter and POL. The spec. used in this simulation of the power supply is 48Vin, bus voltage of 12V and POL of 1.5Vout/3Aout with 1 units in parallel. The detail value of the components such as output inductance, capacitance and cross-over frequency, etc are shown in table 1. The example of the simulation can not cover all phenomenon, but we could leverage this method to practical applications. 12

13 Concept of 3 types of Bus Architectures 43-53V, 36-6V 48V Un-regulated Bus converter Zin 12V, 9.6V Zo POL Load AC 1V/2V AC/DC 48V Bus Con. POL POL POL 1.5V/3A Load 2.5V/2A Load 3.3V/1A Load Non Isolated DC-DC Con V, 36-6V, 36-72V 48V Semi-regulated Bus converter d PWM Controller Zin 12V,9.6V Zo POL Load 43-53V, 36-6V, 36-72V 48V Full-regulated Bus converter d PWM Controller Zin Zo POL 12V, 9.6V, 5V, 3.3V, Load 13

14 Block Diagram of Bus Converter, POL and its Parameter used in Simulation Vb Vin Bus converter POL Lb n : 1 Lo rl Co rc R rlb Cb rcb vo - - vb Bus Converter POL Table 1 Symbol Description Value Vin Input Volotage 48V Vb Bus Volotage 12V fcb Crossover frequency of Bus Converter 15-25kHz Lb Cb rlb rcb Vo/Io Output Inductor of Bus Converter Output Capacitor of Bus Converter Registance of Lb ESR of Cb Output Condition.5-1µH.4-15mF 1mΩ 5mΩ 1.5V/3A fcp Crossover frequency of POL 5kHz Lo Co rl Output inductor Output capacitor Registance of Lo 1.5µH 1µF 1mΩ rc ESR of Co 5mΩ 14

15 Output Impedance (Zo) of bus converter Open loop (Un-regu, Semi-regu) vbus 1 Z () s = = s LC r s( L C r r ) r i P() s { } 2 o b b c b b L c L bus Where, b b b b 2 P( s) = s LbCb scb( rlb rcb) 1 Closed loop (Fully-regu) Z o_ close Z () s o () s = 1 T ( s ) Where, T(s) is a transfer function of Bus converter T = H() s G () s PWM G () s c dv b H(s): sense gain, Gc(s)=transfer function of the compensator, PWM: gain of the comparator, Gdv(s)=Vs/P(s) x (scrc1) 15

16 Input Impedance (Zin) of POL Zin Vb Lo rl Co rc R vo - Z D ( s) = Z n ( sl o r L R ( s) = D 1 ) ( sc 2 D 2 o r c ) // R Magnitude (db) n=1 n=1 Bode Diagram 1 1 T ( s) 1 = Z in ( s) Z N ( s) 1 T ( s) Z D ( s) 1 1 T ( s) Where, T(s) is a transfer function of POL Phase (deg) Frequency (Hz) 1 modules in parallel 16

17 General Un-stability Phenomenon Magnitude (db) Phase (deg) Input Impedance Output Impedance Bode Diagram Output impedance and input impedance Phase (deg) Magnitude (db) Frequency Bode Diagram (Hz) Frequency response of loop gain Frequency (Hz) 17

18 Semi-regulated Semi-regulated vˆ () s in Hi () s ref _ in Gvv () s - Gci () s vˆ () s Z o iˆ () s b ( s) Gdv () s PWM Comparator To get 12db margin, 1,uF of capacitor is needed at bus. Zin Zo vˆ () s b 1,uF Magnitude (db) Phase (deg) POL Zin of POL 2µF 1µF Bode Diagram 4µF Lb=1uH Zo of semi-regulated Bus converter Frequency (Hz) 18

19 Fully-regulated Fully-regulated vˆ () s in Gvv () s Lb=1uH Z o iˆ () s o ( s) Gdv() s PWM Comparator Gc ( s) Compensator Increase the cross over frequency of fullregulated bus converter damp the peak of Zo. vˆ () s ref - H Zin Zo vˆ () s o Sense Gain ( s) POL 2,-3,uF Further more, 2,-3,uF capacitor help To get 1deb margin. Magnitude (db) Phase (deg) 2 1 Zin of POL Zo of full-regulated -4 Bus converter Bode Diagram Frequency (Hz) 15Hz 15kHz 25kHz Magnitude (db) Phase (deg) Zin of POL Bode Diagram 4µF 1µF 5µF Frequency (Hz) Zo of full-regulated Bus converter Cb and Zo : fcp=15khz (Full-regulated case) 19

20 Un-regulated Un-regulated iˆ () s o Zin Zo vˆ () s in Gvv () s Z o ( s) vˆ () s o POL Gdv() s Phase (deg) Magnitude (db) Zin of POL PWM Comparator Zo of un-regulated Bus converter Gc ( s) Compensator Bode Diagram vˆ () s ref 1µH - 2µH * o.5µh vˆ () s 4uF Un-regulated bus converter has small output inductance such as.5uh, so it is stable without large extra capacitor at the bus Frequency (Hz) 2

21 Conclusion Semi-regulated bus converter POL Need a large bus capacitor compare to un-regu. and fully-regu. to be stable. Can cover telecom normal input range (36-6Vin) Fully-regulated bus converter POL By adjusting a cross over frequency of bus converter, it can reduce the bus capacitor for stability rather than semi-regu. Can cover telecom wide input range (36-72Vin) Un-regulated bus converter POL Most stable (means less capacitor than others). Can cover limited input range (narrow range of 43-53V) In a practical application, the bus capacitor should be designed by ripple, transient response, stability consideration. 21

22 Product for Bus Architecture 22

23 Bus Converters Un-regulated Bus converter (4:1) ieb series : 12V/3W (Quarter brick size) iqd series: 12V/15W (Eighth brick size) Fully-regulated Bus Converter (Brick : 12V, 5V, 3.3V) iea series iqb series iqm series 23

24 POLs 12V wide input range (6-14V) PMH series Vo=.75-5V Io = 16A 3-5.5V input iba series iaa series Vo= V Io =15A Vo= V Io =8A 24