Digital Control Methods for Current Sharing of Interleaved Synchronous Buck Converter

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1 Digital Control Methods for Current Sharing of Interleaved Synchronous Buck Converter Keywords «Converter control», «DSP», «ZVS converters» Abstract Pål Andreassen, Tore M. Undeland Norwegian University of Science and Technology O.S. Bragstadsplass E Trondheim, Norway Tel.: Fax: pal.andreassen@elkraft.ntnu.no UR: The quasi square wave operation of the synchronous buck with interleaved parallel outputs has been successfully used in low voltage high current DCsupply for microprocessors. This topology results in fast transient response and high power density. In this paper, two digital control strategies for current sharing control are tested by simulation in Simulink, and tested in the laboratory. The digital current control methods are tested using a MHz Texas Instrument TMSF8 DSP and studied with regard to the current reference step response. The results from the simulations and the experiments show that it is possible to increase control performance by using a predictive controller but that this would require extra cost and design effort to implement a low noise and high bandwidth measurement hardware on the output voltage. Introduction The quasi square wave (QSW) operation of the synchronous buck converter is proven to result in fast transient response, high power density and zero voltage switching (ZVS) []. This topology is a good candidate for high current low voltage DCsupply for microprocessors. The synchronous buck in QSW operation is operated in a so called synchronous continuous conduction mode []. By allowing reverse current through bidirectional switches, the power may flow in both directions. Because of this, the ZVS QSW converter could be used in topologies where bidirectional power flow is needed []. The disadvantages of the quasi square wave operation are high transistor peak current and high input/output current ripple, to achieve zero voltage switching. V in + I I o I I I V o Fig. : Interleaved ZVS Quasi Square Wave Buck Converter I o

2 The current ripple is more than times the average output current. High turnoff current of the main switch tends to increase the turn off losses, especially when minoritycarrier devices such as IGBTs are used []. Because of the high current ripple, interleaved parallel outputs are necessary in order to keep the ripple current in both the input capacitor and the output capacitor low. With the interleaved parallel outputs a controller is needed in order to ensure load current sharing and phase shift of the current ripple. The most common solution in order to implement current sharing is analog peak current mode control []. The error signal of the outputvoltage controller is used as a common peak current reference signal for all parallel outputs. The common reference signal is compared with the instantaneous inductor current in a separate controller for each output. The PWM output is set low if the inductor current is larger than the reference signal. The result is a separate duty cycle for each module in order to level out the peak current in all of the outputs. The sharing of the average current will therefore be dependent on the variation of inductance in each output. A direct implementation of the analog peak current mode control scheme in digital hardware would require a very fast A/D converter because you would need a large number of samples per switching period. The need for large signal processing capabilities would require expensive hardware. Therefore, methods more applicable to digital control hardware have been developed [, 6]. Digital control and sampling strategies The TMSF8 DSP used in these experiments has two eventmanagers. With the eventmanager an updown timer can be set up to a triangular wave form and compared to an input value to generate symmetric pulse width modulation (PWM). The eventmanager can then generate up to four interrupts. It can generate an interrupt on timer underflow, on timer period match and on compare match both in upand downcounting direction. Fig.a shows the available interrupts. A compare match triggers the switching of the transistors. Sampling of interleaved currents Based on the theory of symmetric PWM, in steady state the peak current will be on compare match in upcounting direction, the valley current will be on compare match in the downcounting direction, and the average value of the inductor current will be on timer underflow and on period match. The interrupts can trigger a sampling of the current. In which interrupt to sample the current may be selected based on if the peak current, the valley current or the average current is to be controlled. Timer Timer Timer PWM PWM Compare PWM Compare & Int Int Int Int Sample[n] V in, V o, I, I Sample[n+] V in, V o, I, I Fig. : Single triangle sampling and interrupts Interleaved sampling and pulse width modulation

3 This method of sampling the current and generating a pulse width modulated signal is often used in new digital control of motor drives. With the ZVSQSW converter this sampling method can be very useful in average current control in order to filter out the ripple current which will be more than % peak to peak of the average current. Analog filtering of this ripple would result in long delay times in the feedback and low bandwidth for the control, but with the timer underflow sampling this ripple current is filtered out digitally. The factors that will reduce the bandwidth of this digital control will now be the delays in the feedback loop, the effect of zero order hold (ZOH) sampling, and the computational speed of the DSP. The average current may be sampled at both the period match and timer underflow. This can be utilized so that all measurements, V in, V o, I and I are sampled at the same time. The average current in the inductor is sampled at timer underflow of timer. And the average current in the inductor is sampled at period match of timer which is the same as timer underflow of timer. Fig. b shows the principle of sampling and the pulse width modulation of the interleaved signals. Control design A digital average current sharing controller is implemented using symmetric PWM and timer underflow sampling. The structure of the control system is shown in Fig. a. The bandwidth of the current mode controller is reduced due to delays in the feedback loop and due to the effect of the zero order hold. inear control The control to inductor current transfer function for one of the parallel outputs is derived by averaging over one switching period and by linearization. Eq. shows the derived transfer function. R o is the load resistance, is the output filter inductance, and C is the output capacitor. H sys i() s () s = = d() s ( s + ) RoC s s + + RC C ( ) o () The system transfer function is then discretized by adding a zero order hold element and sampler at the sampling frequency of khz [9]. A discrete PI controller is then added to the system. It is the frequency response of the discretized system that is studied. The gain and time constant of the discrete controller is adjusted for sufficient open loop phase margin. The design criteria used is an open loop phase margin of at least with input voltages, V in, up to times the nominal input voltage. Predictive control With digital control, predictive methods may be used in order to compensate for the effect of zero order hold sampling and delays in the feedback loop. In [6] a general predictive control law is proposed. This method can be adapted to the average current sharing control of the ZVSQSW converter. With symmetric PWM and timer underflow interrupt sampling, the current in the inductor at the time, nt s, is given by the following equation. Vo Vo i[ n] = i[ n ] + dn Ts dn' Ts () where i [n] is the inductor current at the n th interrupt, V in is the input voltage, V o is the output voltage, d n is the duty cycle in the nth period, is the inductance, and T s is the sampling period. The duty cycle can also be described as d n =(d n ). Eq. () can be rewritten to

4 I PWM V in + I V o d n ' T s Compare d n+ ' T s T s T s PWM PWM H i (Z) H i (Z) Sampler Sampler H v (Z) V oref Sampler i[n] i (t) V in Vo i[n] I avg,ref V o i[n+] Digital control system Int Int Int Fig. : Digital average current sharing control Sampling and PWM with predictive control in o [ ] [ ] V V i n = i n + dn Ts Ts () The predicted current at the next interrupt will then be Vo i[ n+ ] = i[ n ] + ( dn + dn+ ) Ts Ts () The control objective would then be to control the predicted inductor current to the current reference value, i [n+]= i avg,ref. The next duty cycle,d n+, can now be calculated based on Eq. () Vo d = d + ( i + i [ n ]) + n n avg, ref Ts () Eq. () is the predictive control law for the average current sharing of the interleaved QSW converter. The controlled current waveform and the symmetric switching and sampling scheme is illustrated in Fig. b. Simulations of the converter control system The simulations are done in Simulink. The modeling of the converter is with the dynamic node technique [9]. Elements in the converter are modeled separately and connected together by capacitive nodes in the system. The control system is modeled with the standard elements of the Simulink library. The values of the circuit elements illustrated in Fig.a are the same through all simulations and laboratory tests. The values used are, ==µh, C=µH, R o =. Ω and V in =V. Simulations of the interleaved converter with linear control The simulation set up of the linear control system and the simulation result of a current reference step is shown in Fig.. The discrete transfer function of the current controller is based on the previously described design criteria and takes into consideration the delay due to the zero order hold.

5 RepSeq RepSeq Add Add Relay Relay Voltage input Delay Delay i_ g i_ g vcp Terminator Io vo dynode dual Sync Buck Converter /R Resistive oad ZeroOrder Hold PI output 6 Gain Gain Saturation Saturation num(z) z Discrete Transfer Fcn num(z) z Discrete Transfer Fcn. Add Add ZeroOrder Hold Coilcurrent [A] Outputvoltage[V] Coilcurrent [A].... Time [s] Current reference Fig. : Simulation set up and simulation result of a current reference step. Simulations of the interleaved converter with predictive control The simulation set up of the predictive control system is shown in Fig.. The simulation result of a current reference step is shown in Fig.6. With the output voltage measurement, the predictive current controllers are coupled together. This can result in oscillations. Therefore, the gain in the current feedback loop should be reduced in order to reduce the oscillations. The gain will not be according to the predictive control law, but close to. The performance of the controller is not significantly reduced by reducing the gain. Also a filter on the output voltage measurement will reduce oscillations between the two current controllers. Voltage input i_ RepSeq RepSeq Add Add Relay Relay Delay Delay g i_ g vcp Terminator Io vo dynode dual Sync Buck Converter /R Resistive oad 8e6s+ Transfer Fcn ZeroOrder Hold ZeroOrder Hold ZeroOrder Hold Pred Out Noise Gain Saturation z Unit Delay Add / Gain K Gain Saturation z Unit Delay Add Gain K Add Gain Add.8 Constant Fig. : Simulation set up of the predictive controller. The simulations were first done assuming no noise and no filter with reduced bandwidth on the voltage measurement. The result of the no noise simulation is shown in Fig.6a. In any practical circuit this will not be possible. A filter on the measurement will be needed and still then there will be some noise on the sampling input. Therefore a simulation with more realistic filter and noise properties is performed. The results of the predictive control with filter and noise is shown in Fig.6b.

6 6 6 Coilcurrent [A] Outputvoltage[V] Coilcurrent [A].... Time [s] Fig. 6: Simulation of a current reference step of the predictive controller without and with noise. A comparison of the reference step response of the linear control and the predictive control show that the predictive controller theoretically will have the faster step response. But, there is very little noise rejection in the voltage feedback loop of the output voltage and this leads to ripple on the output. The ripple can be reduced by filtering the voltage measurements more. But this will again reduce the performance. An outer linear voltage control loop would result in better noise rejection and the negative feedback loop will reduce the voltage ripple. Test setup and experiments Coilcurrent [A] Outputvoltage[V] Coilcurrent [A].... Time [s] A control board with a Texas Instruments F8 DSP is used to test the digital control techniques. Two parallel synchronous buck converters are coupled together. The input voltage, V in, the output voltage, V o, and the current, I x, in each of the two inductors is sampled. The current sharing is controlled using the two different digital control techniques implemented in the F8 DSP. The same circuit values as the values used in the simulations are used in the laboratory set up. The measurement of a current reference step to the linear control is shown in Fig.7. The measurement of a current reference step to the predictive control is shown in Fig.8. The measurement of the reference step to the linear control system show a transient as expected from simulations. The high frequency noise is rejected and the to parallel controllers work as two independent current sources. 6, Voltage[V], Current[A],,,,, Time[s] Vout[V] I_[A] I_[A] Fig. 7: Measured current reference step of linear controller oscilloscope data sampled data

7 6, Voltage[V], Current[A],,,,, Time[s] Vout[V] I_[A] I_[A] Fig. 8: Measured current reference step of predictive controller oscilloscope data sampled data The measurement of the reference step to the predictive control system, show that noise on the voltage measurement is reflected into the system. The noise on the voltage measurement results in ripple on average output current. Also, the performance of predictive control is the reduced due to the reduced bandwidth on the filtered output voltage measurement. Conclusion This paper has discussed and tested two digital control techniques for average current sharing of the interleaved synchronous buck converter. The results both by simulation and experiments show that any improvement in control performance by using a predictive control method is only possible when implementing a low noise high bandwidth measurement on the output voltage. Higher performance of the control is possible but not without the additional cost of better measurement hardware. References []. X. Zhou, P.. Wong, P. Xu, F.C. ee, A.Q. Huang, Investigation of Candidate VRM Topologies for Future Microprocessors, IEEE Transactions on Power Electronics, Volume:, No: 6, Nov. []. G.Hua, F.C.ee, SoftSwitching Techniques in PWM converters, Industrial Electronics, Control and Instrumentation, Proceedings of the IECON 9, p.676 []. S. Chen, W.T. Ng, HighEfficiency Operation of HighFrequency DC/DC Conversion for NextGeneration Microprocessors, Proceedings of IECON, Volume:, p. []. X. Zhou, P. Xu, F.C. ee, A.Q. Huang, A Novel CurrentSharing Control Technique for owvoltage High Current Voltage Regulator Module Applications, IEEE Transactions on Power Electronics, Volume:, No: 6, Nov.. []. S. Bibian, H. Jin, Digital Control with Improved Performance for Boost Power Factor Correction Circuits, Applied Power Electronics Conference and Exposition,. APEC. Sixteenth Annual IEEE, Volume:, 8 March [6]. J. Chen, A. Prodic, R.W. Erickson, D. Maksimovic, Predictive Digital Current Programmed Control, IEEE Transactions on Power Electronics, Volume: 8, No:, Nov.. [7]. N. Mohan, T.M. Undeland, W.Robbins, Power Electronics Converters Applications and Design, nd Edition, John Wiley Sons, 99 [8]. R.W. Erickson, Fundamentals of Power Electronics, th Printing, Kluwer Academic Publishers, 999 [9].Flinders, F.; Oghanna, W.; Simulation of a complex traction PWM rectifier using SIMUINK and the dynamic node technique, Industrial Electronics, Control and Instrumentation, 997. IECON 97. rd International Conference on Volume, 9 Nov. 997 Page(s):78 7 vol.

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