Voltage-Mode Grid-Tie Inverter with Active Power Factor Correction

Transcription

1 Voltage-Mode Grid-Tie Inverter with Active Power Factor Correction Kasemsan Siri Electronics and Power Systems Department, Engineering and Technology Group, The Aerospace Corporation, Tel: he Aerospace Corporation 2009 Patent-Pending

2 Motivation for Voltage-Mode Grid-Tie Inverter Conventional grid-tie inverter operates in a current-source mode: Require fast response of the innermost control loop that regulates the waveform of the inverter s output current, Not easy to compensate the current-mode control loop to be stable, Be susceptible to interactions with the back-end EMI filter and the grid s non-ideal voltage source characteristics. Conventional grid-tie inverter for solar array does not provide active power factor correction (APFC): Only allowed to operate during sunlight periods, Deliver the in-phase output current with respect to the grid voltage, Not fully utilized the capability of active power factor correction particularly during the periods of no sunlight. Voltage-Mode grid-tie inverter for solar array potentially offers APFC function without increasing the power component count. Page 2 Patent-Pending

3 Motivation for Active Power Factor Correction Conventional grid-tie inverter only works during sunlight (day time): Only designed for power transfer from the solar array to a utility grid, Controlled to deliver an in-phase current into the grid, Controlled to provide 0-A reactive current, No active power correction for a reactive load across the grid voltage. Grid-tie inverters should be fully utilized during both day time and night time: Optionally providing active power factor correction which maximizes the power factor for a given set of AC loads sharing the same utilitygrid voltage across the inverter s output. Page 3 Patent-Pending

4 Difficulties of Conventional Current-Mode Inverter (1) Distortion of current waveform, particularly when the utility grid voltage crosses 0-V. (2) As inverter current increases, the system performance decreases toward an instability of the innermost control loop. localized bursts of high frequency oscillation superimposed on the AC current waveform of the utility frequency. (3) Difficult to design the back-end EMI filter that minimizes or avoids undesirable interactions with the inverter response. Higher control crossover frequency is needed for the fidelity of the sinusoidal waveform of the inverter output current, resulting in a potential interaction with the resonant frequency of the EMI filter. Page 4 Patent-Pending

5 INVERTER SYSTEM BLOCK DIAGRAM Convert DC power from solar array to an AC inverter output current, Provide a proper phase control of the inverter output voltage to remove the reactive component from the utility grid current, Track peak power delivered by the solar array at night, Maintain 0-a reactive component in the utility grid current during both daytime and night-time periods. Page 5 Patent-Pending

6 INVERTER SYSTEM CONTROL CONCEPT Six basic blocks work together for reliable DC-to-AC power conversion: 1. SINE-WAVE Regulation Controller with PWM Output 2. Active Power Factor Correction and Harmonic Cancellation Controller 3. 0-ADC Regulation Controller 4. Maximum Power Tacking (MPT) & Input Voltage Regulation Controller 5. Non-MPT Mode Controller 6. Protection Controller Page 6 Patent-Pending

7 Phase-Shift Control & Sinusoidal Profile Regulation Active power factor correction is achieved by the phaseshift control. Being equivalent to Independent MPT Sharing only one common MPT controller Actively performing an MPT control for one power source at a time while holding the most recently tracked source voltages of the remaining power sources After proper phase-shifting of the sinusoidal reference signal, it is multiplied with the DC command signal V CON Forming a sinusoidal profile for production of the inverter output voltage through a voltage-mode PWM scheme, Fulfilling other control objectives such as Maximum Power Tracking and/or Inverter Input Voltage Regulation Page 7 Patent-Pending

8 Harmonic Cancellation Method To achieve the AC grid current having 0-A harmonic or negligible harmonic content, a harmonic cancellation term, v INac (t)/v IN (t), is inserted and the dutyratio can be expressed as d PWM ( t ) = 0. 5 B + k sin( w t + f ) 1 - v V INac IN ( t ) ( t ) where v INac (t) is all of the AC components that are superimposed on the DC component V INdc of the inverter input voltage, V IN (t), and V IN (t) = V INdc + v INac (t). Block 210 shown in Fig. 1 also accepts the inverter input voltage V IN (t) from which the harmonic cancellation term is derived and superimposed onto the ideal sinusoidal reference waveform such that the composite reference signal SINE_AC leads to the duty-ratio signal that satisfies the equation above. Page 8 Patent-Pending

9 0-ADC Regulation Controller The 0-ADC regulation controller 260 ensures the 0-ADC average value of the inverter output current during steady state. providing an integral-lead compensation to the feedback inverter output current signal I O and delivering the counter balance signal V OFF to be added to the composite sinusoidal signal within the controller block 200. Page 9 Patent-Pending

10 VOLTAGE-MODE SINE-WAVE REGULATION CONTROLLER WITH PWM OUTPUT Each of the three source voltages: V1, V2, and V3 is actively controlled by the common MPT controller one voltage at a time, while holding their most recently tracked source voltages of the remaining sources. Page 10 Patent-Pending

11 PWM CONTROL FOR SINE-WAVE VOLTAGE V GS1 = VGS 4 = PWM SD V where GS 2 d PWM = VGS 3 = PWM SD d ( t) = k sin( wt) PWM Ton = + and k 0.5 T Page 11 Patent-Pending

12 SIMULATED INVERTER RESPONSE Amplitude of the capacitive load current (60-degree lead) was varied from 10 ma to 14 A while the inverter output power is kept constant at 200 W. When the load current, I LOAD, is zero or small (i.e. 10 ma), nearly all of the inverter output power is transferred to the utility grid and the amplitude of grid current I AC is around 3.6 A at time = 4s. As I LOAD increases, I AC is decreased as more inverter power is transferred to the load and less inverter power to the grid while the inverter transferred power P IN of 200 W is sustained. Five following plots of the detailed responses from top to bottom (in the lower plot area) are revealed: V IN : the inverter input voltage, I IN : the inverter input current, P IN : the inverter input power (its moving-average), I LOAD : the load current, and I AC : the grid current being paired with V AC The bottom left plot: I AC and V AC are in-phase, signifying that the excess inverter power above the load demand is absorbed by the utility grid. The bottom right plot: I AC and V AC are out-of-phase, signifying that the grid provides an extra power above the inverter 200-W output power to fulfill the heavy load demand. Page 12 Patent-Pending

13 Inverter Response (Inductive Load) without Harmonic Cancellation V LOAD, I LOAD, P IN, P LOAD, and I AC are simulated at around time t = 11s for an inductive load (60-degree lag). For 10.95s < t < 11.05s, the inductive load consumes the same power as that delivered by the inverter output P IN, consequently causing I AC at the utility frequency to be reduced to nearly 0 A. Due to distributed imperfections in the inverter power stage and control, the grid current exhibits the third harmonic frequency (180-Hz) with respect to the grid frequency (without the harmonic cancellation). Page 13 Patent-Pending

14 Inverter Response (Capacitive Load) without harmonic Cancellation V LOAD, I LOAD, P IN, P LOAD, and I AC are simulated at around time t = 11s for a capacitive load (60-degree lead). For 11.15s < t < 11.25s, the capacitive load consumes the same power as that delivered by the inverter output P IN, consequently causing I AC at the utility frequency to be reduced to nearly 0 A. Due to distributed imperfections in the inverter power stage and control, the grid current exhibits the third harmonic frequency (180-Hz) with respect to the grid frequency (without the harmonic cancellation). Page 14 Patent-Pending

15 Inverter Response Before and After Harmonic Cancellation Before After Before the harmonic cancellation is included, the peak-to-peak grid current is ma which mostly contains the third harmonic frequency (180 Hz) as shown on the bottom left plot. After the harmonic cancellation term is included as shown in chart #6, the third harmonic content is almost totally eliminated, leaving only the less than 100-mA peak-topeak current which occurs at the fundamental frequency (60 Hz) as shown on the bottom right plot of the figure. Page 15 Patent-Pending

16 Maximum Power Tracking Controller Two Major Operational Modes (MPT and Non-MPT): In MPT mode, Input Voltage Regulation (IVR) regulates the inverter input voltage at the solar array peak power voltage. In Non-MPT mode, the inverter input voltage is above the solar array peak power voltage to reduce the solar array power as needed. Page 16 Patent-Pending

17 Change in Peak Power Voltage (Between 20 V and 30 V) Inductive load of A (RMS) or 8A (amplitude), utility grid absorbs excess array power, i.e. I AC and V AC are in-phase. Inductive load of slightly below 200 W, leaving about 100 W of the excess inverter output power to be absorbed by the utility grid. The array peak power of 300 W is continuously tracked despite the change in the peak power voltage between 20V and 30V. Page 17 Patent-Pending

18 Change in Peak Power Voltage (Between 20 V and 30 V) Inductive load 14A, utility grid fulfills the load demand while the array peak power (300 W) is tracked and delivered to the load. Grid voltage and current are out of phase, revealing that the utility grid provides extra power to fulfill the load demand which exceeds the 300-W solar array peak power. Page 18 Patent-Pending

19 Simulation of the Grid-Tie Inverter Power System With MPT Control and Active Power Factor Correction PSPICE simulation verifies that the following novel features of the inverter system control: The proper phase-shift method that results in the unity power factor regardless of the load type being terminated across the inverter output (resistive, inductive, or capacitive). The harmonic cancellation method that effectively eliminates or significantly reduces harmonic content from the inverter output voltage and current, particularly at the third or higher harmonic frequencies. The 0-ADC regulation control which ensures that the inverter output current possesses no DC component, thus preventing magnetic saturation from occurring in the inverter isolation transformer. Page 19 Patent-Pending

20 CONCLUSION PSPICE simulation has validated the novel system controller for a voltagemode grid-tie inverter with active power factor correction (APFC). APFC between the grid voltage and current was achieved by a proper phase-shift control method regardless of the inverter load type The harmonic cancellation circuit has demonstrated the control ability to eliminate or significantly reduce harmonic content from the grid voltage and current, particularly at the third or higher harmonic frequencies. Under the non-linear characteristics of the input power source and the non-ideal impedance characteristics of the utility grid, The voltage-mode inverter is much easier to be implemented than the current-mode inverter, particularly for obtaining the unity power factor being observed by the utility grid. Finally, the 0-ADC regulation controller was also validated, preventing magnetic saturation from occurring at the inverter isolation transformer. Page 20 Patent-Pending

21 Maximum Power Tracking Controller Two Major Operational Modes (MPT and Non-MPT): In MPT mode, Input Voltage Regulation (IVR) regulates the inverter input voltage at the solar array peak power voltage. In Non-MPT mode, the inverter input voltage is above the solar array peak power voltage to reduce the solar array power as needed. Page 21 Patent-Pending ISIE 2015

22 TYPICAL I-V & P-V CHARACTERISTICS OF SOLAR ARRAY Page 22 Patent-Pending

23 THREE MAJOR STATES OF SOLAR ARRAY POWER Page 23 Patent-Pending

24 APPENDIX B: MPT Controller Page 24 Patent-Pending ISIE 2015

25 AC ARRAY VOTLAGE AND POWER RIPPLE WITH RESPECT TO UTILITY FREQUENCY Page 25 Patent-Pending

26 MPT CONCEPTUAL BLOCK DIAGRAM Page 26 Patent-Pending

27 MPT IMPLEMENTATION DIAGRAM BASED ON DISCRETE LOGIC Page 27 Patent-Pending

28 Change in Peak Power Voltage (Between 20 V and 30 V) Inductive load of A (RMS) or 8A (amplitude), utility grid absorbs excess array power, i.e. I AC and V AC are in-phase. Inductive load of slightly below 200 W, leaving about 100 W of the excess inverter output power to be absorbed by the utility grid. The array peak power of 300 W is continuously tracked despite the change in the peak power voltage between 20V and 30V. Page 28 Patent-Pending ISIE 2015

29 Change in Peak Power Voltage (Between 20 V and 30 V) Inductive load 14A, utility grid fulfills the load demand while the array peak power (300 W) is tracked and delivered to the load. Grid voltage and current are out of phase, revealing that the utility grid provides extra power to fulfill the load demand which exceeds the 300-W solar array peak power. Page 29 Patent-Pending ISIE 2015

30 Page 30 Patent-Pending

31 Simplified Concept of Inverter Model Page 31 Patent-Pending

32 The Simplest System of Closed-Loop Controlled Inverter Page 32 Patent-Pending

33 Simplified Phasor Diagram with Inductive Load Page 33 Patent-Pending

34 Simplified Phasor Diagram with Capacitive Load Page 34 Patent-Pending

35 Model of Strong-Power Inverter and Utility Grid Simplified equivalent circuit consisting of an inverter, load, and a utility grid with two phasor diagrams of AC voltages and currents when excess inverter power above the load demand is absorbed by the utility grid; the lower-left phasor diagram for an inductive load and the lowerright phasor diagram for a capacitive load. Page 35 Patent-Pending

36 Model of Weak-Power Inverter and Utility Grid Simplified equivalent circuit consisting of an inverter, load, and a utility grid with two phasor diagrams of AC voltages and currents when extra power is provided by the utility grid to fulfill the load demand above the inverter output power; the lower-left phasor diagram for an inductive load and the lower-right phasor diagram for a capacitive load. Page 36 Patent-Pending

37 PHASE-SHIFT CONTROL Page 37 Patent-Pending

38 Extraction of Harmonic Cancellation Term Page 38 Patent-Pending

39 Average Model of the Bridge Switching Network Q1 and Q4 are concurrently switched with their identical ON time, T ON, which is proportionally to the modulation duty ratio D = T ON /T, whereas Q2 and Q3 are always switched in a complementary fashion with Q1 and Q4. <V(VOP)> = D*V IN <V(VON)> = (1-D)*V IN <V(VOP) V(VON)> = (2*D 1)*V IN Page 39 Patent-Pending

40 Large-Signal Average Model of the Bridge Switching Ckt. Page 40 Patent-Pending

41 Average Model of BI-POLAR PWM Modulator d(t) = V CPWM / VR d(t) = T ON (t) / T Where V CPWM = V CON sin(wt) *( 1 - v inac (t) / V IN (t) ) Page 41 Patent-Pending

42 Average Model of SINGLE POLAR PWM Modulator d(t) = V CPWM / VR d(t) = T ON (t) / T Where V CPWM = V CON sin(wt) *( 1 - v inac (t) / V IN (t) ) Page 42 Patent-Pending

43 Homework: (1) Prove that V(VOP, VON) contains no product term sin(wt)*sin(2wt) with harmonic cancellation. (2) Prove that sin(wt)*sin(2wt) contains two frequencies (w 1 and w 2 ) and (3) What are the values of w 1 and w 2? where v inac (t) = V m sin(2wt) V IN (t) = V INDC + V m sin(2wt) V CPWM = V CON * V(SINE_AC) V(SINE_AC) = sin(wt) *( 1 - V m sin(2wt)/ V IN (t) ) Page 43 Patent-Pending

44 PWM SWITCHING SIGNAL BASED ON BI-POLAR MODULATION V GS1 = VGS 4 = PWM SD V where GS 2 d PWM = VGS 3 = PWM SD d ( t) = k sin( wt) PWM Ton = + and k 0.5 T Page 44 Patent-Pending ISIE 2015

45 Large Signal Average Model of Power Switching Bridge (Bi-Polar Modulation Scheme) Page 45 Patent-Pending

46 PWM SWITCHING SIGNAL BASED ON SINGLE POLAR MODULATION V GS 1 V GS 2 = ( PWM * SQW) SD = PWM + SQW SD V GS 3 V GS 4 = ( PWM * SQW) SD = PWM + SQW SD d PWM ( t) = k sin( w t) Page 46 Patent-Pending ISIE 2015 where d PWM Ton = + and k T 1.0

47 ALTERNATIVE PWM SWITCHING SIGNAL BASED ON SINGLE POLAR MODULATION Page 47 Patent-Pending ISIE 2015 PWM A = PWM + SQ2T PWM B = PWM + SQ2T PWM 1 = PWM A SQ _ 60 PWM 2 = PWM B SQ _ 60 V V where = PWM SD V = PWM 1 GS1 1, d PWM GS 2 SD = PWM 2 SD and VGS 4 = PWM 2 GS3, Ton = + and k T SD 1.0

48 Large Signal Average Model of Power Switching Bridge Single Polar Modulation Page 48 Patent-Pending