An Overview of Filters used in Receiver of Software Defined Radio

Transcription

1 An Overview of Filters used in Receiver of Software Defined Radio 1 Archana Charkhawala, 2 M.M.Mushrif 1 Dept. of ET, Priyadarshini College of Engineering, Nagpur, Maharashtra, India 2 Yashwantrao Chauhan college of Engineering, Nagpur, Maharashtra, India Abstract In this work, we deal with the requirement and design of a decimation filter to be used in Software Defined Radio (SDR) receiver. The paper outlines architecture considerations for multistandard SDR receivers. Also, it describes the requirement of digital filters and design steps used in the receiver. Standards like GSM, DECT, EDGE. CDMA, WCDMA, Wimax specifications are mentioned to be supported by Multistandard, Multifunction, Multimode, Multiband SDR. II. SDR Receiver Architectures A multistandard SDR system must meet the performance requirements for each standard and adjust to the different channel bandwidths and carrier frequencies. SDRs are radios that provide software control of a variety of modulation techniques, wide-band or narrow-band operation, communications security functions such as hopping, and waveform requirements of current and evolving standards over a broad frequency range. Keywords SDR, ADC, Digital Down converter (DDC), Direct digital Synthesizer(DDS), Antialiasing filter, Decimation filtering, wireless communications standards. I. Introduction After being the subject of speculation for many years, a Software- Defined Radio (SDR) receiver concept has emerged that is suitable for Wireless communication. SDR is multistandard, multiband, multimode concept which would help realize a system-of-systems concept and provide significantly greater communications capabilities in a single device that are available today. The last few years, however, have seen tremendous progress in clearing up the convoluted RF/digital relation, as well as the evolution of technology and devices. Digital Technology has become easy to implement on basis of superheterodyne systems. Superheterodyne receivers tune in different stations simply by adjusting the frequency of the local oscillator on the input stage, and all processing after that is done at the same frequency, i.e. IF. Furthermore, as digital technology is applied closer and closer to the RF end, other techniques such as varying IF frequency and filter tuning can be done with simple reprogramming as well. The digital down converter (DDC) is a key component of a digital radio. The DDC performs the frequency translation necessary to convert the high sample rates down to lower sample rates for further and easier processing. The technique greatly reduces the amount of effort required for subsequent processing of the signal without loss of any of the information carried. Historically it has been performed in analogue before digitizing the baseband signal for the DSP. Given this facility, which involves high complexity, it becomes impossible to stay with single sampling rate and so altering the sampling rate at different stages is required for low cost DSP hardware. Thus variable sampling rates i.e. Multirate Digital Signal Processing is required. In recent years there has been tremendous progress in the multirate processing of digital signals. Unlike the single- rate system, the sample spacing in a multirate system can vary from point to point. This often results in more efficient processing of signals because the sampling rates at various internal points can be kept as small as possible. Unfortunately, this also results in the introduction of a type of error, i.e., aliasing, which should somehow be cancelled eventually. The basic building blocks in a multirate digital signal processing (DSP) system are decimators and interpolators. Fig. 1: SDR Receiver architecture Many receivers architectures have been proposed: the conventional super-heterodyne architecture, the low intermediate frequency (Low-IF) architecture, the wideband intermediate frequency with double conversion (WIF) architecture and direct homodyne conversion. A. Superheterodyne Receiver The conventional super-heterodyne receiver has very good performance due in part to its discreet Components. It uses an external image reject (IR) filter and an external, narrow-band, IF channel filter within the receive path [2]. B. Low IF architecture Low IF receivers architecture as shown in Fig. 2 below are one option for cost-effective SDR front ends. They are very adaptable to various standards and have good selectivity and sensitivity. Local oscillator leakage can be suppressed by placing the LO frequency outside the band of interest, allowing the upstream (preventing LO radiation from the antenna) and downstream (preventing the LO image from appearing in the basebanded signal) bandpass filters to suppress its contribution. The final I/Q demodulation stage is a good candidate for digital implementation, replacing its local oscillator and 90 phase shift network with a digital waveform generator. This eliminates phase error and oscillator leakage problems, and is known as a digital-if receiver. Fig. 2: low IF Receiver Architecture It simplifies the pre-mixer RF filtering Because signal processing In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 189

2 is at low frequency, there is a potential for implementing the IF filter in active analogue circuitry and reducing the power consumption, which is a reason for its popularity. C. Wideband IF Receiver architecture The Wide-Band Intermediate Frequency With Double Conversion (WIF) architecture has no discreet components within the receive path. Because the channel filtering is done at baseband instead of at IF, a wide-band IF filter can be used, eliminating the need for an off-chip IF filter. With this architecture, channel filtering can be done digitally, allowing the receiver to adapt to multiple communication standards. This approach requires a high dynamic range A/D converter that can adapt to the different channel bandwidths and sampling ratios that the different standards require. In contrast to the super heterodyne, the WIF has a fixed LO1 and a variable LO2. A fixed LO1 can use a higher reference frequency, and therefore have a higher phase-locked loop (PLL) bandwidth and lower phase noise. This allows the phase noise requirement for LO2 to be relaxed. This architecture uses image-reject mixers, eliminating the off-chip IR filter. D. Direct Conversion Homodyne Receiver Fig. 3: Direct conversion Homodyne Architecture [11] This architecture translates frequency to baseband directly to eliminate external components within the receive path. It can be programmed for a multi-standard solution since the local oscillator (LO) is tuned to the same frequency as the incoming RF frequency to select different standards. Here, the incoming RF signal is multiplied by one sided LO signal of a frequency equal to the centre frequency of the desired signal band, and hence does not suffer from image signal interference. The downconversion with a one sided LO signal is achieved by a quadrature mixer in which the incoming signal is multiplied by two LO signals with 90 degrees out of phase. These in-phase and quadrature phase components are then lowpass filtered and sent to ADCs. The digital signal from ADC is given to digital signal processing section for demodulation. The direct-conversion homodyne approach shown in Fig.3 has no external components within the receive path. Because the channel filtering is performed at baseband, unlike the superheterodyne, it is possible to design baseband circuits for the homodyne receiver that are multistandard capable, however, the noise and DC offset must be reduced to achieve adequate dynamic range. It is also called as zero IF. III. DDC Over Analog Techniques All paragraphs must be indented. All paragraphs must be justified, i.e. both left-justified and right-justified. 190 International Journal of Electronics & Communication Technology Fig. 4 Direct Digital Converter (DDC) Digital Down Conversion(DDC) A fundamental part of many communications systems. it is a technique that takes a band limited high sample rate digitized signal, mixes the signal to a lower frequency and reduces the sample rate while retaining all the information. Digital radio receivers often have fast ADC converters to digitize the band limited RF or IF signal generating high data rates; but in many cases, the signal of interest represents a small proportion of that bandwidth. To extract the band of interest at this high sample rate would require a prohibitively large filter [1]. A DDC allows the frequency band of interest to be moved down the spectrum so the sample rate can be reduced, filter requirements and further processing on the signal of interest become more easily realizable. A. Fast ADC Requirements The sigma-delta (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless systems because of their superior linearity, robustness to circuit imperfections, inherent resolution-bandwidth trade off and increased programmability in digital domain. A highly linear sigma-delta modulator for multi-standard operation that can achieve high resolution over a wide variety of bandwidth requirements remains challenging. A reconfigurable ADC is a promising solution to keep the power dissipation as low as possible [1]. The concept of the DDC is to sample the whole input signal and to use digital techniques to reduce the data. However, that may require an unrealistically fast ADC. For example, Nyquist s theory states that we should sample at a rate at least double the bandwidth of interest. B. Complex Oscillator The Local Oscillator generates digital samples of a sine (or cosine) wave having the same frequency as that of the desired radio channel. The output frequency of the local oscillator is dependent upon the channel selected by the user. The Local Oscillator produces a sinusoidal sample at exactly every output sample of the A/D converter, therefore it is driven by the same sampling clock of the A/D converter. The ADC and Direct Digital Synthesizer(DDS) are already available as tools in most of the software and kits. DDS implements the function of the local oscillator in the block diagram. C. Complex Multiplier The Digital Mixer is simply a 2 inputs multiplier which outputs the product of two digital samples. Digital output samples from the A/D are mathematically multiplied with digital samples of a sine (or cosine) signal from the local oscillator. Note that the input samples from the A/D and sine (cosine) samples from the Local Oscillator are generated at the same rate fs (the sampling frequency of the A/D). The multiplication is sample-by-sample and thus the mixer produces samples at the same rate of fs. Note that unlike analog mixer which produces many unwanted mixer products, the digital mixer only produces the sum and

3 the difference frequency signals [4]. Fig. 5: the effect of mixing Fig. 5 illustrates the effect of mixing RF signal with a local oscillator signal. The mixer shifts the spectrum of the RF portion at the frequency of the local oscillator down to DC. D. Low Pass filter pass filter can be used to filter out unwanted high frequency components. The filter accepts digital samples from the output of the Mixer at the sampling frequency, fs. It employs digital processing techniques to implement an FIR (finite impulse response) filter transfer function. The filter passes all frequencies from 0 up to a cutoff frequency equal to the bandwidth of the message signal of interest, and rejects all frequency above that cutoff frequency. Fig. 6: the effect of band limited filtering Fig. 6 illustrates the effect of band-limit filtering in the frequency domain. As can be seen, the filter only captures frequencies below its cutoff frequency and rejects all other. Note that the mixer has translated the input signal down to 0 Hz, thus allowing the filter to select only a narrow slice of the RF spectrum corresponding to a channel of interest. i) Antialiasing filter: A/D Converters are usually operated with a constant sampling frequency when digitizing analog signals. By using a sampling frequency (Fs), typically called the Nyquist rate, all input signals with frequencies below Fs/2 are reliably digitized. If there is a portion of the input signal that resides in the frequency domain above Fs/2, that portion will fold back into the bandwidth of interest with the amplitude preserved. The phenomena makes it impossible to discern the difference between a signal from the lower frequencies (below Fs/2) and higher frequencies (above Fs/2) [7]. Aliasing is the most important side effect of Sample Rate Converter (SRC) which must be mitigated by properly designed filters. This is also the most concern of the filter design issue in SDR receiver front-end [12]. When the wanted channel s bandwidth is much less than the sample rate, the sinc filter can protect it from aliasing. The anti-aliasing filter (AAF) gets rid of all interferers and blockers that could be folded over the signal after sampling operation. E. Decimator In software-defined radio (SDR) receiver, high-quality clocks with very low jitter are required. Hence, it is reasonable to provide only one fixed master clock in practical SDR application. However, different standards have different master clock rates. Under this circumstances, digital sample rate conversion (SRC), the purpose of multirate signal Processing can be used as an important method to provide different clock rates. Multirate Signal Processing consists of using different sample rates within a system to achieve computational efficiencies that are impossible to obtain with a system that operates on a single fixed sample rate. This leads to the concept of changing the sampling rates downward (decimation) to a lower sampling rate; filtering the signal and then changing the sampling rate upward (interpolation) to the original sampling rate. Reducing the sampling rate requires an anti-aliasing filter prior to the decimation to a lower sampling rate. Increasing the sampling rate requires an anti-imaging filter after the interpolation [7]. Receiver architectures must be chosen that minimize the need for filtering since low-loss, broadband tunable filters are not practical in today s technology. i) Cascaded Integrator Comb (CIC) Filter:The cascaded Integrator Comb (CIC) or Hogenauer filter is a class of FIR filter. it is a multiplierless filter architecture that is extremely important for implementing area efficient high sample rate changes in Digital Down Converters (DDC) and Digital Up Converters (DUC)[10]. Generally FIR filters are preferred over IIR filters in multirate (decimating and interpolating) systems Because only a fraction of the calculations that would be required to implement a decimating or interpolating FIR in a literal way actually needs to be done. Since FIR filters do not use feedback, only those outputs which are actually going to be used have to be calculated. Therefore, in the case of decimating FIRs (in which only 1 of N outputs will be used), the other N-1 outputs don't have to be calculated. Similarly, for interpolating filters (in which zeroes are inserted between the input samples to raise the sampling rate) we don't actually have to multiply the inserted zeroes with their corresponding FIR coefficients and sum the result; the multiplication-additions that are associated with the zeroes are just omitted (because they don't change the result anyway). In contrast, since IIR filters use feedback, every input must be used, and every input must be calculated because all inputs and outputs contribute to the feedback in the filter. CICs are simply boxcar filters implemented recursively cascaded with an upsampler or downsampler. These characteristic make CICs very useful for digital systems operating at high rates. Boxcar FIR filters are simply filters in which each coefficient is 1.0. Therefore, for an N-tap boxcar, the output is just the sum of the past N samples. Because boxcar FIRs can be implemented using only adders, they are of interest primarily in hardware implementations, where multipliers are expensive to implement. IV. An Overview Of DIGITAL RECEIVER In a wireless receiver, pushing the digital Signal processor (DSP) to the "front end" also requires the usage of an analog to digital converter (ADC)to convert an intermediate- frequency(if) or In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 191

4 RF analog signal into Discrete time signal. Fig. 7 shows a the block diagram of digital receiver. It selects and filters a single Channel from a fixed signal bandwidth. the sample rate of the real and quadrature components of the signal after the A/D converter must be higher if the input signal is complex- The high resolution Numerically Controlled Oscillator's (NCO) signal output mixes with the sampled signal and translates the input signal band of interest from IF to baseband. The CIC Filter is used as a decimation filter in a receiver to reduce the initial data sample rate down to a lower desired sample rate.. An additional filter is normally needed to eliminate the side lobes and compensate for the pass band deformations caused by the CIC filter. From this example, it is clear that the decimation filter plays an important role in a digital receiver implementation[9].. In other words we can use a multi-rate approach in which the signal is first decimated to a much lower sample rate using a less computationally intensive filter. Then the signal is cleaned up with a second more complex filter working at the decimated sample rate [2]. VI. Goals Of Sdr For very wide frequency coverage, the RF hardware may need to be built in separate portions of circuitry dedicated to particular frequency ranges. The table 2 shows the goals for SDR with the frequency ranges according to the standards. Table 2 : Receiver Frequency bands[6] Center Frequency Band Standard [MHz] G, 2G, ISM (11g/b,..) UNII (11a,cordless) Fig. 7: Digital Receiver i) Design Techniqies for Multirate filters : Polyphase channelization is essential for a variety of applications involving bandwidth reduction and signal separation [3-4]. Filter level reconfigurability can be achieved by dynamically changing the interpolation and decimation factors M and D respectively of the modal filter, to extract channels of different bandwidths. polyphase decomposition results in reduction of computation complexity in FIR filter realization [5]. V. Complexity s of SDR The SDR radio may be more or less complex than the classical approach it replaces depending upon the frequency range and modulation types it has to handle(as shown in Table I). 1. Good enough to receive one channel at a time, but from any band, with any channel bandwidth, and any modulation 2. Tunes channel of interest to zero IF 3. Wideband receiver (no RF preselect) [6]. Table 1 : SDR Modulation scheme and Bandwidth Standard Modulation Scheme Channel Bandwidth(MHz) GSM GMSK 0.2 EDGE 8PSK 0.2 Bluetooth GFSK 1 CDMA IS95 QPSK CDMA 1.25 WCDMA / QPSK/16QAM CDMA CDMA a/g OFDM n OFDM International Journal of Electronics & Communication Technology Table 3 : Frequency Specifications for filter design[8] Standard Frequency in Channel spacing in Input Sampling Frequency in GSM DL: UL: WCDMA DL: UL: WLANa WLANb WLANg WiMax References [1] Gio Cafaro, Tom Gradishar, Joe Heck, Steve Machan, Geetha Nagaraj, Scott Olson, Raul Salvi, Bob Stengel, Bill Ziemer, A 100 MHz 2.5 GHz Direct Conversion CMOS Transceiver for SDR Applications Motorola Labs, Plantation, FL, 33322, USA 2007 IEEE Radio Frequency Integrated Circuits [2] Paul Gray, Carol J. Barrett Thesis, Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications, Thesis, Master of Science in Electrical Engineering University of California, Berkeley [3] S Gregory Harrison, Ambrose Sloan, Wilbur Myrick, Joe Hecker, David Eastin Polyphase Channelization Utilizing General-Purpose Computing On A GPU By SAIC, Innovative Technology Office, Chantilly, VA, USA.Proceedings of the SDR 08 Technical Conference and product Exposition [4] Lee Pucker, Channelization Techniques For Software Defined Radio (Spectrum Signal Processing Inc., Burnaby, B.C, Canada). [5] N. Vun, A. B. Premkumar, IEEE ADC Systems for SDR Digital Front-End pp [6] Asad A. Abidi, The Path to the Software-Defined Radio Receiver, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5,pg no MAY 2007

5 [7] Francisco J. A. de Aquino, Carlos A. F. da Rocha, Leonardo Silva Resende, Design of CIC Filters for Software Radio System,pp , vol.3 ICASSP 2006 IEEE. [8] Shahana T. K., Babita R. Jose, K. Poulose Jacob, Sreela Sasi, Decimation Filter Design Toolbox for Multi- Standard Wireless Transceivers using MATLAB, International Journal of Information and Communication Engineering 5: [9] Asad A. Abidi, Evolution of the Software-Defi ned Radio (SDR) Receiver, Electrical Engineering Department University of California, Los Angeles, ISSCC Girafe [10] PP Vaidyanathan, Multirate Digital Filters, Filter Banks, Polyphase Networks, and Applications:A Tutorial, Proceedings Of The Ieee, Vol. 78, No. 1, January 1990,pp [11] Adel Ghazel, Lirida Naviner, Khaled Grati, On Design and Implementation of a Decimation Filter for Multistandard Wireless Transceivers. [12] Bonnie C. Baker, Anti-Aliasing, Analog Filters for Data Acquisition Systems Microchip Technology, Inc AN699. In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 193