# Exploring Decimation Filters

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2 have a better understanding how decimation filters operate, we created an example. Note that in a delta-sigma converter, the decimation filter is placed after the modulator. Assume a first-order delta-sigma modulator is used to generate a bit stream at the modulator s output (Figure 1). According to Figure 1, the 16 consecutive samples obtained from the modulator are added and the sum is divided by 16 to get the average value of reconstructed input. In this example, for an input of 0.56V, 9 out of 16 bits are high. Thus, the ratio of highs to total bits constructs a value that is very close to the input signal. This example shows that in order to compute the average of D samples, we need D-1 summation and a multiplication by 1/D (which indeed is dividing the sum by D). To get the average of D samples we can write (Equation 1): Y(n)=[x(n)+ x(n-1)+ x(n-2)+ x(n-3)+ x(n-4)+ + x(n-d+1)]/d Equation 1 can be written in Z-Domain (Equation 2): Y(z)=[X(z)+ X(z).z -1 + X(z).z -2 +X(z).z X(z).z 1-D ] / D Now Equation 2 can be simplified to Equation 3: Eq.1 Eq.2 Y(z)=X(z).[1+ z -1 + z -2 + z z 1-D ] / D Eq. 3 The transfer function H(z) can be calculated as Equation 4: Eq. 4 Figure 2 Conceptual implementation of Equation 3. Equation 4 can be simplified in the general form of Equations 5 and 6: Eq. 5 Eq. 6 To avoid D-1 summations and multiplication, commonly a CIC filter is used to achieve a similar result. A CIC filter typically is made of an integrator followed by a subtractor. Before the signal is sent to a Comb filter, it is decimated (down sampled) by a factor of M. Then the down-sampled data is passed to the Comb section. The architecture of a single-stage CIC filter is shown in Figure 3. Figure 4 shows the diagram for a multistage CIC filter. In a CIC filter architecture, note that there is no multiplication (multiplier), as it is required if you intend to implement Equation 6 directly. 34 High Frequency Electronics

3 Figure 3 Conceptual diagram for singlestage CIC filter. Figure 4 Illustration of a multistage CIC filter. In fact, the lack of need for a multiplier is an advantage of this type of filter. The transfer function of the first-order filter shown in Figure 1 can be written as Equations 7 through 8b: Eq.7 Eq.8A Eq.8B Looking into the transfer function of a CIC filter, the transfer function of integrator (accumulator) and subtractor (comb) is recognizable (Equations 9 10): Eq.9 If a multistage configuration (Figure 4) is used to implement a CIC filter, its transfer function can be written as Equation 11: Eq.10 Eq.11 where, K is the number of stages used in the filter. As mentioned earlier, a decimation operation takes place right after the integrator stage, so this must be taken into account. For a decimation factor of M, the transfer function should be revised as Equation 12: Eq.12 Note that in Figures 3 4, the integrators operate at a high sampling rate (fs), whereas the Comb filter operates at a down sampled frequency (fs/m). The CIC transfer function has the geometric series form of sum, which can be simplified as Equation 13: Eq High Frequency Electronics

5 Figure 7 The resulting bit-stream from a delta-sigma modulator macromodel. Figure 8 Reconstruction of an input signal by passing the CIC output through an ideal DAC. voltage representation of the output code so it could be compared to the original analog input. This approach can verify the correctness of handshaking between the blocks and validate the full operation. Figure 8 shows the results of a simulation for sampling clock rates of 25 MHz, 5 MHz and 1.6 MHz with decimated clock rates of KHz, KHz and KHz, respectively. An important point to keep in mind is that CIC filter operation is done in 2s complement. The modulator output is straight binary. The input to conventional digital-to-analog converters (DACs) also is binary. Thus, the modulator output needs to be converted to 2s complement prior to being passed to a CIC filter so the CIC filter can operate on the 2s complement data. In the end, the decimation filter output should be converted back to binary, if it is going to be used by other conventional blocks. Therefore, in the delta-sigma macromodel two additional blocks are inserted before and after the CIC filter. The first block performs a conversion of binary-to-2s complement, while the block at the other end converts 2s complements back to binary codes to be used with an accompanied ideal DAC. The components used in the delta-sigma macromodel are presented in Figure 9. Summary We covered the basics of decimation filters along with their building blocks. The main idea of this work is to recognize the requirement of CIC filters that follow delta-sigma modulators as a part of delta-sigma data converters. The required order of filter, number of bits to be kept and number of bits to be discarded for a given order of delta-sigma converter, and specified decimation factor are explained in detail. Also provided is a simulation result of a sixth-order 24-bit delta- Figure 9 A design using TI s ADC bit ADC macromodel building blocks. 39

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