A Mathematical Guideline for Designing an AC-DC LLC Converter with PFC

Transcription

1 A Mathematical Guideline f Designing an AC-DC LLC Cnvete with PFC Yajie Qiu,, Membe, IEEE; Wenb Liu, Student Membe, IEEE; Peng Fang, Membe, IEEE; Yan-Fei Liu, Fellw, IEEE; Paesh C. Sen, Life Fellw, IEEE. Depatment f Electical and Cmpute Engineeing. GaN Systems Inc Queen s Univesity, Kingstn, Canada Ottawa, Canada yqiu@gansystems.cm; liu.wenb@queensu.ca; p.fang@queensu.ca; yanfei.liu@queensu.ca; senp@queensu.ca Abstact Althugh LLC tplgy has been applied t AC-DC pwe supplies as a Pwe Fact Cectin (PFC) cnvete in the liteatue, thee is n publicatins pesent intuitive equatins that simplify LLC designing in de t meet the PFC gain equiements. In this pape, a mathematical design guideline is deived f LLC PFC cnvete applicatins, pving that by caefully designing the esnant tank gain at paallel esnant fequency at the peak AC vltage highe than, its gain will meet the PFC equiement f the AC vltages and esult in a successful single-stage PFC design with pwe fact ve The guideline is extended t ffline wide input and utput vltage LLC PFC applicatins. A 40-Watt pttype f a single-stage LLC LED dive with PFC has been built t veify the feasibility f the ppsed design guideline. Keywds AC-DC Cnvete; PFC; LLC; Single-Stage; Resnant Cnvete I. INTRODUCTION Massive eseach have been attacted and new tplgies have been studied n AC-DC pwe supply and its cntl stategy [-6], LLC tplgy is still ppulaly used as the secnd stage cnvete t pvide galvanic islatin and utput vltage/cuent egulatin [3, 4]. Hweve, all the pwe is pcessed twice, which seveely sacifices the ttal efficiency and pwe density. T vecme this disadvantage, single-stage esnant slutins with PFC wee discussed in [7-0]. The LLC esnant tplgy has been applied t a PFC cnvete in [7, 8] and then extended t an LED dive applicatin in [9], esulting in pwe supplies with highe efficiency and a educed pfile. Hweve, the pimay switches peate at an asymmetical duty ati in the this aticle, which nt nly esults in cntl and diving cicuit cmplexity, but als intduces thid hamnics int the input cuent, sacificing the ptimal pwe fact pefmance. In [0], using the ectifie-cmpensated fundamental-mde appximatin methd, the feasibility f the LLC tplgy wking as a PFC cnvete is pven with 50% duty cycle switch peatin. Hweve, thee is still n intuitive mathematical design guideline t help enginees quickly design the LLC cnvete t achieve the pwe fact cectin withut ve-designing the gain. In this pape, a peak-gain-based mathematical mdel is ppsed f an LLC cnvete that will achieve pwe fact cectin and als guaantee enugh gain f the entie line vltage ange. II. LLC RESONANT CONVERTER DESIGN GUIDELINE FOR PFC A. LLC Resnant Cnvete Vltage Gain Review The half-bidge LLC esnant cnvete pttype is shwn in Fig.. The peating fequency ange f the LLC PFC is defined as f p f s f, whee belw-esnance peatin is pefeed t ensue the inductive impedance chaacteistics f the LLC esnant tank, s that the sft switching can be achieved in bth pimay side switches and secnday dides. AC i in S H + v in - S L L C L m n: D C I + V R L Fig.. Pttype f Half-Bidge LLC Pwe Fact Cectin Cicuit The imum switching fequency is set at the seies esnant fequency f, expessed in (). The quality fact Q, the inductance ati K, the nmalized switching fequency f n and the ttal gain f the cnvete M LLCttal ae expessed in () t (5) [-3] and n is the tansfme s tuns ati. M f = π LC () π L Iut π L Q 8n C Vut 8n C Rut () Lm K = L (3) LLC ttal f fn = fs (4) + f + n Q K fn fn (5) B. Single-Stage PFC Gain Requiement Analysis Fig. plts the equied vltage gain, G eq(θ), f an LLC cnvete in PFC mde, accding t (6). D

2 00V 50V 00V V in V in V in V in V in 50V 0V v in (ɵ)= V in sin(ɵ) MLLC(f=fp) ɵ 0.5P P G eq (ɵ)=v /v in (ɵ) p (ɵ)=v in (ɵ)i in (ɵ) 0 30º 45º 90º 35º 50º 80º It is bseved that G eq(θ) t achieve pwe fact cectin is diffeent at each time instant, while the LLC cnvete utput pwe p ut(θ) is als changing as pe (7). put ( θ) = pin ( θ) = vin ( θ) iin ( θ) (7) = Iin msvin ms ( sin( θ) ) = ( sin( θ) ) P Assug the AC input vltage is 0VRMS: at 90º, the LLC shuld pvide tw times the steady state utput pwe (P pk =P ). At this time, the v in is at peak V inpk=0v.44, which is gd f pviding highe utput pwe. At 45º, the LLC shuld pvide the utput pwe (P ), but v in is 0V.44 sin(45º) =0V. The LLC cnvete shuld geneate V at 0V input at utput pwe level f P. At 30º, the v in = 0.5V inpk, and i in = 0.5I pk, the utput pwe is 0.5P pk =0.5P. Theefe, the LLC cnvete shuld pvide V at the utput pwe level f 0.5P. In de t achieve high pwe fact cectin pefmance, the LLC cnvete must achieve diffeent gains at diffeent input vltages. F PFC applicatin, the utput vltage is usually a cnstant. When P ut deceases, R ut als linealy inceases. Fig. 3 plts the nmalized LLC tank gain at paallel fequency unde diffeent lad (R ut anges fm t ). featuing an inceasing gain when the R ut is inceasing, this changing tend is in ageement with the PFC gain equiement as shwn in Fig.. Theefe, LLC esnant cnvete is a ptential candidate f single-stage PFC peatin tplgy. The esults fm () t (5) will be used late t deive the design ule f the LLC cnvete in PFC mde. P Fig.. Single-stage LLC PFC gain equiement G eq in in ms P 0.5P Vut Vut ( θ) = v ( θ) = V sin( θ) (6) Rut Fig. 3. Nmalized LLC tank gain at paallel esnant fequency unde diffeent lad, R ut C. Deivatin f the LLC Resnant Cnvete Design Guideline f PFC The entie LLC PFC design guideline is cmpsed f tw pats: the tansfme tuns ati design, and the LLC esnant tank design. ) Tansfme Tuns Rati Design Guideline Accding t (6) and (7), the imum gain equiement f a PFC design G eq (θ) ccus at θ=π/, when the instantaneus utput pwe is equal t twice the aveage utput pwe, P. The imum gain f the LLC esnant tank in the inductive peating ange ccus at the seies esnant fequency, f. Theefe, the ttal gain f the LLC cnvete at f is intentinally designed t be equal t the imum gain equiement f the PFC cnvete in (8) and the esulting tuns ati is expessed in (9). π Geq ( θ) = Geq ( θ = ) Vut V (8) ut = = π V sin( ) Vin ms in ms N pi Vin RMS n = N = sec V (9) ut ) LLC Resnant Tank Design Guideline In PFC mde, the quality fact Q pfc changes with θ. Deived fm (), the θ-dependent quality fact, Q pfc(θ) is shwn in (0), whee Q fulllad in () is the full lad quality fact when the LLC esnant cnvete is wking at the PFC aveage pwe P, and is a cnstant value. The ttal gain f the LLC esnant cnvete in PFC mde is shwn in (). Q pfc ( θ ) C C ( θ ) Rac ( θ ) Re full lad Qfull lad π L I ut full lad 8n C Vut ( θ) = = sin( ) = sin( ) Q L π P 4 V L ut in RMS C L (0) ()

3 MLLC ttal ( fs, θ) MLLC ( fs, θ) f sin K f f f MLLC ttal ( fs = fp, θ) MLLC ( fs = fp, θ) f 4 f p f ( sinθ ) Q full lad K f p f f p 4 fs f ( θ ) Q full lad s s () (3) Then the ttal gain f the LLC esnant cnvete at the paallel esnant fequency, f s =f p, is deived in (3). With the definitins f f p in (4) and K in (3), (3) is simplified int (5). f = π ( L + L ) C p m M LLC ttal fs = fp, θ = MLLC fs = fp, = K ( sinθ ) Qfull lad + K ( ) ( θ) (4) (5) If the LLC esnant tank gain f the peak input vltage (θ=π/) at the paallel esnant fequency M LLC(f s=f p, θ=π/) is designed equal t highe than, as shwn in (6), the esulting ttal LLC esnant cnvete gain can be then deived fm (9), () and (5), and is shwn in (7). Since the inequality f /(sinθ) /(sinθ) is always valid f 0 θ π, the LLC cnvete gain at the paallel esnant fequency, f p, will meet the PFC gain equiement (0 θ π) as pe (8). In sht, we nly design the LLC at ne phase θ=π/ t meet the PFC equiement, then the equiement f the the phase will autmatically be satisfied. π MLLC fs = fp, θ = = (6) K π Put L + K Vin RMS C Vut MLLC ttal ( fs = fp, θ ) V in RMS ( sinθ ) (7) Vut MLLC ttal ( fs = fp, θ ) V in RMS ( sinθ ) (8) Vut Geq ( θ ) V sin( θ) in ms D. Extended LLC Resnant Cnvete Design Guideline f PFC with Wide Input and Output Vltages Requiements The ppsed design guideline can als be adapted t the PFC applicatins with a wide AC input vltage, V in V in V in, and wide DC utput vltage, V ut V ut V ut as fllws: The LLC tansfme ati shuld be set based n the imum gain equiement which ccus at the imum input (V in ) and the imum utput (V ut ), as shwn in (9). V n = (9) in ms Vut T exple the design ule f LLC PFC unde all the cases f the utput vltage ange, we define Vut = λvut (0) V λ ut () Vut With the changing f V ut, the gain equiement f wide utput vltage ange PFC cmes int a λ-elated expessin as shwn in (0). G eq ext Vut ( θ, λ) = λ () V sin( θ ) in ms Accding t () and (3) the LLC cnvete gain in λ- dependent fm is btained in (3), whee Q fullladv is the quality fact when the utput vltage is at V. MLLC ttal ext ( fs, θ, λ) M LLC ext ( fs, θ) ext ext f 4 fs f + 4 λ + ( sinθ) Q full lad v K fs f fs λ (3) The ttal gain f LLC cnvete at the paallel esnant fequency, f p, is deived by using (0) t eplace V ut in (5). MLLC ttal ext ( fs = fp, θλ, ) = MLLC ext ( fs = fp, θλ, ) ext Vut K π P ( sin ) ut L V in θ + K ( Vin ) C (4) Vut K π λ V V in ( sin ) Iut L θ + K ( Vin ) C It is bseved fm (4) that the ttal LLC cnvete gain at f p is deceasing while the gain equiement is inceasing V with the incease f λ when ut λ <. Theefe, we nly Vut need t check the LLC cnvete gain cnsideing the highest utput vltage (λ=) (shwn in (5)) and make sue it satisfies the gain equiement (shwn in (6)). Geq div ( θ, λ = ) = Vut V sin( θ ) in ms (5) M LLC div( fs, θλ, = ) = f 4 fs f ( sinθ ) Qfull lad v K fs f fs (6) By fllwing the deivatin steps in II. C, the extended LLC esnant cnvete design guideline is btained as fllws:

4 a) the tansfme tuns ati value is designed t be equal t V inrms / V ut b) the gain f the LLC esnant tank at f p is highe than the pduct f the vaiatin atis f input vltage and utput vltage, cnsideing the case θ=90º when line vltage is at peak value. π (7) M LLC ext fs = fp, θ = = K Q full lad v + K Vin ms Vut V V in ms ut This is demnstated in Fig. 5, whee the esulting gain cuve f the designed LLC PFC (in geen) csses the gain equiement (in ed) nly at θ=90º when p ut(θ)=p (the utput pwe cuve is shwn in blue), and then is always highe than the equiement when 0<θ<80º, 0<p ut(θ)<p. Fig. 6 als shws that the designed LLC gain (the cled suface) is always highe than the PFC gain equiement (the ed suface) within the specified utput vltage ange (40 V<V ut<60 V, 0<θ< π), esulting in a successful LLC PFC design. III. DESIGN EXAMPLE A 40 W, single-stage half-bidge LLC LED dive was designed and built using the ppsed mathematical guideline. The specificatins ae shwn in Table I. TABLE I. SINGLE-STAGE LLC LED DRIVER SPECIFICATIONS V in V LED I LED P O f line 80~300 Vac 40~60 Vdc 4 A 40 W 60 Hz The expected tansfme tuns ati f the half-bidge LLC LED dive n is calculated in (8). N pi Vin RMS 300 n = 5.3 N = sec V = ut 40 (8) Table II lists the imum gain equiement value f the desied LLC LED dive, calculated in (9). TABLE II. M LLC(f p) LLC TANK GAIN REQUIREMENT AT THE PARALLEL RESONANT FREQUENCY (FP) V utma x I P=p(θ=π/) = P =V ut I ut >.5 60 V 4 A 60 V 4 A=480 W Vin Vut Vin Vut The key LLC paametes ae listed in Table III. = = (9) Fig. 4. Nmalized Gain Plt f the Designed LLC Resnant Cnvete at heaviest lad p ut(θ=90º)=p O M LLC (θ) G eq (θ) G eq (θ=90º )=M LLCttal (θ=90º ) p nm (θ) TABLE III. KEY PARAMETERS OF DESIGNED SINGLE-STAGE LLC LED DRIVER Npi:Nsec : Tansfme Ce PQ 40 Lm 03 µh L 0 µh C FKPO6804D00JSSD 3 (6800 pf KV) Output capacit C B43504A08M 3 (000 µf, 50 V) Switching fequency(fs) 00 khz ~ 50 khz Switches (SH & SL) SPPN80C3 As shwn in Fig. 4, the designed LLC esnant tank featues a nmalized gain f.7 at the paallel esnant fequency fp/f=0.39, which is 9% highe than the equiement f.5. Accding t the ppsed extended LLC PFC design guideline, nce the LLC gain meets the PFC equiement at peak AC input vltage, it will meet the equiement f the entie line vltage cycle. 0 45º 90º 35º 80º θ Fig. 5. Gain Requiement vs. Gain Cuve f the Designed LLC Resnant Cnvete Cnsideing V ut=v ut =60 V Cnsideing the entie peating ange f utput vltage, a 3-D suface plt is dawn in Fig. 6 using the PFC gain equiement expessin in () and the LLC gain expessin at paallel esnant fequency in (4). The gain equiement is a ed suface, while the LLC gain is an iegula cled suface. Bth f them ae changing with λ=v /V and phase f line vltage θ. It is bseved that the designed LLC esnant tank featues the gain that is always highe than the equiement within the specified utput vltage ange as

5 well as the entie half line vltage cycle (0.667 <λ <, 0 < θ <80 ), esulting in a successful LLC PFC design. M LLCttal (θ,λ ) Fig W Single-Stage LLC PFC LED Dive Pttype M LLCdivttal, G eqdiv G eq (θ,λ) λ=v /V LED LAMP (40~60V 4A ) input cnnects LED ba # 60V 50V 40V LED ba # LED vltage adjuste LED chips M LLCttal (θ,λ ) Fig W LED Lamp Lad (V LED=40~60V, I LED=4A) G eq (θ,λ) M LLCdivttal, G eqd iv λ=v /V Fig. 6. Designed LLC Resnant Cnvete Gain vs. PFC Gain Requiement in 3D Suface Plt Cnsideing the Wide Output Vltage (V ut <V ut<v ut ) IV. EXPERIMENTAL VERIFICATION The pictues f the designed 40W single-stage halfbidge LLC LED dive pttype is shwn in Fig. 7 while the LED lad is shwn in Fig. 8. The lad is made f paalleled-cnnected LED bas and each LED ba has 8 pieces f LED chips fm Cee (XMLBWT T505CT) cnnected in seies t pvide enugh lad ability (the LED vltage up t 60V and LED cuent up t 4A). As shwn in Fig. 9, the PFC cntl stategy is implemented using dspic33fj3gs606. A linea ptcuple is used t tansmit LED cuent signal t the pimay side. The LED cuent signal is sampled by an ADC, and then subtacted fm a efeence vltage value t ceate an e value. The e value is pcessed by a slw PI cntlle and becmes ne f the tw essential signals t ceate the input cuent efeence. The the essential infmatin f the input cuent efeence is the sinusidal input vltage. The ectified input vltage is fistly scaled dwn t adapt the DSC analg input ange and then sampled by the secnd ADC. By multiplying the e value fm the fist ADC and the scaled input vltage efeence fm the secnd ADC, a ectified sinusidal input cuent efeence signal is geneated. Since it is difficult t accuately btain the aveage input cuent value ve ne switching cycle in LLC esnant tplgy due t the iegula cuent wavefm and the existence f ciculatin cuent, the input cuent value is calculated by using the cycle-by-cycle aveage input cuent sensing methd ppsed in [4]. This methd accuately measues the aveage input cuent ve each switching peid by sensing the seies esnant capacit vltage and the input vltage at a paticula time instant and thus pvides eal-time aveage input cuent infmatin.

6 Bidge Rectifie Single-Stage Half-Bidge LLC PFC Cnvete vin D 80~300 D3 Vac D D4 SH SL C 0.4nF L 0uH Lm 03uH T Daux D D Q Q ILED 4A C 3mF LFB uh + + VLED 40~60V Ns Caux 470uF Q3 Q4 CFB 4.7uF Scale dwn ADC ADC vcs Scale dwn cmplementay signals at 50% duty cycle SH Gate Dives SL Full-Bidge Ripple Cancellatin Cnvete SPWM signals t Q ~ Q4 Full Bidge MOSFETs Dives Cuent sensing vi Optinal Paametes C Cj fs S/H thff & tlff Intenal Cunte Cntl signal Geneat Cmpaat Analg Implementatin f Bipla Ripple Cancellatin Cntl Input Cuent Sensing Algithm ii + PI Switching Peid Digital Signal Cntlle vi Multiplie PI + ILEDsens I LEDef ADC Linea Opt- cuple and Peipheal Cicuity Fig. 9. The Implementatin f the Single-Stage LLC Resnant LED Dive. The expeimental pttype pesents pwe fact pefmance f 0.99 at 80 V AC input, as shwn in Fig. 0. It is nticed that thee ae a blank ptins f input cuent in the vicinity f the input vltage ze cssing pints. This is caused by the nnlineaity f the MOSFET utput capacitance, C ss, which is a nnlinea capacitance that vaies with the dain-t-suce vltage f the MOSFET[5]. As an aveage C ss value is used in the existing digital implementatin, the nnlineaity f C ss value in the eal cicuit esults the sensing e at the light input cuent and the lw input vltage. The existing pttype is using Si MOSFET (SPPN80C3) as the half bidge switches, featuing quite high C ss value at lw input vltage (C ss@vin=30v>500pf). Using the GaN HEMTs with significantly educed C ss (C ss@vin=30v<50pf) will educe the diffeence between the aveage value and the eal value f C ss and lead t the impved PF pefmance. Input Vltage: 80Vac 9% is achieved. The 0 Hz utput ipple is cancelled by an auxiliay ipple cancellatin cicuit [6, 7]. The PF and efficiency data unde diffeent input and utput vltages ae shwn in Fig. 8 and Fig. 9. Ch: Input Vltage Ch3: Dain t Suce Vltage Case 6: θ=90 Case 5: θ=60 Case 4: θ=45 Case 3: θ=30 Case : θ=0 Case : θ=0 Ch4: Gate Diving signals Fig.. Sft Switching Pefmance f the LLC PFC n Pimay Side at Diffeent Phase Angle, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W Input Cuent PF=0.99 Output Cuent: 4Adc Fig. 0. Pwe fact pefmance f the Half-bidge LLC LED Dive, When V in=80 V, I ut=4 V, V ut 60 V Ze vltage switching pefmance duing the whle PFC peatin ae shwn in Fig. ~ Fig. 7. Als, the design pesents a cst-effective, high-efficiency slutin, cmpaed with the tw-stage LED dive slutin. A peak efficiency f Fig.. ZVS Pefmance f the LLC PFC n Pimay Side at θ=0º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W

7 Fig. 3. ZVS Pefmance f the LLC PFC n Pimay Side at θ=0º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W Fig. 6. ZVS Pefmance f the LLC PFC n Pimay Side at θ=60º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W Fig. 4. ZVS Pefmance f the LLC PFC n Pimay Side at θ=30º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W Fig. 7. ZVS Pefmance f the LLC PFC Stage n Pimay Side at θ=90º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W LLC PFC Pwe Fact (I=4A) V 0V 300V 40V utput 50V utput 60V utput Fig. 5. ZVS Pefmance f the LLC PFC n Pimay Side at θ=45º, When V in=80 Vac, V LED 60 V, I LED=4 A, P O=40 W Fig. 8. Pwe fact pefmance f the Half-bidge LLC LED Dive at Diffeent Input and Output Vltages 7

8 9.0% 9.0% 90.0% 89.0% 88.0% 90.8% 90.7% 90.% LLC PFC eff (I=4A) 9.4% 9.3% 90.7% Fig. 9. Efficiency f the Half-bidge LLC LED Dive at Diffeent Input and Output Vltages CONCLUSION In this pape, a mathematical LLC-type cnvete design guideline f PFC is ppsed, which is intuitive and easy t apply. By caefully designing the LLC esnant cnvete with its tank gain at paallel esnant fequency t be highe than cnsideing the case when line vltage is at peak value, its gain will meet the single-stage PFC equiement f the entie line vltage ange (0<θ<80º), esulting in a successful LLC PFC design. T veify the design ule and demnstate the advantages f the single-stage LLC pwe fact cectin tplgy, a 40W ffline high pwe LED dive is built with vaiable input vltage ange 80Vac~300Vac and vaiable utput vltage ange f 40Vdc~60Vdc. Featuing a high peak pwe fact pefmance f 0.99, the design pesents a cst effective and high-efficiency slutin, cmpaed t the cnventinal tw-stage LED dive slutin. A peak efficiency f 9% has been achieved n the pttype. V. REFERENCES 9.0% 9.8% 9.% 80V 0V 300V 40V utput 50V utput 60V utput [] J. Lu et al., "A Mdula Designed Thee-phase High-efficiency Highpwe-density EV Battey Chage Using Dual/Tiple-Phase-Shift Cntl," IEEE Tansactins n Pwe Electnics, vl. PP, n. 99, pp. -, 07. [] R. Hu and A. Emadi, "A Pimay Full-Integated Active Filte Auxiliay Pwe Mdule in Electified Vehicles With Single-Phase Onbad Chages," IEEE Tansactins n Pwe Electnics, vl. 3, n., pp , 07. [3] Z. Hu, Y. Qiu, Y.-F. Liu, and P. C. Sen, "A Cntl Stategy and Design Methd f Inteleaved LLC Cnvetes Opeating at Vaiable Switching Fequency," Pwe Electnics, IEEE Tansactins n, vl. 9, n. 8, pp , 04. [4] Z. Hu, Y. Qiu, L. Wang, and Y.-F. Liu, "An Inteleaved LLC Resnant Cnvete Opeating at Cnstant Switching Fequency," Pwe Electnics, IEEE Tansactins n, vl. 9, n. 6, pp , 04. [5] J. Lu et al., "Applying Vaiable-Switching-Fequency Vaiable-Phase- Shift Cntl and E-Mde GaN HEMTs t an Indiect Matix Cnvete-Based EV Battey Chage," IEEE Tansactins n Tansptatin Electificatin, vl. 3, n. 3, pp , 07. [6] R. Hu and A. Emadi, "Applied Integated Active Filte Auxiliay Pwe Mdule f Electified Vehicles With Single-Phase Onbad Chages," IEEE Tansactins n Pwe Electnics, vl. 3, n. 3, pp , 07. [7] C. M. Lai and K. K. Shyu, "A single-stage AC/DC cnvete based n ze vltage switching LLC esnant tplgy," IET Electic Pwe Applicatins, vl., n. 5, pp , 007. [8] H. L. D and B. H. Kwn, "Single-stage asymmetical PWM AC-DC cnvete with high pwe fact," IEE Pceedings - Electic Pwe Applicatins, vl. 49, n., pp. -8, 00. [9] K. Seng-Ju, K. Chn-Taek, K. Yung-J, L. Jae-Du, and K. Yung- Sek, "Single-stage asymmetical LLC esnant cnvete with lw vltage stess acss switching devices," in 03 Intenatinal Cnfeence n Electical Machines and Systems (ICEMS), 03, pp [0] D. L. O. Sullivan, M. G. Egan, and M. J. Willes, "A Family f Single- Stage Resnant AC/DC Cnvetes With PFC," IEEE Tansactins n Pwe Electnics, vl. 4, n., pp , 009. [] R. L. Steigewald, "A cmpaisn f half-bidge esnant cnvete tplgies," IEEE Tansactins n Pwe Electnics, vl. 3, n., pp. 74-8, 988. [] S. D. Simne, C. Adagna, C. Spini, and G. Gattavai, "Design-iented steady-state analysis f LLC esnant cnvetes based n FHA," in Intenatinal Sympsium n Pwe Electnics, Electical Dives, Autmatin and Mtin, 006. SPEEDAM 006., 006, pp [3] Z. Hu, L. Wang, Y. Qiu, Y.-F. Liu, and P. C. Sen, "An Accuate Design Algithm f LLC Resnant Cnvetes Pat II," IEEE Tansactins n Pwe Electnics, vl. 3, n. 8, pp , 06. [4] Z. Hu, Y. F. Liu, and P. C. Sen, "Cycle-by-cycle aveage input cuent sensing methd f LLC esnant tplgies," in 03 IEEE Enegy Cnvesin Cngess and Expsitin, 03, pp [5] D. Cstinett, R. Zane, and D. Maksimvi, "Cicuit-iented mdeling f nnlinea device capacitances in switched mde pwe cnvetes," in Cntl and Mdeling f Pwe Electnics (COMPEL), 0 IEEE 3th Wkshp n, 0, pp. -8. [6] Y. Qiu, L. Wang, H. Wang, Y. Liu, and P. C.Sen, "Bipla Ripple Cancellatin Methd t Achieve Single-Stage Electlytic-Capacit- Less High-Pwe LED Dive," Emeging and Selected Tpics in Pwe Electnics, IEEE Junal f, vl. 3, n. 3, pp , 05. [7] Y. Qiu, H. Wang, Z. Hu, L. Wang, Y.-F. Liu, and P. C. Sen, "Electlytic-Capacit-Less High-Pwe LED Dive," in Enegy Cnvesin Cngess and Expsitin (ECCE), 04 IEEE, 04, pp