NV V GaNFast Power IC. 2. Description. 1. Features. 3. Topologies / Applications. 4. Typical Application Circuits

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1 650 V GaNFast Power IC QFN 5 x 6 mm. Features implified schematic GaNFast Power IC Monolithically-integrated gate drive Wide logic input range with hysteresis 5 V / 5 V input-compatible Wide range (0 to 30 V Programmable turn-on dv/dt 200 V/ns dv/dt immunity 650 V emode GaN FET Low 20 mω resistance Zero reverse recovery charge 2 MHz operation mall, low-profile MT QFN 5 x 6 mm footprint, 0.85 mm profile Minimized package inductance Environmental RoH, Pb-free, REACH-compliant 2. escription The is a 650 V GaNFast power IC, optimized for high frequency, soft-switching topologies. Monolithic integration of FET, drive and logic creates an easy-to-use digital-in, power-out high-performance powertrain building block, enabling designers to create the fastest, smallest, most efficient integrated powertrain in the world. The highest dv/dt immunity, high-speed integrated drive and industry-standard low-profile, low-inductance, 5 x 6 mm MT QFN package allow designers to exploit Navitas GaN technology with simple, quick, dependable solutions for breakthrough power density and efficiency. Navitas GaNFast power ICs extend the capabilities of traditional topologies such as flyback, half-bridge, resonant, etc. to MHz+ and enable the commercial introduction of breakthrough designs. 3. Topologies / Applications AC-C, C-C, C-AC Buck, boost, half bridge, full bridge Active Clamp Flyback, LLC resonant, Class Mobile fast-chargers, adapters Notebook adaptors LE lighting, solar micro-inverters TV / monitor, wireless power erver, telecom & networking MP 4. Typical Application Circuits C IN(+ C OUT(+ C IN(+ 0V to 24V V Z REG dv/dt Half Bridge river IC REG V Z dv/dt C IN(- C OUT(- 0V to 24V C IN(- REG V Z dv/dt PGN Boost Half-bridge Final atasheet Rev

2 5. Table of Contents. Features escription Topologies / Applications Typical Application Circuits pecifications Absolute Maximum Ratings Recommended Operating Conditions E Ratings Thermal Resistance Electrical Characteristics witching Waveforms Characteristic Graphs Internal chematic, Pin Configurations and Functions Functional escription tart Up Normal Operating Mode tandby Mode Programmable Turn-on dv/dt Control Current ensing Paralleling evices V Input Circuit PCB Layout Guidelines Recommended Component Values Recommended PCB Land Pattern PCB Layout Guidelines QFN Package Outline Tape and Reel imensions Ordering Information... 2 Final atasheet 2 Rev

3 6. pecifications 6.. Absolute Maximum Ratings ( (with respect to ource (pad unless noted YMBOL PARAMETER MAX UNIT V rain-to-ource Voltage -7 to +650 V V T Transient rain-to-ource Voltage (2 750 V V CC upply Voltage 30 V V Input Pin Voltage -3 to +30 V V Z V etting Pin Voltage 6.6 V V rive upply Voltage 7.2 V I Continuous rain Current (@ T C = 00ºC 2 A I PULE Pulsed rain Current (0 T J = 25ºC 24 A I PULE Pulsed rain Current (0 T J = 25ºC 6 A dv/dt lew Rate on rain-to-ource 200 V/ns T J Operating Junction Temperature -55 to 50 ºC T TOR torage Temperature -55 to 50 ºC ( Absolute maximum ratings are stress ratings; devices subjected to stresses beyond these ratings may cause permanent damage. (2 < µ. V T is intended for surge rating during non-repetitive events (for example start-up, line interruption Recommended Operating Conditions (3 YMBOL PARAMETER MIN TYP MAX UNIT V Z rive upply et Zener Voltage ( V V rive upply Voltage V I _EXT Regulator External Load Current 3.0 ma R Gate rive Turn-On Current et Resistance ( Ω V Input Pin Voltage 0 5 Min. of (V CC or 20 V rain-to-ource Voltage 520 V V CC upply Voltage 0 24 V T J Operating Junction Temperature ºC V (3 Exposure to conditions beyond maximum recommended operating conditions for extended periods of time may affect device reliability. (4 Use of zener diode other than 6.2 V is not recommended. ee Table I for recommended part numbers of 6.2 V zener diodes. (5 R resistor must be used. Minimum 0 Ohm to ensure application and device robustness. Final atasheet 3 Rev

4 6.3. E Ratings YMBOL PARAMETER MAX UNIT HBM Human Body Model (per J ,000 V CM Charged evice Model (per J ,000 V 6.4. Thermal Resistance YMBOL PARAMETER TYP UNIT (6 R ɵjc Junction-to-Case.8 ºC/W (6 R ɵja Junction-to-Ambient 50 ºC/W (6 R ɵ measured on UT mounted on square inch 2 oz Cu (FR4 PCB Final atasheet 4 Rev

5 6.5. Electrical Characteristics Typical conditions: V = 400 V, V CC = 5 V, V Z = 6.2 V, F W = MHz, T AMB = 25 ºC, I = 6 A, R = 0 Ω (or specified YMBOL PARAMETER MIN TYP MAX UNIT CONITION V CC upply Characteristics I QCC V CC Quiescent Current ma V = 0 V I QCC-W V CC Operating Current 2.85 ma F W = MHz, V = Open Low-ide Logic Input Characteristics V H Input Logic High Threshold (rising edge 4 V V L Input Logic Low Threshold (falling edge V V I-HY Input Logic Hysteresis 0.5 V T ON Turn-on Propagation elay ns Fig., Fig.2 T OFF Turn-off Propagation elay 9 ns Fig., Fig.2 T R rain rise time 6 ns Fig., Fig.2 T F rain fall time 3 ns Fig., Fig.2 witching Characteristics F W witching Frequency 2 MHz t PW Pulse width µs GaN FET Characteristics I rain-ource Leakage Current µa V = 650 V, V = 0 V I rain-ource Leakage Current 0 µa V = 650 V, V = 0 V, T C = 25 ºC R (ON rain-ource Resistance mω V = 6 V, I = 6 A V ource-rain Reverse Voltage V V = 0 V, I = 6 A Q O Output Charge 27 nc V = 400 V, V = 0 V Q RR Reverse Recovery Charge 0 nc C O Output Capacitance 27 pf V = 400 V, V = 0 V C O(er (7 C O(tr (8 Effective Output Capacitance, Energy Related Effective Output Capacitance, Time Related 4 pf V = 400 V, V = 0 V 67 pf V = 400 V, V = 0 V (7 C O(er is a fixed capacitance that gives the same stored energy as C O while V is rising from 0 to 400 V (8 C O(tr is a fixed capacitance that gives the same charging time as C O while V is rising from 0 to 400 V Final atasheet 5 Rev

6 6.6. witching Waveforms (T C = 25 ºC unless otherwise specified V 50% V CC V V 90% V t Z Fig.. Inductive switching circuit 0% TON TOFF TF TR Fig.2. Propagation delay and rise/fall time definitions t Final atasheet 6 Rev

7 6.7. Characteristic Graphs (GaN FET, T C = 25 ºC unless otherwise specified Fig.3. Pulsed rain current (I PULE vs. drain-to-source voltage (V at T = 25 C Fig.4. Pulsed rain current (I PULE vs. drain-to-source voltage (V at T = 25 C Fig.5. ource-to-drain reverse conduction voltage Fig.6. rain-to-source leakage current (I vs. drain-to-source voltage (V Fig.7. V H and V L vs. junction temperature(t J Fig.8. Normalized on-resistance (R (ON vs. junction temperature (T J Final atasheet 7 Rev

8 Characteristic Graphs (Cont. Fig.9. Output capacitance (C O vs. drain-to-source voltage (V Fig.0. Energy stored in output capacitance (E O vs. drain-to-source voltage (V Fig.. Charge stored in output capacitance (Q O vs. drain-to-source voltage (V Fig.2. V CC operating current (I QCC-W vs. operating frequency (F W Fig.3. V CC quiescent current (I QCC vs. supply voltage (V CC Fig.4. Propagation delay (T ON and T OFF vs. junction temperature(t J Final atasheet 8 Rev

9 Characteristic Graphs (Cont. Fig.5. lew rate (dv/dt vs. gate drive turn-on current set resistance (R at T = 25 C Fig.6. Power dissipation (P TOT vs. case temperature (T C Fig.7. Max. thermal transient impedance (Z thjc vs. pulse width (t P Final atasheet 9 Rev

10 7. Internal chematic, Pin Configurations and Functions V CC 8 4 Z REG V 5 dv/dt 2 PA Package Top View Pin Number ymbol I/O ( V CC P upply voltage (0V to 24V escription 2 I input 3 V I Gate drive supply voltage. Gate drive turn-on current set pin (using R. 4 Z I Gate drive supply voltage set pin (6.2 V zener to GN. 5,6,7,8 P rain of power FET PA O, G ource of power FET & GaN IC supply ground. Metal pad on bottom of package. ( I = Input, O = Output, P = Power, G = GaN IC Ground Final atasheet 0 Rev

11 8. Functional escription The following functional description contains additional information regarding the IC operating modes and pin functionality. 8.. tart Up When the V CC supply is first applied to the, care should be taken such that the V and Z pins are up at their correct voltage levels before the input signal starts. The V pin ramp up time is determined by the internal regulator current at this pin and the external C V capacitor. Also, since the Z pin voltage sets the V voltage level, the V pin will ramp up together with the Z pin (Fig.8. 0V to 24V V Z 0nF 6.2V Fig.8. Quick start-up circuit For half-bridge configurations, it is important that the V CC supply, the Z pin, and the V supply of the high-side are all charged up to their proper levels before the first high-side pulses start. For LLC applications, a long on-time pulse to the low-side (> 0 µs is typically provided by the LLC controller to allow the supply pins of the high-side to charge up (through the external bootstrap diode to their correct levels before the first high-side pulses start (Fig.9. For active clamp flyback (ACF applications, the halfbridge must be ready very quickly due to the soft-start mode of the ACF controller. When the first few pulses are generated by the ACF controller, the highside supply pins of the will require a few lowside pulses to charge up (through the external bootstrap diode before the high-side starts to switch (Fig.20. Fig.9. LLC half-bridge start-up timing diagram Fig.20. ACF half-bridge start-up timing diagram Final atasheet Rev

12 8.2. Normal Operating Mode uring Normal Operating Mode, all of the internal circuit blocks are active. V CC is operating within the recommended range of 0 V to 24 V, the V pin is at the voltage set by the zener diode at the Z pin (6.2 V, and the internal gate drive and power FET are both enabled. The external signal at the pin determines the frequency and duty-cycle of the internal gate of the power FET. As the voltage toggles above and below the rising and falling input thresholds (4 V and V, the internal gate of the power FET toggles on and off between V and 0 V (Fig.2. The drain of the power FET then toggles between the source voltage (typically power ground and a higher voltage level (650 V max, depending on the external power conversion circuit topology. V V V BU T OFF T ON T PERIO Fig.2. Normal operating mode timing diagram t t 0V to 24V ENABLE 00K I330EL B84A V Z Fig.22. tandby mode cut-off circuit 8.4. Programmable Turn-on dv/dt Control uring first start-up pulses or during hard-switching conditions, it is desirable to limit the slew rate (dv/dt of the drain of the power FET during turn-on. This is necessary to reduce EMI or reduce circuit switching noise. To program the turn-on dv/dt rate of the internal power FET, a resistor (R is placed in between the V capacitor and the V pin. This resistor (R sets the turn-on current of the internal gate driver and therefore sets the turn-on falling edge dv/dt rate of the drain of the power FET (Fig.23. A typical turn-on slew-rate change with respect to R is shown in Fig.5. Minimum 0 Ω R is required. V 8.3. tandby Mode TOFF TON t For applications where a low standby power is required, an external series cut-off circuit (Fig.22 can be used to disconnect of the from the main supply of the power supply. This will reduce current consumption when the converter is in burst mode during light-load or open load conditions. The cut-off circuit consists of a series PMO FET that is turned on and off with a pull-down NMO FET. The gate of the NMO is controlled by an external ENABLE signal that should be provided by the main controller of the power supply. The capacitor value at the pin should then be selected according to the desired start-up speed of the each time the ENABLE signal toggles high. A 22 nf capacitor at, for example, will give a typical start-up time of approximately 2 µs. V VBU rain turn-on Falling edge Increase R to ecrease dv/dt Fig.23. Turn-on dv/dt slew rate control t Final atasheet 2 Rev

13 8.5. Current ensing For many applications it is necessary to sense the cycleby-cycle current flowing through the power FET. To sense the current flowing through the, a standard current-sensing resistor can be placed in between the source and power ground (Fig.24. In this configuration, all of the components around the (C, C V, Z, etc. should be grounded with a single connection at the source. Also, an additional RC filter can be inserted between the signal and the pin (00 Ω, 00 pf typical. This filter is necessary to prevent false triggering due to high-frequency voltage spikes occurring at the source node due to external parasitic inductance from the source PCB trace or the current-sensing resistor itself. 0V to 24V C 00R 00pF V CC V Z R C 8.6. Paralleling evices For some applications it is desirable to parallel ICs in order to reduce conduction losses and temperatures. Two ICs can be connected in parallel in a PFC boost application working in boundary-conduction mode (BCM only. The parallel configuration for two ICs is shown in Fig.25. The paired pins that are connected together include the drain pins (, the source pins (, the V CC pins, the pins, and the Z. A single Z diode can be shared by both ICs. The V pins are not connected together and require separate V supply capacitors (C V, C V2 and separate turnon current set resistors (R, R 2. Each IC should have its own local supply filter capacitor (C, C 2. The pins can have a single filter resistor (R but separate filter capacitors (C, C 2 should be placed at the pin of each IC. When designing the PCB layout for the two paralleled ICs, the drain and source connections should be made as symmetrical as possible two avoid any parasitic inductance or capacitance mismatch. A proper PCB layout example for paralleling is shown in ection. CIN(+ COUT(+ PGN V Z Z V Z Fig.24. Current sensing circuit C 0V to 24V C R R CV C C2 R2 C2 CV2 CIN(- RC COUT(- Fig.25. Boost schematic using two parallel ICs Final atasheet 3 Rev

14 V Input Circuit For some applications where a 3.3 V signal is required (P, MCU, etc. an additional buffer can be placed before the input pin (Fig.26 with the buffer supply voltage connected to the V capacitor. 0V to 24V Fig V input buffer circuit 8.8. PCB Layout Guidelines The design of the PCB layout is critical for good noise immunity, sufficient thermal management, and proper operation of the IC. Typical PCB layout examples for without current sensing resistor, with current sensing resistor, and paralleling, are all shown in ections 0 and. The following rules should be followed carefully during the design of the PCB layout: Place all IC filter and programming components directly next to the IC. These components include (C, C V, R, C, R and Z. 2 Keep ground trace of IC filter and programming components separate from power GN trace. o not run power GN currents through ground trace of filter components! 3 For best thermal management, place thermal vias in the source pad area to conduct the heat out through the bottom of the package and through the PCB board to other layers (see ections 0 and for correct layout examples. 4 Use large PCB thermal planes (connected with thermal vias to the source pad and additional PCB layers to reduce IC temperatures as much as possible (see ections 0 and for correct layout examples. 5 For half-bridge layouts, do not extend copper planes from one IC across the components or pads of the other IC! 6 For high density designs, use a 4-layer PCB and 2 oz. copper to route signal connections. This allows layout to maintain large thermal copper planes and reduce power device temperature. Final atasheet 4 Rev

15 8.9. Recommended Component Values The following table (Table I shows the recommended component values for the external filter capacitors, zener diode, and R connected to the pins of the. These components should be placed as close as possible to the IC. Please see PCB Layout guidelines for more information. The zener diode at the Z pin should be a lowcurrent type with a flat zener, and the min/max limits must be followed. R must be a minimum of 0 Ω to ensure application and device robustness. YM ECRIPTION PART NO. UPPLIER MIN TYP MAX UNIT C Maximum V CC supply capacitor 0. µf C V V supply capacitor 0.0 µf R Gate drive turn-on current set resistor Ω Taiwan emiconductor Z V set zener diode ( Z pin BZT52B6V2 RHG Corporation V MM3Z6V2TG ON-emiconductor R filter resistor 00 Ω C filter capacitor 00 pf Table I. Recommended component values Zener election The zener voltage is a critical parameter that sets the internal reference for gate drive voltage and other circuitry. The zener diode needs to be selected such that the voltage on the Z pin is within recommended operating conditions (5.8 V to 6.6 V across operating temperature (-40 C to 25 C and bias current (0 µa to ma. To ensure effective operation, the current vs. voltage characteristics of the zener diode should be measured down to 0 µa to ensure flat characteristics across the current operating range (0 µa to ma. The recommended part numbers meet these requirements. If the zener selected by user does not ensure that the voltage on the zener pin is always within the recommended operating range, the functionality and reliability of the can be impacted. An external resistor (~47 kω between and Z can improve zener voltage stability by adding bias current to the zener pin to ensure the voltage on the Z pin is always within the recommended operating range (Error! Reference source not found.. This will add ~200 µa of quiescent current. 0V to 24V Fig.27. Increasing Zener Bias Current for table Zener Voltage Final atasheet 5 Rev

16 9. Recommended PCB Land Pattern All dimensions are in mm Final atasheet 6 Rev

17 0. PCB Layout Guidelines PCB Via Top Layer Without Current ensing Resistor Bottom Layer Component Landing Pad (Top Layer Place supply filter capacitor (C at pin Bottom Layer Thermal Copper Area (adjust size as necessary C upply Input Gate rive ET Resistor (R V Filter Capacitor (CV V ET Zener (Z 4 rain witching Node C V R Z CV Z PCB Thermal Vias (dia = 0.65mm, hole = 0.33mm, pitch = 0.925mm, via wall thickness = mil PWR GN (Top View (Top View With Current ensing Resistor Place supply filter capacitor (C filter capacitor (C filter resistor (R upply Input Gate rive ET Resistor (R V Filter Capacitor (CV V ET Zener (Z Current ensing ignal C 4 Bottom Layer Thermal Copper Area (adjust size as necessary rain witching Node R C C C R CV V Z Z RC PCB Thermal Vias (dia = 0.65mm, hole = 0.33mm, pitch = 0.925mm, via wall thickness = mil Current ensing Resistors (RC PWR GN (Top View (Top View Final atasheet 7 Rev

18 . PCB Layout Guidelines (cont. PCB Paralleling 2 ICs (Boost PFC, BCM Mode only Via Top Layer Bottom Layer Component Landing Pad (Top Layer rain witching Node V Z Z V Z C 0V to 24V C R C V C 2 R 2 R C C 2 C V2 R C PWR GN PCB rain witching Node Bottom Layer Thermal Copper Area (adjust size as necessary 4 4 Thermal Vias (dia = 0.65mm, hole = 0.33mm, pitch = 0.925mm, via wall thickness = mil C Z C2 C R C V C2 R2 CV2 Input upply C ignal R RC PWR GN Current ensing Resistors (RC (Top View Final atasheet 8 Rev

19 2. QFN Package Outline Final atasheet 9 Rev

20 3. Tape and Reel imensions Final atasheet 20 Rev

21 4. Ordering Information Part Number Operating Temperature Grade torage ML Package Temperature Range Rating Packing (Tape & Reel -40 C to +25 C T CAE -55 C to +50 C T CAE 5 x 6 mm QFN 3,000 : 7 Reel 5,000 : 3 Reel Additional Information ICLAIMER Navitas emiconductor Inc. (Navitas reserves the right to modify the products and/or specifications described herein at any time and at Navitas sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied. This document is presented only as a guide and does not convey any license under intellectual property rights of Navitas or any third parties. Navitas products are not intended for use in applications involving extreme environmental conditions or in life support systems. Products supplied under Navitas Terms and Conditions. Navitas emiconductor, Navitas, GaNFast and associated logos are registered trademarks of Navitas. Copyright 208 Navitas emiconductor Inc. All rights reserved Navitas emiconductor Inc., 20 E El egundo Blvd, uite 20, El egundo, California 90245, UA. Contact info@navitassemi.com Final atasheet 2 Rev