OKI Semiconductor MR27V12800J
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1 MR27V12800J 8M Word 16 Bit or 16M Word 8 Bit P2ROM FEATURES 8,388,608-word 16-bit/16,777,216-word 8-bit electrically switchable configuration 3.0 V to 3.6 V power supply Access time 80 ns MAX (MR27V12800J-xxxTN) 100 ns MAX(MR27V12800J-xxxTNE) Operating current 25 ma MAX(5MHz) Standby current 10 µa MAX Input/Output TTL compatible Three-state output PACKAGES MR27V12800J-xxxTN, MR27V12800J-xxxTNE 48-pin plastic TSOP (TSOP I 48-P K) MR27V12800J-xxxTY, MR27V12800J-xxxTYE 48-pin plastic TSOP (TSOP I 48-P L) P2ROM ADVANCED TECHNOLOGY P2ROM stands for Production Programmed ROM. This exclusive Oki technology utilizes factory test equipment for programming the customers code into the P2ROM prior to final production testing. Advancements in this technology allows production costs to be equivalent to MASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following; Short lead time, since the P2ROM is programmed at the final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product. No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply. No additional programming charge, unlike Flash and OTP that require additional programming and handling costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price. Custom Marking is available at no additional charge. Pin Compatible with Mask ROM Issue Date: Jul. 9, 2004 PIN CONFIGURATION (TOP VIEW) MR27V12800J-xxxTN MR27V12800J-xxxTNE A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 A21 A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 Vss Vss D15/A 1 D7 D14 D6 D13 D5 D12 D4 V CC V CC A22 D11 D3 D10 D2 D9 D1 D8 D0 OE # Vss Vss MR27V12800J-xxxTY MR27V12800J-xxxTYE Vss 47 Vss 46 D15/A 1 45 D7 44 D14 43 D6 42 D13 41 D5 40 D12 39 D4 38 V CC 37 V CC 36 A22 35 D11 34 D3 33 D10 32 D2 31 D9 30 D1 29 D8 28 D0 27 OE # 26 Vss 25 Vss A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 A21 A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 48TSOP(Type-I) 1/9
2 BLOCK DIAGRAM A 1 8/ 16 Switch OE# CE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Address Buffer Row Decoder Column Decoder Memory Cell Matrix 8M 16-Bit or 16M 8-Bit Multiplexer Output Buffer D0 D2 D4 D6 D8 D10 D12 D14 D1 D3 D5 D7 D9 D11 D13 D15 In 8-bit output mode, these pins are placed in a high-z state and pin D15 functions as the A-1 address pin. PIN DESCRIPTIONS Pin name D15 / A 1 A0 to A22 D0 to D14 OE# V CC V SS Functions Data output / Address input Address inputs Data outputs Chip enable input Output enable input Word / Byte select input Power supply voltage Ground 2/9
3 FUNCTION TABLE Mode OE# V CC D0 to D7 D8 to D14 D15/A 1 Read (16-Bit) L L H D OUT Read (8-Bit) L L L D OUT Hi Z L/H 3.0 V H Output disable L H to Hi Z L 3.6 V H Standby H Hi Z L : Don t Care (H or L) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Value Unit Operating temperature under bias Ta 0 to 70 C Storage temperature Tstg 55 to 125 C Input voltage V I 0.5 to V CC +0.5 V Output voltage V O relative to V SS 0.5 to V CC +0.5 V Power supply voltage V CC 0.5 to 5 V Power dissipation per package P D Ta = 25 C 1.0 W Output short circuit current I OS 10 ma RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70 C) Parameter Symbol Condition Min. Typ. Max. Unit V CC power supply voltage V CC V Input H level V IH V CC = 3.0 to 3.6 V 2.2 V CC +0.5 V Input L level V Voltage is relative to V SS. : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. : -1.5V(Min.) when pulse width of undershoot is less than 10ns. V IL PIN CAPACITANCE (V CC = 3.0 V, Ta = 25 C, f = 1 MHz) Parameter Symbol Condition Min. Typ. Max. Unit Input C IN1 8 V I = 0 V 200 C IN2 Output C OUT V O = 0 V 10 pf 3/9
4 ELECTRICAL CHARACTERISTICS DC Characteristics (V CC = 2.7 to 3.6 V, Ta = 0 to 70 C) Parameter Symbol Condition Min. Typ. Max. Unit Input leakage current I LI V I = 0 to V CC 5 µa Output leakage current I LO V O = 0 to V CC 5 µa V CC power supply current I CCSC = V CC 10 µa (Standby) I CCST = V IH 1 ma V CC power supply current (Read) I CCA = V IL, OE# = V IH 25 ma f=5mhz Input H level V IH 2.2 V CC +0.5 V Input L level V IL V Output H level V OH I OH = 1 ma 2.4 V Output L level V OL I OL = 2 ma 0.4 V Voltage is relative to V SS. : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. : -1.5V(Min.) when pulse width of undershoot is less than 10ns. AC Characteristics Note 1 MR27V12800J-xxxTN, MR27V12800J-xxxTY Note 2 MR27V12800J-xxxTNE, MR27V12800J-xxxTYE (V CC = 3.0 to 3.6 V, Ta = 0 to 70 C) Parameter Symbol Condition Min. Max. Unit Address cycle time t C 80 (Note 1) 100 (Note 2) ns Address access time t ACC = OE# = V IL 80 (Note 1) 100 (Note 2) ns access time t CE OE# = V IL 80 (Note 1) 100 (Note 2) ns OE# access time t OE = V IL 30 ns Output disable time t CHZ OE# = V IL 0 20 ns t OHZ = V IL 0 20 ns Output hold time t OH = OE# = V IL 0 ns Measurement conditions Input signal level V/3 V Input timing reference level /2vcc Output load pf Output timing reference level /2Vcc Output load Output 50 pf (Including scope and jig) 4/9
5 TIMING CHART (READ CYCLE) 16-Bit Read Mode ( = V IH ) t C t C A0 to A22 t OH t CE t ACC t OE t OH t CHZ OE# t ACC t OHZ D0 to D15 Hi-Z Valid Data Valid Data Hi-Z 8-Bit Read Mode ( = V IL ) t C t C A-1 to A22 t OH t CE t ACC t OE t OH t CHZ OE# t ACC t OHZ D0 to D7 Hi-Z Valid Data Valid Data Hi-Z 5/9
6 PACKAGE DIMENSIONS TSOP(1)48-P K (Unit: mm) Mirror finish Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5µm) 5 Package weight (g) 0.55 TYP. Rev. No./Last Revised 1/Dec. 2, 1999 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 6/9
7 TSOP(1)48-P L (Unit: mm) 5 Rev. Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5µm) Package weight (g) 0.55 TYP. No./Last Revised 1/Feb. 27, 2003 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 7/9
8 REVISION HISTORY Document No. Date Previous Edition Page Current Edition Description FEDR27V12800J July Final edition 1 FEDR27V12800J Jan , 4 1, 4 Change tc, tacc, tce to 100ns FEDR27V12800J Jan Change P/N to MR27V12800J-xxxTNE FEDR27V12800J Mar. 10, , 4 1, 4 Added MR27V12800J-xxxTN FEDR27V12800J Jun. 6, , 3, 4 1, 3, 4 1. Change Ta to 0 C 2. Added MR27V12800J-xxxTY,TYE Jul. 9, Add P D condition and I OS = 10mA 8/9
9 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. 9/9
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FINAL Am27C040 4 Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time 90 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug in upgrade
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
1Mb (128K x 8) Unregulated Battery Voltage, One-time Programmable, Read-only Memory
Features Fast read access time 90ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Compatible with JEDEC standard Atmel AT27C010
256K (32K x 8) Paged Parallel EEPROM AT28C256
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
A4 A3 A2 A1 A0 DQ0 DQ15. DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12
128K x 16 Low Power SRAM Rev 1.5 04/2007 Features 48-Ball BGA (CSP), Top View Single power supply voltage of 2.7V to 3.6V Power down features using CE Low operating current : 30mA(max for 55 ns) Maximum
128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations
128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
P4C1299/P4C1299L. ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES DESCRIPTION. Full CMOS, 6T Cell. Data Retention with 2.0V Supply (P4C1299L)
FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 15/20/25/35 ns (Commercial/Industrial) 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Output Enable (OE)
512K (64K x 8) Unregulated Battery. Programmable, Read-only Memory
Features Fast read access time 70ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Pin compatible with JEDEC standard Atmel AT27C512R
32M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 33,578,432-bit high-speed Static Random Access Memory organized as 4M(2M) words
256K (32K x 8) Unregulated Battery-Voltage High-Speed OTP EPROM AT27BV256
Features Fast Read Access Time 70 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Pin Compatible with JEDEC Standard AT27C256R Low
HT23C128 CMOS 16K 8-Bit Mask ROM
CMOS 16K8-Bit Mask ROM Features Operating voltage: 2.7V~5.5V Low power consumption Operation: 25mA max. (V CC =5V 10mA max. (V CC =3V Standby: 30A max. (V CC =5V 10A max. (V CC =3V Access time: 150ns max.
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM DESCRIPTION The TC51WHM516AXBN is a 33,554,432-bit pseudo static random access memory(psram) organized
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs
IS62WV10248EALL/BLL IS65WV10248EALL/BLL. 1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating TTL compatible interface levels Single power supply
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Features Fast Read Access Time - 45 ns Low-Power CMOS Operation 100 µa max.
Pin Connection (Top View)
TOSHIBA TC551001BPL/BFL/BFTL/BTRL-70L/85L SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits
Fast read access time 70ns Low-power CMOS operation 100μA max standby 30mA max active at 5MHz. JEDEC standard packages 32-lead PDIP 32-lead PLCC
Atmel AT7C040 4Mb (51K x 8) OTP, EPROM DATASHEET Features Fast read access time 70ns Low-power CMOS operation 100μA max standby 30mA max active at 5MHz JEDEC standard packages 3-lead PDIP 3-lead PLCC 5V
P4C1257/P4C1257L. ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS. Separate Data I/O
P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES Full CMOS High Speed (Equal Access and Cycle s) 12/15/20/25 ns (Commercial) 12/15/20/25 ns (Industrial) 25/35/45/55/70 ns (Military)
CBTS3253 Dual 1-of-4 FET multiplexer/demultiplexer with Schottky diode clamping
INTEGRATED CIRCUITS 2002 Nov 06 Philips Semiconductors FEATURES 5 Ω switch connection between two ports TTL-compatible input levels Schottky diodes on I/O clamp undershoot Minimal propagation delay through
HT27C020 OTP CMOS 256K 8-Bit EPROM
OTP CMOS 256K 8-Bit EPROM Features Operating voltage: +5.0V Programming voltage V PP=12.5V±0.2V V CC=6.0V±0.2V High-reliability CMOS technology Latch-up immunity to 100mA from -1.0V to V CC+1.0V CMOS and
8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
Battery-Voltage. 1-Megabit (128K x 8) Unregulated OTP EPROM AT27BV010. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
1Mb (64K x 16) Unregulated Battery Voltage, High-speed, One-time Programmable, Read-only Memory
Features Fast read access time 90ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Pin compatible with JEDEC standard Atmel AT27C1024
Single Clock Generator
ASAHI KASEI EMD CORPORATION Single Clock Generator AK8113 Features Output Frequency Range: 74.17582MHz / 74.25MHz (Selectable) Input Frequency: 27MHz Low Jitter Performance: 15 ps (Typ.) Period, 1σ Low
Rev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
INTEGRATED CIRCUITS. 74ABT125 Quad buffer (3-State) Product specification Supersedes data of 1996 Mar 05 IC23 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1996 Mar 05 IC23 Data Handbook 1998 Jan 16 FEATURES Quad bus interface 3-State buffers Live insertion/extraction permitted Output capability: +64mA/ 32mA Latch-up
Semiconductor MSC GENERAL DESCRIPTION FEATURES FEDL FEDL Previous version: Nov. 1997
Semiconductor MSC7170-01 FEDL7170-03 Semiconductor This version: MSC7170-01 Sep. 2000 Previous version: Nov. 1997 5 7 Dot Character 16-Digit 2-Line Display Controller/Driver with Keyscan Function GENERAL
16 Meg FPM DRAM AS4LC4M4. 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT ACTIVE POWER DISSIPATION PERFORMANCE RANGE
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 FEATURES Fast Page Mode Operation CAS\-before-RAS\ Refresh Capability RAS\-only and
Battery-Voltage. 1-Megabit (64K x 16) Unregulated. High-Speed OTP EPROM AT27BV1024. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Pin Compatible with JEDEC Standard AT27C1024 Low
CBTS3306 Dual bus switch with Schottky diode clamping
INTEGRATED CIRCUITS Dual bus switch with Schottky diode clamping 2001 Nov 08 File under Integrated Circuits ICL03 FEATURES 5 Ω switch connection between two ports TTL-compatible input levels Package options
Rev. No. History Issue Date Remark
32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package
TC4001BP, TC4001BF, TC4001BFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4001BP/BF/BFT TC4001BP, TC4001BF, TC4001BFT TC4001B Quad 2 Input NOR Gate The TC4001B is 2-input positive NOR gate, respectively. Since the
Hex inverting buffer; 3-state
Rev. 9 18 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer with 3-state outputs. The 3-state outputs are controlled by
Real-Time Clock (RTC) Module. Calendar in day of the week, day of the month, months, and years with automatic leap-year adjustment
Features Direct clock/calendar replacement for IBM AT-compatible computers and other applications Functionally compatible with the DS1287/DS1287A and MC146818A 114 bytes of general nonvolatile storage
Revision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final 11 Marking Information
Quad 2-input NAND Schmitt trigger
Quad 2-input NAND Schmitt trigger BU4093B / BU4093BF / BU4093BF The BU4093B, BU4093BF, and BU4093BF are 4-circuit, 2-input NAND gates whose input pins all have a Schmitt trigger function. As the circuit
RMLV0808BGSB - 4S2. 8Mb Advanced LPSRAM (1024k word 8bit) Description. Features. Part Name Information. R10DS0232EJ0200 Rev
8Mb Advanced LPSRAM (1024k word 8bit) Description The RMLV0808BGSB is a family of 8-Mbit static RAMs organized 1,048,576-word 8-bit, fabricated by Renesas s high-performance Advanced LPSRAM technologies.
INTEGRATED CIRCUITS. 74F175A Quad D flip-flop. Product specification Supersedes data of 1996 Mar 12 IC15 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1996 Mar 12 IC15 Data Handbook 2000 Jun 30 FEATURES Four edge-triggered D-type flip-flops Buffered common clock Buffered asynchronous Master Reset True and complementary
NTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package
NTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package NTE27C256 15P Integrated Circuit 256 Kbit (32Kb x 8) OTP EPROM 28 Lead DIP Type Packag