CDCR81 DIRECT RAMBUS CLOCK GENERATOR

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1 300-MHz Differential Clock Source for Direct RAMBUS Memory Systems for an 600-MHz Data Transfer Rate Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications Operates From a Single 3.3-V Supply and 120-mW at 300 MHz (Typ) Packaged in a Shrink Small-Outline Package (DBQ) Wide Phase-Lock Input Frequency Range 33 MHz to 100 MHz No External Components Required for PLL Supports Independent Channel Clocking Spread Spectrum Clocking Tracking Capability to Reduce EMI Designed For Use With TI s 133-MHz Clock Synthesizers CDC925, CDC924, CDC922 and CDC921 V DD IR REF V DD P GNDP GNDI PM SYNN GNDC V DD C V DD IPD STOPB PWRDNB DBQ PACKAGE (TOP VIEW) NC No internal connection S0 S1 V DD O GNDO NC B GNDO V DD O MULT0 MULT1 S2 description The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on desktop, workstation, server and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REF and P clock references to the DRCG and memory controller, respectively. The DRCG multiplies REF and drives a high-speed BUS to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the P and BUS frequencies by ratios M and N such that P/M = SYN/N, where SYN = BUS/4. The DRCG detects the phase difference between P/M and SYN/N and adjusts the phase of BUS such that the skew between P/M and SYN/N is minimized. This allows data to be transferred across the SYN/P boundary without incurring additional latency. User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUS frequencies ranging from 267 MHz to 400 MHz with clock references ranging from 33 MHz to 100 MHz. The meets Rambus Clock Generator, Revision 1.0 specification up to 300 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REF on the Rambus channel and to place the outputs in a high-impedance state for board testing. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Direct Rambus and Rambus are trademarks of Rambus Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1999, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 description (continued) The is characterized for operation over free-air temperatures of 0 C to 85 C. functional block diagram PWRDWNB S0 S1 S2 STOPB Test MUX Bypass MUX ByP PLL REF B PLL Phase Aligner B A PA φd 2 MULT0 MULT1 PM SYNN FUNCTION TABLE MODE S0 S1 S2 B Normal Phase aligned clock Phase aligned clock B Bypass PLL PLLB Test REF REFB Output test (OE) 0 1 X Hi-Z Hi-Z Reserved Reserved Reserved Hi-Z Hi-Z X = don t care, Hi-Z = high impedance 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION 20 O Output clock B 18 O Output clock (complement) GNDC 8 GND for phase aligner GNDI 5 GND for control inputs GNDO 17, 21 GND for clock outputs GNDP 4 GND for PLL MULT0 15 I PLL multiplier select MULT1 14 I PLL multiplier select NC 19 Not used PM 6 I Phase detector input PWRDNB 12 I Active low power down REF 2 I Reference clock S0 24 I Mode control S1 23 I Mode control S2 13 I Mode control STOPB 11 I Active low output disable SYNN 7 I Phase detector input VDDC 9 VDD for phase aligner VDDIPD 10 Reference voltage for phase detector inputs and STOPB VDDIR 1 Reference voltage for REF VDDO 16, 22 VDD for clock outputs VDDP 3 VDD for PLL POST OFFICE BOX DALLAS, TEXAS

4 PLL divider selection Table 1 lists the supported REF and BUS frequencies. Other REF frequencies are permitted, provided that (267 MHz < BUS < 400 MHz) and (33 MHz < REF < 100 MHz). MULT0 clock output driver states Table 1. REF and BUS Frequencies MULT1 REF (MHz) MULTIPLY RATIO BUS (MHz) /3 267 Table 2. Clock Output Driver States STATE PWRDNB STOPB B Powerdown 0 X GND GND stop 1 0 VX, STOP VX, STOP Normal 1 1 Depending on the state of S0, S1, and S2. PA/PLL/ REF PAB/PLLB/ REFB absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, V DD (see Note 1) V to 4 V Output voltage range, V O, at any output terminal V to V DD V Input voltage range,v I, at any input terminal V to V DD V ESD rating TBD Continuous total power dissipation see Dissipation Rating Table Operating free-air temperature range, T A C to 85 C Storage temperature range, T stg C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25 C TA = 70 C POWER RATING TA = 85 C POWER RATING DBQ 1400 mw 11 mw/ C 905 mw 740 mw This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD V High-level input voltage, VIH (CMOS) 0.7 VDD V Low-level input voltage, VIL (CMOS) 0.3 VDD V Initial phase error at phase detector inputs (required range for phase aligner) 0.5 tc(pd) 0.5 tc(pd) REF low-level input voltage, VIL 0.3 VDDIR V REF high-level input voltage, VIH 0.7 VDDIR V Input signal low voltage, VIL (STOPB) 0.3 VDDIPD V Input signal high voltage, VIH (STOPB) 0.7 VDDIPD V Input reference voltage for (REF) (VDDIR) V Input reference voltage for (PM and SYSN) (VDDIPD) V High-level output current, IOH 16 ma Low-level output current, IOL 16 ma Operating free-air temperature, TA 0 85 C timing requirements MIN MAX UNIT Input cycle time, tc(in) ns Input cycle-to-cycle jitter 250 ps Input duty cycle over 10,000 cycles 40% 60% Input frequency modulation, fmod khz Modulation index, non-linear maximum 0.5% 0.6% Phase detector input cycle time (PM and SYNN) ns Input slew rate, SR 1 4 V/ns Input duty cycle (PM and SYNN) 25% 75% POST OFFICE BOX DALLAS, TEXAS

6 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V O(STOP) Output voltage during Stop (StopB=0) See Figure VO(X) Output crossing-point voltage See Figures 1 and V VO Output voltage swing See Figure V V IK Input clamp voltage VDD = V, II = 18 ma 1.2 V See Figure 1 2 VOH High-level output voltage VDD = min to max, IOH = 1 ma VDD 0.1 V VDD = V, IOH = 16 ma 2.4 See Figure 1 1 VOL Low-level output voltage VDD = min to max, IOL = 1 ma 0.1 V VDD = V, IOL = 16 ma 0.5 VDD = V, VO = 1 V IOH High-level output current VDD = 3.3 V, VO = 1.65 V 51 ma VDD = V, VO = V VDD = V, VO = 1.95 V IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 65 ma VDD = V, VO = 0.4 V IOZ High-impedance-state output current S0 = 0, S1 = 1 ±10 µa IOZ(STOP) IOZ(PD) IIH High-impedance-state output current during stop High-impedance-state output current in powerdown state REF, PM, High-level input SYNN, STOPB current PWRDNB, S0, S1, S2, MULT0, MULT1 REF, PM, Low-level input SYNN, STOPB IIL current PWRDNB, S0, S1, S2, MULT0, MULT1 ZO Output impedance Stop= 0, VO = GND or VDD ±100 µa PWDNB= 0, VO = GND or VDD V µa VDD = V, VI = VDD 10 VDD = V, VI = VDD 10 VDD = V, VI = 0 10 VDD = V, VI = 0 10 High state RI at IO 14.5 ma to 16.5 ma Low state RI at IO 14.5 ma to 16.5 ma Reference current VDDIR, VDDIPD VDD = V, µa µa Ω PWRDNB = 0 50 µa PWRDNB = ma CI Input capacitance VI = VDD or GND 1.8 pf CO Output capacitance VO = VDD or GND 3.1 pf IDD(PD) Supply current in powerdown state REF = 0 MHz to 100 MHz, PWDNB = 0, STOPB = µa IDD(STOP) Supply current in stop state BUS configured for 400 MHz 30 ma IDD(NORMAL) Supply current in normal state BUS = 400 MHz 70 ma VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP All typical values are at VDD = 3.3 V, TA = 25 C. 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tc(out) Clock output cycle time ns t(jitter) Stopped phase 267 MHz See Figure 3 60 ps Total cycle jitter over 1, 2, alignment 400 MHz 3, 4, 5, or 6 clock cycles Infinite phase 267 MHz 80 See Figure 3 ps alignment 300 MHz 70 t(phase) Phase detector phase error for distributed loop Static phase error ps t(phase, SSC) PLL output phase error when tracking SSC Dynamic phase error ps t(dc) Output duty cycle over 10,000 cycles See Figure 4 45% 55% Stopped phase 267 MHz alignment 400 MHz See Figure 5 50 ps t(dc, err) Output cycle-to-cycle 267 MHz 70 duty cycle error Infinite it phase 300 MHz See Figure 5 80 ps alignment 400 MHz 90 tr, tf t Output rise and fall times (measured at 20%-80% of output voltage) Difference between rise and fall times on a single device (20% 80%) tf tr All typical values are at VDD = 3.3 V, TA = 25 C. state transition latency specifications t(powerup) t(vddpowerup) t(mult) t(on) t(setl) PARAMETER FROM TO Delay time, PWRDNB to /B output settled (excluding t(distlock)) Delay time, PWRDNB to internal PLL and clock are on and settled Delay time, powerup to /B output settled Delay time, powerup to internal PLL and clock are on and settled MULT0 and MULT1 change to /B output resettled (excluding t(distlock)) STOPB to /B glitch-free clock edges STOPB to /B output settled to within 50 ps of the phase before STOPB was disabled Powerdown VDD See Figure ps See Figure ps Normal Normal TEST CONDITIONS MIN TYP MAX UNIT See Figure 8 3 See Figure ms ms Normal Normal See Figure 9 1 ms Stop Stop t(off) STOPB to /B output disabled Normal t(powerdown) t(stop) Delay time, PWRDNB to the device in powerdown mode Maximum time in STOP (STOPB = 0) before re-entering normal mode (STOPB = 1) STOPB Normal See Figure ns Normal See Figure cycles Stop Powerdown See Figure 10 5 ns 1 ms STOPB Normal 100 µs POST OFFICE BOX DALLAS, TEXAS

8 state transition latency specifications (continued) t(on) t(distlock) PARAMETER FROM TO Minimum time in normal mode (STOPB = 1) before re-entering STOP (STOPB = 0) Time from when /B output is settled to when the phase error between SYNN and PM falls within t(err-pd) Normal Unlocked stop TEST CONDITIONS MIN TYP MAX UNIT 100 ms Locked 5 ms PARAMETER MEASUREMENT INFORMATION 68 Ω, ±5% 10 pf 39 Ω, ±5% RT = 28 Ω 68 Ω, ±5% 39 Ω, ±5% 100 pf RT = 28 Ω 10 pf Figure 1. Test Load and Voltage Definitions (V O(STOP), V O(X), V O, V OH, V OL ) B tc1 tc2 Cycle-to-cycle jitter = tc1 tc2 over consecutive cycles Figure 2. Cycle-to-Cycle Jitter B tc3 tc4 Cycle-to-cycle jitter = tc3 tc4 over consecutive cycles Figure 3. Short Term Cycle-to-Cycle Jitter over 4 Cycles 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 PARAMETER MEASUREMENT INFORMATION B tpd1 Duty cycle = (tpd1/tc5) tc5 Figure 4. Output Duty Cycle B tpd2 tpd3 tc6 tc7 Duty cycle error = tpd2 tpd3 Figure 5. Duty Cycle Error (Cycle-to-Cycle) B VO(X)+ VO(X), nom VO(X) Figure 6. Crossing-Point Voltage 80% 20% VOH VOL tr tf Figure 7. Voltage Waveforms PWRDNB tpowerup tpowerdown /B ÎÎÎÎÎÎÎ ÎÎ Figure 8. PWRDNB Transition Timings POST OFFICE BOX DALLAS, TEXAS

10 MULT0 and/or MULT1 PARAMETER MEASUREMENT INFORMATION tmult /B ÎÎÎÎÎÎÎÎ Figure 9. MULT Transition Timings ton tstop STOPB /B ton (see Note A) tsetl ÎÎÎÎ ÎÎ toff (see Note A) NOTE A: Vref = VO ±200 mv Output clock not specified glitches ok Clock enabled and glitch free Clock output settled within 50 ps of the phase before disabled Figure 10. STOPB Transition Timings 10 POST OFFICE BOX DALLAS, TEXAS 75265

11 PARAMETER MEASUREMENT INFORMATION 0 HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE I OH High-Level Output Current A Weak Rambus (min) Nom Strong Rambus (max) VOH High-Level Output Voltage V Figure 11. Pullup IBIS I/V Chart 0.12 LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE I OL Low-Level Output Current A Rambus (max) Strong Nom Weak Rambus (min) VOL Low-Level Output Voltage V Figure 12. Pulldown IBIS I/V Chart POST OFFICE BOX DALLAS, TEXAS

12 DBQ (R-PDSO-G**) 24 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE (0,64) (0,30) (0,20) (0,13) M (3,99) (3,81) (6,20) (5,80) (0,20) NOM 1 12 Gage Plane A (0,25) (0,89) (0,40) (1,75) MAX (0,25) (0,10) Seating Plane (0,10) DIM PINS ** A MAX (5,00) (8,74) (8,74) A MIN (4,78) (8,56) (8,56) /C 02/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed (0,15). D. Falls within JEDEC MO POST OFFICE BOX DALLAS, TEXAS 75265

13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency