S3922/S3923 series. NMOS linear image sensor. Voltage output type with current-integration readout circuit and impedance conversion circuit.

Transcription

1 IMAGE SENSOR NMOS linear image sensor S39/S393 series Voltage output type with current-integration readout circuit and impedance conversion circuit NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning circuit is made up of N-channel MOS transiors, operates at low power consumption and is easy to handle. Each photodiode has a large active area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output linearity and wide dynamic range. S39/S393 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. The output is available in boxcar waveform allowing signal readout with a simple external circuit. The photodiodes of S39 series have a height of 0.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S393 series also have a height of 0.5 mm but are arrayed at a spacing of 5 µm. The photodiodes are available in 3 different pixel quantities for each series, 8 (S39-8Q), 56 (S39-56Q, S393-56Q) and 5 (S39-5Q, S393-5Q) and 04 (S393-04Q). Quartz glass is the andard window material. Features Applications l Built-in current-integration readout circuit utilizing l Multichannel spectrophotometry video line capacitance and impedance conversion l Image readout syem circuit (boxcar waveform output) l Wide active area Pixel pitch: 50 µm (S39 series) 5 µm (S393 series) Pixel height: 0.5 mm l High UV sensitivity with good ability l Low dark current and high saturation charge allow a long integration time and a wide dynamic range at room temperature l Excellent output linearity and sensitivity spatial uniformity l Low voltage, single power supply operation l Start pulse, clock pulse and video line reset pulse are CMOS logic compatible Figure Equivalent circuit Figure Active area ructure START CLOCK CLOCK ADDRESS SWITCH ACTIVE PHOTODIODE SATURATION CONTROL GATE SATURATION CONTROL DRAIN ADDRESS SWITCH DUMMY DIODE DIGITAL SHIFT RESISTER (MOS SHIFT RESISTER) END OF SCAN SOURCE FOLLOWER CIRCUIT ACTIVE VIDEO DUMMY VIDEO OXIDATION SILICON b a 0.5 mm.0 µm RESET SWITCH RESET RESET V N TYPE SILICON.0 µm 400 µm KMPDC009EA P TYPE SILICON S39 SERIES: a=50 µm, b=45 µm S393 SERIES: a=5 µm, b=0 µm Absolute maximum ratings Parameter Symbol Value KMPDA0EA Supply voltage 5 V pulse (φ, φ, φ, φ) voltage Vφ 5 V Power consumption * P 0 mw Operating temperature * Topr -40 to +65 C Storage temperature Tg -40 to +85 C *: =5 V, Vr=.5 V *: No condensation

2 NMOS linear image sensor S39/S393 series Shape specifications Parameter S39- S39- S39- S393- S393- S393-8Q 56Q 5Q 56Q 5Q 04Q Number of pixels Package length mm Number of pin - Window material * 3 Quartz Quartz - Weight g *3: Fiber optic plate is available. Specifications (Ta=5 C) Parameter Symbol S39 series S393 series Min. Typ. Max. Min. Typ. Max. Pixel pitch µm Pixel height mm Spectral response range (0 % of peak) λ 00 to to 000 nm Peak sensitivity wavelength λp nm Photodiode dark current * 4 ID pa Photodiode capacitance * 4 Cph pf Saturation exposure * 4, * 5 Esat mlx s Saturation charge * 4 Qsat pc (-8Q) (-56Q) - mv Saturation output voltage * 4 Vsat (-56Q) (-5Q) - mv (-5Q) (-04Q) - mv Photo response non-uniformity * 6 PRNU - - ±3 - - ±3 % *4: V=.5 V, =5.0 V, Vφ=5.0 V *5: 856 K, tungen lamp *6: 50 % of saturation, excluding the art pixel and la pixel Electrical characteriics (Ta=5 C) Parameter Symbol Condition S39 series S393 series Min. Typ. Max. Min. Typ. Max. Clock pulse (φ, φ) High Vφ, Vφ (H) V voltage Low Vφ, Vφ (L) V Start pulse (φ) voltage High Vφs (H) 4.5 Vφ Vφ 0 V Low Vφs (L) V pulse ( φ) High Vrφ (H) 4.5 Vφ Vφ 0 V voltage Low Vrφ (L) V Source follower circuit drain voltage 4.5 Vφ Vφ 0 V voltage ( V) * 7 * 8 Vr.0 Vφ -.5 Vφ Vφ -.5 Vφ -.0 V Saturation control gate voltage Vscg V Saturation control drain voltage * 8 Vscd - Vr - - Vr - V Clock pulse (φ, φ) rise / fall time trφ, trφ tfφ, tfφ ns Clock pulse (φ, φ) pulse width tpwφ, tpwφ ns Start pulse (φ) rise / fall time trφs, tfφs ns Start pulse (φ) pulse width tpwφs ns pulse rise / fall time trrφ, tfrφ ns Start pulse (φ) and clock pulse (φ) overlap tφov ns Clock pulse (φ) and reset pulse ( φ) overlap tφovr ns Clock pulse (φ) and reset pulse ( φ) delay time tdφr ns Clock pulse (φ, φ) space * 9 X, X trf trf ns Clock pulse (φ, φ) space tsφr ns Data rate * 0 f khz Video delay time tvd - 00 (-8 Q) (-56 Q) - ns 50 % of - 50 (-56 Q) (-5 Q) - ns saturation * 0-00 (-5 Q) (-04 Q) - ns - (-8 Q) (-56 Q) - pf Clock pulse (φ, φ) Cφ 5 V bias - 36 (-56 Q) (-5 Q) - pf line capacitance - 67 (-5 Q) (-04 Q) - pf pulse ( φ) line capacitance Cr 5 V bias pf - (-8 Q) - - (-56 Q) - pf Saturation control gate (Vscg) Cscg 5 V bias - 0 (-56 Q) (-5 Q) - pf line capacitance - 35 (-5 Q) (-04 Q) - pf Output impedance Zo =5 V Vr=.5 V Ω *7: Vφ is input pulse voltage. (refer to figure 8) *8: Terminal pin 7 is used for both V and saturation control drain voltage. *9: trf is the clock pulse rise or fall time. A clock pulse space of rise time/fall time - 0 ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 0 ns. (refer to figure 7) *0: V=.5 V, =5.0 V, Vφ =5.0 V

3 NMOS linear image sensor S39/S393 series Figure 3 Dimensional outlines (unit: mm) S39-8Q, S393-56Q S39-56Q, S393-5Q ACTIVE AREA ± ± 0. ACTIVE AREA ± ± ± PHOTOSENSITIVE SURFACE.3 ± 0.* ± PHOTOSENSITIVE SURFACE.3 ± 0.* * Optical diance from the outer surface of the quartz window to the chip surface * Optical diance from the outer surface of the quartz window to the chip surface KMPDA008EA KMPDA009EA S39-5Q, S393-04Q Figure 4 Pin connection ACTIVE AREA ± ± Vscg ± PHOTOSENSITIVE SURFACE.3 ± 0. * RESET RESET V (Vscd) ACTIVE VIDEO DUMMY VIDEO END OF SCAN Vsub , Vsub and should be grounded KMPDC005EA * Optical diance from the outer surface of the quartz window to the chip surface KMPDA00EA

4 NMOS linear image sensor S39/S393 series φ, φ Terminal or output Description Pulses for operating the MOS shift regier. The video data rate is equal to the clock pulse frequency since the video output signal is obtained synchronously with the rise of φ pulse. Pulse for arting the MOS shift regier operation. The time interval between art pulses is equal to the signal accumulation time. φ - Connected to the anode of each photodiode. This should be grounded. Vscg Used for rericting blooming. This should be grounded. φ With φ at high level, the video line is reset at the V voltage. V The V terminal connects to each photodiode cathode via the video line when the address turns on. A positive voltage should be applied to the V terminal to use each photodiode at a reverse bias. Setting the V voltage to.5 V is recommended when the amplitude of φ, φ and φ is 5 V. Terminal pin 7 is used for both V and Vscd. Vscd Used for rericting blooming. This should be biased at a voltage equal to V. Active video Output Low-impedance video output signal after internal current-voltage conversion. Negative-going output including DC offset. Dummy video Output This has the same ructure as the active video, but is not connected to photodiodes, so only DC offset is output. Leave this terminal open when not used. Vsub - Connected to the silicon subrate. This should be grounded. End of scan Output - Should be grounded. Supply voltage to the internal impedance conversion circuit. A voltage equal to the amplitude of each clock should be applied to this terminal. This should be pulled up at 5 V by using a 0 kω resior. This is a negative going pulse that appears synchronously with the φ timing right after the la photodiode is addressed. Figure 5 Spectral response (typical example) Figure 6 Output voltage vs. exposure 0.3 (Ta=5 C) (Typ. V=.5 V, =5.0 V, V =5.0 V, light source: 856 K) 0 (Typ. V=.5 V, =5.0 V, V =5.0 V, light source: 856 K) 0 SATURATION OUTPUT VOLTAGE SATURATION OUTPUT VOLTAGE PHOTO SENSITIVITY (A/W) OUTPUT VOLTAGE (V) S39-8Q S39-56Q S39-5Q SATURATION EXPOSURE OUTPUT VOLTAGE (V) S393-56Q S393-5Q S393-04Q SATURATION EXPOSURE WAVELENGTH (nm) EXPOSURE (lx s) EXPOSURE (lx s) KMPDB049EA KMPDB00EA KMPDB0EA Conruction of image sensor The NMOS image sensor consis of a scanning circuit made up of MOS transiors, a photodiode array, and a switching transior array that addresses each photodiode, all integrated onto a monolithic silicon chip. Figure shows the circuit of a NMOS linear image sensor. The MOS scanning circuit operates at low power consumption and generates a scanning pulse train by using a art pulse and -phase clock pulses in order to turn on each address sequentially. Each address switch is comprised of an NMOS transior using the photodiode as the source, the video line as the drain and the scanning pulse input section as the gate. The photodiode array operates in charge integration mode so that the output is proportional to the amount of light exposure (light intensity integration time). Each cell consis of an active photodiode and a dummy diode, which are respectively connected to the active video line and the dummy video line via a switching transior. Each of the active photodiodes is also connected to the saturation control drain via the saturation control gate, so that the photodiode blooming can be suppressed by grounding the saturation control gate. Applying a pulse signal to the saturation control gate triggers all reset. (See Auxiliary functions.)

5 NMOS linear image sensor S39/S393 series Figure shows the schematic diagram of the photodiode active area. This active area has a PN junction consiing of an N-type diffusion layer formed on a P-type silicon subrate. A signal charge generated by light input accumulates as a capacitive charge in this PN junction. The N-type diffusion layer provides high UV sensitivity but low dark current. Driver circuit A art pulse φ and -phase clock pulses φ, φ are needed to drive the shift regier. These art and clock pulses are positive going pulses and CMOS logic compatible. The -phase clock pulses φ, φ can be either completely separated or complementary. However, both pulses mu not be High at the same time. A clock pulse space (X and X in Figure 7) of a rise time/fall time - 0 ns or more should be input if the rise and fall times of φ, φ are longer than 0 ns. The φ and φ clock pulses Figure 7 Timing chart for driver circuit mu be held at High at lea 00 ns. Since the photodiode signal is obtained at the rise of each φ pulse, the clock pulse frequency will equal the video data rate. The amplitude of art pulse φ is the same as the φ and φ pulses. The shift regier arts the scanning at the High level of φ, so the art pulse interval is equal to signal accumulation time. The φ pulse mu be held High at lea 00 ns and overlap with φ at lea for 00 ns. To operate the shift regier correctly, φ mu change from the High level to the Low level only once during High level of φ. The timing chart for each pulse is shown in Figure 7. End of scan The end of scan (EOS) signal appears in synchronization with the φ timing right after the la photodiode is addressed, and the EOS terminal should be pulled up at 5 V using a 0 kω resior. Figure 8 V voltage margin END OF SCAN V s (H) V s (L) V (H) V (L) V (H) V (L) Vr (H) Vr (L) ACTIVE VIDEO OUTPUT tpw s tr s tpw tpw tvd tf s RESET V VOLTAGE (V) MAX. RECOMMENDED RESET V VOLTAGE RESET V VOLTAGE RANGE tr tf MIN. X X tf RESET t ov ts r- t ovr td r- CLOCK PULSE AMPLITUDE (V) tfr trr KMPDB0047EA KMPDC006EA Signal readout circuit S39/S393 series include a current integration circuit utilizing the video line capacitance and an impedance conversion circuit. This allows signal readout with a simple external circuit. However, a positive bias mu be applied to the video line because the photodiode anode of NMOS linear image sensors is at 0 V (). This is done by adding an appropriate pulse to the φ terminal. The amplitude of the reset pulse should be equal to φ, φ and φ. When the reset pulse is at the high level, the video line is set at the V voltage. Figure 8 shows the V voltage margin. A higher clock pulse amplitude allows higher V voltage and saturation charge. Conversely, if the V voltage is set at a low level with a higher clock pulse amplitude, the rise and fall times of video output waveform can be shortened. Setting the V voltage to.5 V is recommended when the amplitude of φ, φ, φ and φ is 5 V. To obtain a able output, an overlap between the reset pulse ( φ) and φ mu be settled. ( φ mu rise while φ is at the high level.) Furthermore, φ mu fall while φ is at the low level. S39/S393 series provide output signals with negativegoing boxcar waveform which include a DC offset of approximately V when V is.5 V. If you want to remove the DC offset to obtain the positive-going output, the signal readout circuit and pulse timing shown in Figure 9 are recommended. In this circuit, Rs mu be larger than 0 kω. Also, the gain is determined by the ratio of Rf to Rs, so choose the Rf value that suits your application.

6 NMOS linear image sensor S39/S393 series Hamamatsu provides the following driver circuits and related products (sold separately). Product name Type No. Content Feature Driver circuit C7885 Low co driver circuit Low price Single power supply (+5 V) operation C7885G C C85-0 Boxcar waveform output Pulse generator C85-0 C7885 series Cable A86 C7883 to C7885 series B, length m Figure 9 Readout circuit example and timing chart +5 V + +5 V 0 kω +.5 V V (Vscd) Vscg Vsub EOS DUMMY VIDEO ACTIVE VIDEO OPEN Rs 0 kω + +5 V EOS + Rf KMPDC008EA KMPDC007EA Anti-blooming function If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To avoid this problem and maintain the signal purity, applying the same voltage as the V voltage to the saturation control drain and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should be applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an optimum bias voltage should be selected. Auxiliary functions ) All reset In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that uses the readout line, S39/S393 series can reset the photodiode charge by applying a pulse to the saturation control gate. The amplitude of this pulse should be equal to the φ, φ, φ, φ pulses and the pulse width should be longer than 5 µs. When the saturation control gate is set at the High level, all photodiodes are reset to the saturation control drain potential (equal to video bias). Conversely, when the saturation control gate is set at the Low level (0 V), the signal charge accumulates in each photodiode without being reset. ) Dummy video S39/S393 series have a dummy video line. Positive-polarity video signals with the DC offset remove can be obtained by differential amplification of the active video line and dummy video line outputs. When not needed, leave this unconnected. Precautions for using NMOS linear image sensors ) Electroatic countermeasures NMOS linear image sensors are designed to resi atic electrical charges. However, take sufficient cautions and countermeasures to prevent damage from atic charges when handling the sensors. ) Window If du or grime icks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or cotton swab slightly moiened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not rub the window with dry cloth or cotton swab as this may generate atic electricity. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. 00 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 6- Ichino-cho, Hamamatsu City, Japan, Telephone: (8) , Fax: (8) , U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 690, Bridgewater, N.J , U.S.A., Telephone: () , Fax: () Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerr. 0, D-8 Herrsching am Ammersee, Germany, Telephone: (49) , Fax: (49) France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 988 Massy Cedex, France, Telephone: 33-() , Fax: 33-() ed Kingdom: Hamamatsu Photonics UK Limited: Howard Court, 0 Tewin Road, Welwyn Garden City, Hertfordshire AL7 BW, ed Kingdom, Telephone: (44) , Fax: (44) North Europe: Hamamatsu Photonics Norden AB: Smidesvägen, SE-7 4 Solna, Sweden, Telephone: (46) , Fax: (46) Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, /E, 000 Arese, (Milano), Italy, Telephone: (39) , Fax: (39) Cat. No. KMPD037E0 Apr. 00 DN