CCD area image sensor

Transcription

1 Back-thinned FFT-CCD The is a family of FFT-CCD image sensors specifically designed for low-light-level detection in scientific applications. By using the binning operation, the can be used as a linear image sensor having a long aperture in the direction of the device length. This makes the suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal processing speed compared with conventional methods by which signals are digitally added by an external circuit. The also features low noise and low dark signal (MPP mode operation). This enables low-light-level detection and long integration time, thus achieving a wide dynamic range. The has an effective pixel size of μm and is available in image areas ranging from (H).392 (V) mm 2 (52 58 pixels) up to a large image area of (H) (V) mm 2 (24 25 pixels). Features Non-cooled type: S73 series One-stage TE-cooled type: S73 series Pixel size: μm Line, pixel binning Greater than 9% quantum efficiency at peak sensitivity wavelength Wide spectral response range Low readout noise Wide dynamic range MPP operation High UV sensitivity with good stability Applications Fluorescence spectrometer, ICP Industrial inspection Semiconductor inspection DNA sequencer Low-light-level detection Raman spectrometer Selection guide Type no. Cooling Number of total pixels Number of effective Image size pixels [mm (H) mm (V)] S S Non-cooled S S S73-96S S73-97S One-stage S73-6S TE-cooled S73-7S Note: Two-stage TE-cooled type (S732-6/-7) is available upon request (made-to-order product). Suitable multichannel detector head C74 C74

2 Structure Parameter S73 series S73 series Pixel size (H V) μm Vertical clock phase 2 phases Horizontal clock phase 2 phases Output circuit One-stage MOSFET source follower Package 24-pin ceramic DIP (refer to dimensional outlines) Window* Quartz glass* 2 AR-coated sapphire* 3 *: Temporary window type (ex. S73-96N) is available upon request. (Temporary window is fixed by tape to protect the CCD chip and wire bonding.) *2: Resing sealing *3: Hermetic sealing Absolute maximum ratings (Ta=25 C) Parameter Symbol Min. Typ. Max. Unit Operating temperature* 4 Topr C Storage temperature Tstg C Output transistor drain voltage VOD V Reset drain voltage VRD V Vertical input source voltage VISV V Horizontal input source voltage VISH V Vertical input gate voltage VIGV, VIG2V V Horizontal input gate voltage VIGH, VIG2H V Summing gate voltage VSG V Output gate voltage VOG V Reset gate voltage VRG V Transfer gate voltage VTG V Vertical shift register clock voltage VPV, VP2V V Horizontal shift register clock voltage VPH, VP2H V Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings. *4: Package temperature (S73 series), chip temperature (S73 series) Operating conditions (MPP mode, Ta=25 C) Parameter Symbol Min. Typ. Max. Unit Output transistor drain voltage VOD V Reset drain voltage VRD V Output gate voltage VOG 3 5 V Substrate voltage VSS - - V vertical input source VISV - VRD - V Test point horizontal input source VISH - VRD - V vertical input gate VIGV, VIG2V V horizontal input gate VIGH, VIG2H V Vertical shift register High VPVH, VP2VH clock voltage Low VPVL, VP2VL V Horizontal shift register High VPHH, VP2HH clock voltage Low VPHL, VP2HL V Summing gate voltage High VSGH Low VSGL V Reset gate voltage High VRGH Low VRGL V Transfer gate voltage High VTGH Low VTGL V External load resistance RL k 2

3 Electrical characteristics (Ta=25 C) Parameter Symbol Min. Typ. Max. Unit Signal output frequency fc -.25 MHz S73* Vertical shift register S73*-97/-6 CPV, CP2V capacitance S73* pf Horizontal shift register S73*-96/-97 CPH, CP2H - capacitance S73*-6/ pf Summing gate capacitance CSG pf Reset gate capacitance CRG pf Transfer gate capacitance S73*-96/ CTG - S73*-6/ pf Charge transfer efficiency* 5 CTE DC output level* 6 Vout V Output impedance* 6 Zo k Power consumption* 6 * 7 P mw *5: Charge transfer efficiency per pixel, measured at half of the full well capacity *6: The values depend on the load resistance. (Typical, VOD=2 V, Load resistance=22 k ) *7: Power consumption of the on-chip amplifier plus load resistance Electrical and optical characteristics (Ta=25 C, unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Saturation output voltage Vsat - Fw Sv - V Full well capacity Vertical Fw Horizontal* ke - CCD node sensitivity Sv μv/e - Dark current* 9 25 C - DS (MPP mode) C - e - /pixel/s Readout noise* Nr e - rms Dynamic range* Line binning DR Area scanning Photoresponse nonuniformity* 2 PRNU - ±3 ± % Spectral response range - 2 to - nm Point defect* 3 White spots Black spots Blemish - Cluster defect* Column defect* *8: The linearity is ±.5%. *9: Dark current nearly doubles for every 5 to 7 C increase in temperature. *: Measured with a HAMAMATSU C488 digital CCD camera with a CDS circuit (sensor temperature: -4 C, operating frequency: 5 khz) *: Dynamic range = Full well capacity / Readout noise *2: Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 56 nm) Photoresponse nonuniformity = Fixed pattern noise (peak to peak) Signal [%] *3: White spots Pixels whose dark current is higher than ke - after one-second integration at C. Black spots Pixels whose sensitivity is lower than one-half of the average pixel output. (measured with uniform light producing one-half of the saturation charge) *4: 2 to 9 contiguous defective pixels *5: or more contiguous defective pixels 3

4 Spectral response (without window)* 6 9 (Typ. Ta=25 C) Back-thinned CCD 8 Quantum efficiency (%) Front-illuminated CCD (UV coated) Front-illuminated CCD Wavelength (nm) KMPDB58EB *6: Spectral response with quartz glass or AR-coated sapphire is decreased according to the spectral transmittance characteristic of window material. Spectral transmittance characteristics Dark current vs. temperature (Typ. Ta=25 C) (Typ.) 9 Transmittance (%) AR coated sapphire Quartz window Dark current (e - /pixel/s) Wavelength (nm) KMPDBEA Temperature ( C) KMPDB256EA 4

5 Device structure (conceptual drawing of top view) Thinning Effective pixels Effective pixels bevel V Thinning H 4-bevel signal out 2 n 2 Horizontal shift register 2 V=58, 22 H=52, blank pixels 2 n signal out 4 blank pixels Horizontal shift register 6-bevel 6-bevel Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. KMPDC6ED 5

6 Timing chart Line binning Integration period (shutter must be open) PV Tpwv Vertical binning period (shutter must be closed) Tovr Readout period (shutter must be closed) (bevel): S73*-96/ (bevel): S73*-97/-7 P2V, TG PH Tpwh, Tpws : S73*-96/-97 44: S73*-6/-7 P2H, SG RG Tpwr OS D D D2..D, S..S52, D.. D9 D2..D, S..S24, D..D9 D2 : S73*-96/-97 D2 : S73*-6/-7 KMPDC7ED Parameter Symbol Min. Typ. Max. Unit S73* PV, P2V, TG* 7 Pulse width S73*-97/-6 Tpwv μs S73* Rise and fall time Tprv, Tpfv - - ns PH, P2H* 7 Rise and fall time Tprh, Tpfh - - ns Pulse width Tpwh ns Duty ratio % Pulse width Tpws ns SG Rise and fall time Tprs, Tpfs - - ns Duty ratio % RG Pulse width Tpwr - - ns Rise and fall time Tprr, Tpfr ns TG PH Overlap time Tovr μs *7: Symmetrical clock pulses should be overlapped at 5% of maximum pulse amplitude. 6

7 Area scanning: large full well mode Integration period (shutter must be open) PV P2V, TG PH P2H, SG RG OS Tpwv Readout period (shutter must be closed) (bevel): S73*-96/ (bevel): S73*-97/-7 P2V, TG PH Tovr Tpwh, Tpws Enlarged view P2H, SG RG OS Tpwr D D2 D3 D4 S..S52 D8 D9 D2: S73*-96/-97 D5..D, S..S24, D..D7 : S73*-6/-7 KMPDC27EC Parameter Symbol Min. Typ. Max. Unit S73* PV, P2V, TG* 8 Pulse width S73*-97/-6 Tpwv μs S73* Rise and fall time Tprv, Tpfv - - ns PH, P2H* 8 Rise and fall time Tprh, Tpfh - - ns Pulse width Tpwh ns Duty ratio % Pulse width Tpws ns SG Rise and fall time Tprs, Tpfs - - ns Duty ratio % RG Pulse width Tpwr - - ns Rise and fall time Tprr, Tpfr ns TG PH Overlap time Tovr μs *8: Symmetrical clock pulses should be overlapped at 5% of maximum pulse amplitude. 7

8 Dimensional outline (unit: mm) S73-96/-97 S73-6/-7 Window 6.3* Window 28.6* 24 Photosensitive area Photosensitive area * A 22.4 ± ±.3 8.2* A 22.4 ± ± ± ± ± ±.44 st pin indication pad Photosensitive surface st pin indication pad Photosensitive surface 3. S73-96: A=.392 S73-97: A= ± ± ± ±.49 (24 ).5 ±.5 3. S73-6: A=.392 S73-7: A= ± ± ± ±.49 (24 ).5 ±.5 * Size of window that guarantees the transmittance in the Spectral transmittance characteristics graph KMPDA46EF * Size of window that guarantees the transmittance in the Spectral transmittance characteristics graph KMPDA47EG S73-96S/-97S Window 6.3* Photosensitive area * A ± ± ± ± ±.3 2 st pin indication pad Photosensitive surface TE-cooler 3. S73-96S: A=.392 S73-97S: A= ± ± ± ±.68 (24 ).5 ±.5 * Size of window that guarantees the transmittance in the Spectral transmittance characteristics graph KMPDA48EH 8

9 S73-6S/-7S Window 28.6* Photosensitive area * A ± ± ± ± ±.3 st pin indication pad Photosensitive surface TE-cooler 3. S73-6S: A=.392 S73-7S: A= ± ± ± ±.68 (24 ).5 ±.5 * Size of window that guarantees the transmittance in the Spectral transmittance characteristics graph KMPDA49EI Pin connections Pin S73 series S73 series Remark no. Symbol Function Symbol Function (standard operation) RD Reset drain RD Reset drain +2 V 2 OS Output transistor source OS Output transistor source RL=22 k 3 OD Output transistor drain OD Output transistor drain +2 V 4 OG Output gate OG Output gate +3 V 5 SG Summing gate SG Summing gate Same pulse as P2H P2H CCD horizontal register clock-2 P2H CCD horizontal register clock-2 9 PH CCD horizontal register clock- PH CCD horizontal register clock- IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2) -8 V IGH Test point (horizontal input gate-) IGH Test point (horizontal input gate-) -8 V 2 ISH Test point (horizontal input source) ISH Test point (horizontal input source) Connect to RD 3 TG* 9 Transfer gate TG* 9 Transfer gate Same pulse as P2V 4 P2V CCD vertical register clock-2 P2V CCD vertical register clock-2 5 PV CCD vertical register clock- PV CCD vertical register clock- 6 - Th Thermistor 7 - Th2 Thermistor 8 - P- TE-cooler- 9 - P+ TE-cooler+ 2 SS Substrate (GND) SS Substrate (GND) GND 2 ISV Test point (vertical input source) ISV Test point (vertical input source) Connect to RD 22 IG2V Test point (vertical input gate-2) IG2V Test point (vertical input gate-2) -8 V 23 IGV Test point (vertical input gate-) IGV Test point (vertical input gate-) -8 V 24 RG Reset gate RG Reset gate *9: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as P2V. 9

10 Specifications of built-in TE-cooler (Typ. vacuum condition) Parameter Symbol Condition S73-96S/-97S S73-6S/-7S Unit Internal resistance Rint Ta=25 C Maximum current* 2 Imax Tc* 2 =Th* 22 =25 C.5 3. A Maximum voltage Vmax Tc* 2 =Th* 22 =25 C V Maximum heat absorption* 23 Qmax W Maximum temperature of heat radiating side C *2: If the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 6% of this maximum current. *2: Temperature of the cooling side of thermoelectric cooler *22: Temperature of the heat radiating side of thermoelectric cooler *23: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit. S73-96S/-97S S73-6S/-7S 7 6 (Typ. Ta=25 C) 3 Voltage vs. current CCD temperature vs. current (Typ. Ta=25 C) 3 Voltage vs. current CCD temperature vs. current 2 Voltage (V) CCD temperature ( C) Voltage (V) CCD temperature ( C) Current (A) Current (A) KMPDB78EA KMPDB79EA Specifications of built-in temperature sensor A thermistor chip is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and absolute temperature is expressed by the following equation. RT = RT2 exp BT/T2 (/T - /T2) RT: Resistance at absolute temperature T [K] RT2: Resistance at absolute temperature T2 [K] BT/T2: B constant [K] MΩ (Typ. Ta=25 C) The characteristics of the thermistor used are as follows. R298= k B298/323=345 K Resistance kω kω Temperature (K) KMPDBEB

11 Precautions (electrostatic countermeasures) Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. Element cooling/heating temperature incline rate When cooling the CCD by an externally attached cooler, set the cooler operation so that the temperature gradient (rate of temperature change) for cooling or allowing the CCD to warm back is less than 5 K/minute. Related information Precautions Disclaimer Image sensors/precautions Technical information FFT-CCD area image sensor/technical information Features C74: for S73 series C74: for S73 series Area scanning or full line-binnng operation Readout frequency: 25 khz Readout noise: 2 e- rms T=5 C ( T changes by cooling method.) Multichannel detector heads C74, C74 Input Symbol Value Supply voltage VD VA+ VA- VA2 VD2 Vp VF +5 Vdc, 2 ma +5 Vdc, + ma -5 Vdc, - ma +24 Vdc, 3 ma +5 Vdc, 3 ma (C74) +5 Vdc, 2.5 A (C74) +2 Vdc, ma (C74) Master start ms HCMOS logic compatible Master clock mc HCMOS logic compatible, MHz

12 Multichannel detector head controller C7557- Features For control of multichannel detector head and data acquisition Easy control and data acquisition using supplied software via USB interface Connection example Shutter* timing pulse AC cable ( to 24 V included with C7557-) Trig. Dedicated cable (included with C7557-) POWER SIGNAL I/O TE CONTROL I/O USB cable (included with C7557-) Image sensor + Multichannel detector head C7557- PC (USB 2./3.) [Windows 7 (32-bit, 64-bit)/ Windows 8 (64-bit)/ Windows 8. (64-bit)] * Shutter, etc. are not available. KACCC42ED Information described in this material is current as of March, 25. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or a suffix "(Z)" which means developmental specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. HAMAMATSU PHOTONICS K.K., Solid State Division 26- Ichino-cho, Higashi-ku, Hamamatsu City, Japan, Telephone: (8) , Fax: (8) U.S.A.: Hamamatsu Corporation: 36 Foothill Road, Bridgewater, N.J. 887, U.S.A., Telephone: () , Fax: () Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr., D-822 Herrsching am Ammersee, Germany, Telephone: (49) , Fax: (49) France: Hamamatsu Photonics France S.A.R.L.: 9, Rue du Saule Trapu, Parc du Moulin de Massy, 9882 Massy Cedex, France, Telephone: 33-() , Fax: 33-() United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, Tewin Road, Welwyn Garden City, Hertfordshire AL7 BW, United Kingdom, Telephone: (44) , Fax: (44) North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan Kista, Sweden, Telephone: (46) , Fax: (46) Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, int. 6, 22 Arese (Milano), Italy, Telephone: (39) , Fax: (39) China: Hamamatsu Photonics (China) Co., Ltd.: B2, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 2, China, Telephone: (86) , Fax: (86) Cat. No. KMPD23E8 Mar. 25 DN 2