FINAL EXAMINATION SOLUTIONS

Transcription

1 FINAL EXAMINATION SOLUTIONS Electronics I for EE ourse Number EE 09-3 N 0460 Instructor: James K Beard, PhD beard@rowanedu Page of 3

2 Table of ontents Problem (0%)3 Solution 3 Problem (0%)5 Solution 6 Problem 3 (0%)7 Solution 8 Problem 4 (0%)9 Solution 9 Problem 5 (0%) Solution List of Figures Figure ircuit to Solve for Problem 3 Figure V-i urves from a Model of the IFZ4N MOSFET 5 Figure 3 Microcontroller Operated Electromagnet Driver from 5 Volts Using the IFZ4N MOSFET 5 Figure 4 Epanded v-i urves from a Model of the IFZ4N MOSFET 6 Figure 5 Op-amp circuit for Problem 3 7 Figure 6 MOSFET Signal Model 9 Figure 7 BJT Inverting Amplifier Biasing ircuit Figure 8 BJT Inverting Amplifier Biasing Model Page of 3

3 Problem (0%) efer to the circuit of Figure Use the steady-state sine wave solutions and the concepts of inductive and capacitive impedance, and apply circuit theory to solve the problems much as you would with resistive networks Show all work and provide equations for the following: Show the comple form vzin ( t ) for the input voltage such that vin () t is the real part of vzin () t and vzin () t has constant comple amplitude with time Derive and show the voltage across the resistor in either real or comple format G ω that, when multiplied by 3 Provide the comple voltage transfer function ( ) () vz t, yields the comple form of the output voltage across the resistor IN L v V IN P () t = cos( ω t φ ) Figure ircuit to Solve for Problem Solution The base equations are vzin () t = VP ep( j ( ω t φ )) () ZL = j ω L Z = j ω The voltage across is found by the voltage divider equation The impedance of the resistance in parallel with the capacitance is j ω () = = j ω = Z Z so we have the voltage across as Page 3 of 3

4 (3) Z vz t vzin t Z Z () = () The transfer function G ( ω ) is found as (4) G ( ω) L j ω = vz j ω L j ω = vzin L j ω ω L ( t ) () t L IN () t () t vzout = = vzin j ω ω L Page 4 of 3

5 Problem (0%) Figure below is a simple model of the IFZ4N MOSFET from I that offers a reasonable approimation of the v-i curves in the I data sheet for an ambient temperature of 5 (ontinued on net page) 6 Drain urrent, Amperes Bound 30 V 35 V 40 V 45 V 50 V 55 V 60 V 65 V Ohm Ohms 4 Ohms Drain Voltage, Volts Figure V-i urves from a Model of the IFZ4N MOSFET Electromagnet 5 Volts From ail Or H-Bridge Output From PI 0 Ω IFZ4N N-hannel MOSFET (same one that the H-bridge uses) Figure 3 Microcontroller Operated Electromagnet Driver from 5 Volts Using the IFZ4N MOSFET Page 5 of 3

6 Drain urrent, Amperes Bound 30 V 35 V 40 V 45 V 50 V 55 V 60 V 65 V Ohm Ohms 4 Ohms Drain Voltage, Volts Figure 4 Epanded v-i urves from a Model of the IFZ4N MOSFET The transition voltage V T for this model is 75 Volts Figure 4 above is another set of v-i curves from the model of the IFZ4N MOSFET that zooms in on the lower drain currents onsider the electromagnet a simple resistive load Assume that the PI microcontroller provides 50 Volts of drive for the MOSFET gate Draw the load lines for electromagnet resistances of Ohm, Ohms, and 4 Ohms Give the steady-state D current through the electromagnet for each resistance ompare that current with the current that would be produced by 5 Volts across the electromagnet Solution The load lines are drawn on the figures The results from the intersection of the load lines with the MOSFET v-i curves for 5 Volts gate voltage are as shown below in Table Table omparison of Load Line and Direct onnection urrents esistance Load Line urrent Straight onnection urrent Ohm 44 Amperes 50 Amperes Ohms 8 Amperes 5 Amperes 4 Ohms 0 Amperes 5 Amperes Page 6 of 3

7 Problem 3 (0%) See Figure 5 below for the circuit to analyze for this problem Use the perfect op-amp approimations to analyze the circuit Solve for e OUT in terms of e and e Simplify and interpret the result for the special case 3 = 4 What is the input impedance as seen at e and e? What is the Thévenin equivalent for the output at e OUT? HINT: Use superposition to analyze each op-amp Find e in terms of e, and find e OUT in terms of e and e separately, then add the results and substitute your solution for e in terms of e e - e OUT e - e 3 4 Figure 5 Op-amp circuit for Problem 3 Page 7 of 3

8 Solution Ecept for some capacitive coupling, this is the same op-amp configuration that is used in the Term Project In Laboratory 3, you were asked to build this circuit and test it In the laboratory report instructions, you were asked to analyze this circuit for your lab report See this link for the lab protocol: We are instructed to use the perfect op-amp approimation, which is infinite input impedance, voltage source output, and infinite gain We will use the hint and fine e first Note that the bottom op-amp in Figure 5 is a non-inverting amplifier Because this is a perfect op-amp and has a voltage source output, any current flowing through will have no effect on e, so we see that we can analyze this non-inverting amplifier while ignoring the rest of the circuit We can analyze this circuit in detail or simply use what we have learned studying non-inverting amplifiers and went over in the Study Session on April 30 and write e as 3 (3) e = e 4 The hint net tells us to look at e OUT as a function of e and e separately using the principle of superposition - taking one of the inputs as zero volts and finding the output due to the other, then using the principle of linearity by taking the output as the sum of the outputs due to all of the inputs separately From the input e and taking e as zero, we see that we have a simple inverting amplifier, (3) eout ( e ) = e onversely, taking e as zero, we see that we again have a simple non-inverting amplifier, and (33) eout ( e ) = e As the hint suggests, we add the two results from (3) and (33), (34) eout = e e Since we have e as a function of e from (3), which, as suggested by the hint, we substitute into (34) to obtain 3 (35) eout = e e e 4 Note that when 3 = 4 this is a differential amplifier with theoretically zero e e e e common-mode gain; the output is a function of ( ) but not ( ) Page 8 of 3

9 Problem 4 (0%) efer to the MOSFET signal model shown in Figure 6 For an input signal e IN applied at the gate ( v Gate = v IN ), Find the Thévenin equivalent circuit between the output marked v Source and ground Find the Thévenin equivalent circuit between the output marked v Drain and ground The solutions will be algebraic equations involving the transconductance g and the resistances Bias, S, and D HINT: Write Kirchhoff's current law for the current node at the source terminal and use the node voltage notation This will solve the circuit Then, find the short circuit currents; this is simpler than the virtual source technique v Drain i D v Gate Bias v G v S g ( v G v S ) v Source i S D S Figure 6 MOSFET Signal Model Solution Since the gate current is zero, the current out of the MOSFET source is the same as the current into the drain, and Kirchhoff's current law simply re-states this Writing Kirchhoff's current law for the node at the MOSFET source is, in terms of the node voltage v Source, vs (4) is = = g ( vg vs) = id S from which we can find the source voltage v S Page 9 of 3

10 g S (4) vs = vg g S which is the open circuit voltage at the MOSFET source terminal The source current is vs g (43) i = S vg = S g S We can find the short circuit current as i S for zero source resistance, ie take S as zero in (43): (44) iss, = g vg The Thévenin equivalent resistance is the open circuit voltage divided by the short circuit current, or vs S (45) S = TH i = g SS, The current into the drain terminal of the MOSFET is the same as the current out of the source terminal as given by (43) and we find the voltage at the drain terminal from Ohm's law as g D (46) vd = id D = is D = vg g S which is the open circuit voltage at the drain terminal The short circuit current is simply the negative of the source current as given by (43) because the drain current is not a function of D, and the Thévenin equivalent resistance at the drain terminal is vd (47) DTh = = D id This can be seen by the principle of superposition and the test source method because, when the gate voltage v G is taken as zero the current in the controlled source is zero and the impedance seen at the drain terminal is simply E S Page 0 of 3

11 Problem 5 (0%) This is a BJT biasing problem efer to Figure 7 for the circuit and Figure 8 for the biasing model The problem is to design a BJT amplifier that meets these requirements: Given an NPN transistor with a minimum current gain β MIN of 50, and a baseemitter voltage drop V f of 07 Volts, A collector supply voltage V of 5 Volts, We require an output impedance of 0 kohms, We require a gain of 5, We require that the collector voltage be approimately V or 75 Volts when there is no signal present, and We require here that you define the Thévenin equivalent circuit for the bias circuit shown inside the dotted lines in Figure 8, not the voltage divider resistors Give the values of the resistances in Figure 8, the voltages at the transistor terminals, and the transistor base and collector currents V = 5 V Input B IN OUT Output B E Figure 7 BJT Inverting Amplifier Biasing ircuit Page of 3

12 B B V Bias i B V i E BE E β i E B V i Figure 8 BJT Inverting Amplifier Biasing Model Note that the Thévenin equivalent circuit for the bias components B, B and V is inside the dotted bo in the bias model shown in Figure 8 Find the maimum allowable value of B that will allow robust operation of the circuit for current gain at or above the minimum β of 50 as given in the problem statement MIN Solution Since the A or incremental small signal gain for the BJT is, for the purposes of this problem, the same as the D current gain, the signal model can bet taken from the bias model, Figure 8 by dropping the D voltages The output impedance at the collector terminal of the BJT can be seen from this to be simply ; this can be seen by taking the base voltage as zero and using the test source method Thus, the maimum collector resistance that will provide an inverting amplifier with the required impedance of 0,000 Ohms is 0,000 Ohms, (5) = 0, 000 Ω We know from our signal model and the fact that we have a moderate to high current gain β that the gain G is approimately E, so the proper value of the emitter resistor E is 0000 Ω (5) E = = = 400 Ω G 5 We require that the collector voltage be approimately 75 Volts, so the collector resistor must have a voltage drop of ( 5 75) Volts or again 75 Volts, so the collector current is to be set at Page of 3

13 (53) i 75V = = 075 ma 0000 Ω The emitter voltage is about /G times this or (54) v = i i = 03Volts E E E E Since we are given a base to emitter voltage drop V f in the problem statement of 07 Volts, we now have the base voltage v B as (55) v = v V = 03Volts 07 Volts = Volt B E V We require that the Thévenin equivalent resistance of the bias source be small enough for robust operation as an inverting amplifier This means that we must provide a voltage V Bias that is approimately the base voltage v B and a resistance that is much smaller than the Thévenin equivalent resistance seen at the base terminal, (56) BTh = ( β ) E which we can obtain from the signal model obtained from Figure 8 by dropping the D voltages and using the test source method to the right of the dotted line We have a minimum current gain β MIN of 50 from the problem statement, so we have VBias = Volt (57) B 60,000 Ω I will accept other valid methods of establishing the bias voltage and Thévenin equivalent resistance Page 3 of 3