12V --> 5V 5V --> 3.3V 3.3V --> 1.8V VIO VIO_SD. SDIO Pin Header. GPIOs. mpcie Bus USB2.0 JTAG. PCM Pin Header FT232R. 32.

Transcription

1 V --> V V -->.V.V -->.V VO VO_S POs US.0 JT PO0 PO PO PO PO PO US_N US_P TK TMS T TO (PO-) (PO-) (PO-) (PO-) S_LK S_M S_T[:0] PE_RLK_P PE_RLK_N US_N US_P PE_TX_P PE_TX_N PE_RX_P PE_RX_N PE_WKEn PE_LKREQn PE_W_SLEn(PO-) PE_PERSTn(PO-) SO Pin Header mpe us FTR URT_SOUT(PO-) URT_SN (PO-) URT_TSn (PO-0) URT_RTSn (PO-) PM_N (PO-) PM_OUT (PO-) PM_LK (PO-) PM_SYN (PO-) PM Pin Header.kHz OS Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT VK-0-SPT_lockdiagram Friday, May, 0 ate : Revision : Sheet : of.0

2 TE REVSON NUMER NTLS NTL RELESE 0/0/ 0 Kai Wei nitial raft 0/0/ 0 Kai Wei 0/0/ 0 Kai Wei lean up for EVT design review. hange J,J,J from female to male pin header lean up for EVT design review.dd (0.uF/00) and 0 (0.0uF/00) for VO on FT chip..hange J,J,J,J,J,J,J0,R,R,R,, to NP..hange the Orcad symbol of SS0NT to the latest one which updated on /..hange U to RT0 0/0/ 0 Kai Wei lean up for EVT design review 0/0/ 0 Kai Wei 0/0/.0 Kai Wei dd, Update Silkscreen :.hange model name to VK-0-SPT.orrect the HOST ONF setting P design specification. Substrate: FR ROHS compliant, T 0 degree.. Solder mask color=lue, Silkscreen color=whte. Surface finish to be mmersion Nickel/old (EN) with - u". Start with / oz. copper on all layers. ZZ-P P Substrate ZZ-LEL Laird Module M :XXXXXXX F :XXXXXXX E :XXXXXXX :XXXXXXX LEL Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT VK-0-SPT_Title and History Friday, May, 0 Sheet : of.0 ate : Revision :

3 Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT VK-0-SPT_Power Tree Friday, May, 0 Sheet : of.0 ate : Revision :

4 N JK P PWR_ MF,00R, MF PWR_ 0V, F FUSE,hold. + -0uF,V 0uF,V R 0K,% R NP/.K,% U VN EN N.MHz, OOT SW F OMP NP/0.0uF,V 0.0uF,V R.K,% 00pF,0V 0V, PL.uH,. R K R 0K,% + -0uF,V 0uF,V 0.uF,V JK_V V --> V US_V US Q UL-PH,-.,-0V JK_V SW Slide switch,pt, P/0 RE_V 0 0uF,V RE_V R 0K,% PVN VN U P SW MOE EN P F MHz, PL uh,. pf,0v R K,% R K,% RE_V 0uF,0V RE_V 0.uF,V O_V V F 0R, F 0R, RE_VO SW Slide switch,pt, P/0 F 0R, F 0R, RE_VO_S S SW Slide switch,pt, P/0 0.uF,V R K US_PWREN 0.uF,V.uF,0V U VN Vout=0. *[+(R/R)] EN VOUT LO,00m F NP/0.0uF,V R R R.K,% R0 0K,% pf,0v.uf,0v V -->.V.V -->.V RE_VO VO RE_V J O_V SW V Slide switch,pt, P/0 NP/PN HEER,.mm XP RE_VO_S VO_S J S NP/PN HEER,.mm XP S RE_V V J NP/PN HEER,.mm XP Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT VK-0-SPT_Power Friday, May, 0 Sheet : of.0 ate : Revision :

5 KV 000pF,KV US0 KV 000pF,KV US0 US_V US MicroUS-,SM/0d V - + F 0R, 0uF,0V US_V US_PWREN - + 0V, R 0R ualtvs,v,00w US- US+ 0.0uF,V TP TP TP TP R 0R TP TP,mm R0 0K,% 0.uF,V 0 0.uF,V US0 0 US US US US USM USP VOUT THP N_ N_ N_ N_ N_ N_ VO V U US-URT,QFN TS# RTS# TX 0 RX R# SR# # TR# 0 0 RESET# OS OSO TEST R 0K,% FTR SS0NT TS# (input) <----- URT-RTSn (output) RTS# (output) -----> URT_TSn (input) TX (output) -----> URT_RX (input) RX (input) <----- URT_TX (output) 0 0.0uF,V VO J 0.uF,V US_V URT_RTSn PN HEER,.mm XP J URT_TSn PN HEER,.mm XP J URT_RX PN HEER,.mm XP J URT_TX PN HEER,.mm XP R.K R 0K,% TTLR_V LK TS# ROWN V RE TX ORNE RX YELLOW RTS# REEN J PN HEER,.mm XP J PN HEER,.mm XP US0 FTR PE_TX_P PE_TX_N US_N US_P LE_WLN LE_WPN PE_WKEn PE_LKREQn PE_RLK_P PE_RLK_N PE_W_SLEn PE_PERSTn PE_RX_P PE_RX_N PE FP ON V ON +.V +.V WKE#(MP) OEX(MN) OE(ERP) LKREQ#(ERN) UM_PWR UM_T 0 REFLK- REFLK+ UM_LK UM_RST UM_VPP W_SLE# PERST# 0 +.VUX UM_ +.V UM_ PERn0 (+) PERp0 (-) SM_LK 0 SM_T PETn0 (-) PETp0 (+) US_- US_+ 0 LE_WWN# LE_WLN# LE_WPN# +.V(Rsv) +.V0(Rsv) Rsv() Rsv(Vendor) Rsv(Vendor) Rsv(/SS) P Rsv(P) 0 +.V P +.V LH/EH-0RL-Txx ON MPR0 PO V PE_W_SLEn ON MPR0 J0 PE_W_SLEn PO V_PE F 0R, NP/PN HEER,.mm XP S ON MPR0 R NP/0R ON MPR0 V 0.uF,V 0uF,0V R0 NP/00K,% R0 0R ON +.V_ +.V_ +.V_ +.VUX_ +.VUX_ +.VUX_ +.VUX_ +.VUX_ RSV_ RSV_ RSV_ RSV _ Half-Mini ard PERST* WKE* R 0R SM_LK 0 SM_T R 0R OEX OEX 0 UM_PWR UM_T REFLKP UM_LK REFLKN UM_RESET UM_VPP PE_LKREQn RSV_UM_ LKREQ* 0 RSV_UM_ W_SLE* PET0P PET0N PER0P PER0N LE_WPN* LE_WLN* LE_WWN* US_P US_N MT MT PE_PERSTn PE_WKEn R 0R R 0R PE_TX_N PE_TX_P R 0R R 0R R 0R R 0R LE_WPN LE_WLN R R PE_RX_N PE_RX_P PE_PERSTn PE_WKEn R R NP/pF,0V PE_LKREQn PE_TX_N PE_TX_P US_P US_N R NP/0R ON_US_P ON_US_N R NP/0R PE_RX_N PE_RX_P LE_WPN LE_WLN PE_RLK_N PE_RLK_P US_P US_N ON_US_P ON_US_N PE_RLK_N PE_RLK_P Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT NP/pF,0V VK-0-SPT_mPe/URT Friday, May, 0 ate : Revision : Sheet : of.0

6 U SS0NT V ON_US_P ON_US_N 0.uF,V S 0uF,0V US ON_US_P ON_US_N US_V R NP/0R R NP/0R ualtvs,v,00w V_SO J S_LK NP/.mm XP NP/0pF,0V US.0 Micro- S_T S_T S_M S_T0 S_T F 0R, 0uF,0V 000pF,KV US US MicroUS-,SM/0d + - V US 000pF,KV J R0 0R R 0R R 0R 0 R 0R 0 R 0R R 0R.mm,XP PE_WKEn PE_LKREQn PE_PERSTn PE_W_SLEn Pn TP,mm TP RF_ VO V RF_ ONF_HOST ONF_HOST ONF_HOST0 PM_LK PM_OUT PM_SYN 0 PM_N PO0 PE_WKEn PE_LKREQn PE_PERSTn PE_W_SLEn LTE_SOUT LTE_SN 0 VO V KHz_LK 0 Pn LE_OUT_WLN LE_OUT_T JT_TMS NT0 (RF_)/WF+T JT_TK URT_RTSn URT_TSn URT_RX URT_TX 0 SO_LK NT (RF_)/WF ONLY SO_M SO_T S_T ONF_HOST SO_T SO_T0 ONF_HOST VO_S ONF_HOST0 PMU_EN 0 PM_LK PM_OUT V PM_SYN V PM_N PO0 US_P US_N PE_WKEn PE_LKREQn PE_RX_P/US0_RX_P PE_PERSTn PE_RX_N/US0_RX_N PE_W_SLEn LTE_SOUT/JT_TO PE_TX_P/US0_TX_N 0 LTE_SN/JT_T PE_TX_N/US0_TX_P VO V_OUT PE_RLK_P PE_RLK_N KHz 0 0 LE_OUT_WLN LE_OUT_T JT_TMS JT_TK URT_RTSn URT_TSn URT_RX URT_TX S_LK S_M S_T S_T S_T S_T0 VO_S PMU_EN VO_S V TP TP,mm lose to SS0 US_P US_N PE_RX_P PE_RX_N PE_RX_P PE_RX_N 0.uF,V PE_TX_N 0.uF,V PE_TX_P PE_RLK_P PE_RLK_N URT_RTSn URT_TSn URT_RX URT_TX 0uF,0V US_P US_N PE_RLK_P PE_RLK_N 0 0uF,0V PE_TX_N PE_TX_P V R 00K ONF_HOST0 R00K R 00K ONF_HOST R00K R 00K ONF_HOST R00K SW Slide switch,pt, P/0 SW Slide switch,pt, P/0 SW Slide switch,pt, P/0 ootstrap onfig. (REF:V) LTE_SOUT LTE_SN JT_TMS JT_TK J PO PO PO PO PN HEER,.mm XP JT nterface SO nterface PM_N PM_OUT PM_LK PM_SYN J PO PO PO PO PN HEER,.mm XP PM nterface PO0 PO PO PO PO PO J PN HEER,.mm XP POs RF_ 0.pF,0V NP/pF,0V.pF,0V ON U.FL,0d/0.mm S S NP/.pF,0V NP/pF,0V ON oardedgefemale,p/.mm V J PN HEER,.mm XP R V.K,% R J0 Pn 0K,% PN HEER,.mm XP SW TT SW,P/0d.pF,0V Pn PE_PERSTn PO SW R NP/0R TT SW,P/0d R 0R V R.K,% PMU_EN.pF,0V J PN HEER,.mm XP R0 0K,% PMU_EN RF_.pF,0V NP/pF,0V S.pF,0V ON U.FL,0d/0.mm S NP/.pF,0V NP/pF,0V ON oardedgefemale,p/.mm RF_ON KHz_LK U.KHz,ppm OUT.kHz RE_VO V E.uF,0V 0.uF,V R 0K,% J PN HEER,.mm XP V LE_V J LE_V NP/PN HEER,.mm XP R 0R LE lue,00 VO J NP/PN HEER,.mm XP S S LE_WLN LE_T LE_VO LE lue,00 R 0R R 0R R LE_OUT_WLN NP/0R PO LE_WLN LE lue,00 R 0R R R 0R LE_OUT_T NP/0R PO LE_WPN ON0 Screw Hole,M For Test Fixture Laird Technologies SU F, No., ong Sec., uangming th Rd, Zhubei ity, Hsinchu ounty 0, Taiwan (R.O.) Project Name : Schematic Name : rawing y : VK-0-SPT ON Screw Hole,M Friday, May, 0 ON Screw Hole,M VK-0-SPT_SP Sheet : of.0 ate : Revision : ON Screw Hole,M