1 Bi-directional Ultra-low Capacitance ESD / Transient Protection Diode

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1 Bi-directional Ultra-low Capacitance ESD / Transient Protection Diode 1 Bi-directional Ultra-low Capacitance ESD / Transient Protection Diode 1.1 Features ESD / transient protection of RF signal lines according to: IEC (ESD): ±2 kv (contact) IEC (EFT): 4 A (5/5 ns) IEC (surge): 3 A (8/2 μs) Maximum working voltage: V RWM ±5.3 V Extremely low capacitance: C L =.2 pf (typical) Low clamping voltage: V CL = 29 V at I PP = 16 A (typical) Very low reverse current I R < 1 na typ. Very small form factor down to.62 x.32 x.31 mm 3 Pb-free (RoHS compliant) and halogen free package 1.2 Application Examples ESD protection of sensitive RF signal lines, Bluetooth Class 2, Automated Meter Reading RF antenna protection, frontend module, GPS, mobile TV, FM radio, UWB 2 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram Figure 2-1 Pin Configuration and Schematic Diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Table 2-1 Ordering Information Type Package Configuration Marking code ESDP2RF-2LS PG-TSSLP line, bi-directional T ESDP2RF-2LRH PG-TSLP line, bi-directional T Final Data Sheet 8 Revision 1.,

2 3 Table 3-1 Maximum Ratings at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 1) V ESD 2 kv Peak pulse current (t p = 8/2 μs) 2) I PP 3 A Operating temperature range T OP C Storage temperature T stg C 1) V ESD according to IEC ) I PP according to IEC Electrical at T A =25 C, unless otherwise specified R DYN V BR V RWM Dynamic resistance Breakdown voltage Reverse working voltage maximum I V CL Clamping voltage I PP I PP Peak pulse current R DYN V CL I BR V BR V RWM I RWM I RWM I BR V RWM V BR V CL V R DYN I PP Figure 3-1 Definitions of electrical characteristics Diode_Characteristic_Curve_Bi-directional.vsd Table 3-2 DC at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM V Breakdown voltage V BR 7 V I R = 1 ma, from pin 1 to pin 2, from pin 2 to pin 1 Reverse current I R <1 5 na V R = 5.3 V Final Data Sheet 9 Revision 1.,

3 Table 3-3 RF at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Diode capacitance C L.23.4 pf V R = V, f = 1 MHz.2.4 pf V R = V, f = 1 GHz Table 3-4 ESD at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Clamping voltage 1) V CL 29 V I pp = 16 A 38 V I pp = 3 A Dynamic resistance 1) R DYN 1 Ω Series inductance L S.2 nh ESDP2RF-2LS.4 nh ESDP2RF-2LRH 1)Please refer to Application Note AN21 [4]. TLP parameter: Z = 5 Ω, t p = 1ns, t r = 3ps, averaging window: t 1 = 3 ns to t 2 = 6 ns, extraction of dynamic resistance using least squares fit of TLP charactertistics between I PP1 = 1 A and I PP2 = 4 A. Final Data Sheet 1 Revision 1.,

4 3.2 Typical at T A = 25 C, unless otherwise specified C I R [A] C C V R [V] Figure 3-2 Reverse current: I R = f(v R ), T A = parameter.4.3 C L [pf] V R [V] Figure 3-3 Line capacitance: C L = f(v R ), f = 1 MHz Final Data Sheet 11 Revision 1.,

5 V C L [pf] V V.21 Figure f [MHz] Line capacitance: C L = f(f), V R = parameter C L [pf] Figure V V.3.2 V T A [ C] Line capacitance: C L = f(t A ), V R = parameter Final Data Sheet 12 Revision 1.,

6 V CL [V] V CL-max-peak = 112 [V] V CL-3ns-peak = 24.8 [V] t p [ns] Figure 3-6 IEC V CL = f(t), 8 kv positiv pulse from pin 1 to pin V CL [V] V CL-max-peak = -116 [V] V CL-3ns-peak = -25. [V] t p [ns] Figure 3-7 IEC V CL = f(t), 8 kv negativ pulse from pin 1 to pin 2 Final Data Sheet 13 Revision 1.,

7 V CL [V] V CL-max-peak = 162 [V] 8 V CL-3ns-peak = 37.4 [V] t p [ns] Figure 3-8 IEC V CL = f(t), 15 kv positiv pulse from pin 1 to pin 2 V CL [V] V CL-max-peak = -169 [V] -8 V CL-3ns-peak = [V] t p [ns] Figure 3-9 IEC V CL = f(t), 15 kv negativ pulse from pin 1 to pin 2 Final Data Sheet 14 Revision 1.,

8 4 ESDP2RF-2xx R DYN 2 I TLP [A] R DYN =1.Ω Equivalent V IEC [kv] V TLP [V] Figure 3-1 Clamping voltage : I TLP = f(v TLP ) [4] Final Data Sheet 15 Revision 1.,

9 Application Information 4 Application Information Connector Protected signal line 1 I/O ESD sensitive device 2 The protection diode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible. Pin 2 (or pin 1) should be connected directly to a ground plane on the board. Application_ESDP2RF -2xx.vsd Figure 4-1 Single line, bi-directional ESD / Transient protection [1], [2], [3] Final Data Sheet 16 Revision 1.,

10 Ordering Information Scheme (Examples) 5 Ordering Information Scheme (Examples) ESD P1 RF - XX YY Package XX = Pin number (i.e.: 2 = 2 pins; 3 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For Radio Frequency Applications Line Capacitance CL in pf: (i.e.: P1 =.1pF) ESD 5V3 U n U - XX YY Package or Application XX = Pin number (i.e.: 2 = 2 pins; 3 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI Uni- / Bi-directional or Rail to Rail protection Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>1pF), Low (<1pF), Ultra-low (<1pF) Figure 5-1 Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V) Ordering information scheme Final Data Sheet 17 Revision 1.,

11 Package Information 6 Package Information 6.1 PG-TSLP-2-17 (mm) [5] Top view Bottom view.5 MAX..6 ±.5.65 ± ±.5 Figure 6-1 Cathode marking PG-TSLP-2-17: Package overview 1).5 ±.35 1) Dimension applies to plated terminal 1).25 ±.35 TSLP27PO V Figure 6-2 PG-TSLP-2-17: Footprint Copper Solder mask Stencil apertures TSLP-2-7-FP V Orientation marking.76 TSLP-2-7-TP V3 Figure 6-3 PG-TSLP-2-17: Packing Figure 6-4 PG-TSLP-2-17: Marking (example) Final Data Sheet 18 Revision 1.,

12 Package Information 7 Package Information 7.1 PG-TSSLP-2-1 (mm) [5] Top view Bottom view.32± ± ±.35 Cathode marking 1).26±.25 1).2 ±.25 Figure 7-1 1) Dimension applies to plated terminal PG-TSSLP-2-1: Package overview TSSLP-2-1,-2-PO V Copper Solder mask Stencil apertures Figure 7-2 PG-TSSLP-2-1: Footprint TSSLP-2-1,-2-FP V Ey Figure 7-3 Cathode marking PG-TSSLP-2-1: Packing Ex Figure 7-4 PG-TSSLP-2-1: Marking (example) Final Data Sheet 19 Revision 1.,

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