A novel voltage reference without the operational amplifier and resistors

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1 International Journal of Researh in Engineering and Siene (IJRES) ISSN (Online): , ISSN (Print): Volume 3 Issue 12 ǁ eember ǁ PP A novel voltage referene without the operational amplifier and resistors Jin Ling Zhou, WanLing eng, XiaoYu Ma, JunKai Huang (College of Information Siene and Tehnology, Jinan University, China) ABSTRACT: A novel voltage referene has been proposed and simulated using a 0.18µm CMOS proess in this paper. A near-zero temperature oeffiient voltage is ahieved in virtue of the bias voltage subiriut whih onsists of two MOSFETs operating in the saturation region. The kind of bias voltage subiriut is used to adjust the output voltage and ompensate the urvature. The output voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, whih was about mv for the MOSFETs we used. The power supply rejetion ratio (PSRR) is improved with three feedbak loops. Although the output voltage flutuates with proess variation, the iruit an monitor the proess variation in MOSFET threshold voltage. The simulation results show that the line regulation is 0.75 mv/v in a supply voltage range from 1.6 V to 3.1 V and the temperature oeffiient is around 10.8 ppm/ to 28.5 ppm/ at 9 different orners in a temperature range from -20 to 120. The PSRR is -70 db at 100Hz with a supply voltage at 1.8 V, and the layout size is 0.012mm 2. The results of simulation and post layout simulation are almost the same. Keywords: CMOS, voltage referene, PSRR, saturation region, proess variation I. Introdution The voltage referenes are essential modules in integrated iruit designs, whih are used in analog -todigital or digital-to- analog onversion, urrent soures for driving laser diodes, signal onditioning, signal measurement, power supply, battery harges, and battery supervision, et. However, different iruit topologies operated at different frequenies indue signifiant flutuations on the power supply. Therefore, a larger PSRR is required. Some iruits enhane the PSRR with operational amplifier [1-3]. However, the operational amplifier brings Offset Voltage and inreases the omplexity of the iruit. In order to avoid the Offset Voltage brought from the operational amplifier, several feedbak loops are designed in the iruit. The traditional voltage referene iruit needs resistane of several hundred mega ohms to adjust iruit for temperature ompensation [4-6]. Suh a high resistane needs large area. Therefore, in order to avoid the use of resistane whih results in a large hip area, and to eliminate the proess variations aused by the resistane manufaturing, we develop a new voltage referene without resistors. In this paper, a novel voltage referene is presented. It uses the feedbak tehnique instead of operational amplifier to enhane PSRR. The PSRR is analyzed in a small signal model and simulation results show that it has been improved greatly. The temperature ompensation is obtained using the bias voltage subiriut whih onsists of two MOSFETs operating in the saturation region and is used to adjust the output voltage and ompensate the urvature. The output voltage is equal to the threshold voltage when the MOSFET operates at 0 K. In this paper, the output voltage is about mv. The results of proess orner simulation show that the output voltage variation ΔVref well reflets the threshold voltage variation ΔV TH and temperature oeffiient (TC) of output voltage hardly depends on proess variation. Post layout simulation shows the parasiti parameters of this iruit are very small. The following setions provide the details on our iruit. Setion 2 desribes the priniple of our voltage referene soure. Setion 3 presents the simulation results. Setion 4 presents the layout and post layout simulation results and omparison. Finally, Setion 5 shows the onlusion. II. Ciruit and priniple The priniple of our voltage referene is illustrated in Fig.1. The iruit onsists of a start-up iruit, a urrent soure subiruit and a bias voltage subiriut. The bias voltage subiriut onsists of two MOSFETs (MN6, MP4). All the MOSFETs exept for MN4 operate in the saturation region. The MOS resistor MN4 operates in the strong-inversion and deep-triode region. The iruit generates two voltages with a negative temperature oeffiient (TC) and a positive TC. Then, it adds them together to produe a onstant voltage with a zero TC. The following setions desribe the operation in detail. 13 Page

2 A novel voltage referene without the operational amplifier and resistors MS5 MP1 I MP2 MP3 I MP4 mi F Vref MS4 MN1 E MN2 MP5 MN3 A MN6 MS1 MS3 C MN5 Q1 Q2 Q3 B MS2 MN4 Start-up iruit Current soure subiruit Bias voltage subiruit Fig.1The proposed voltage referene iruit 2.1 Priniple of temperature ompensation In the saturation region, the gate-soure voltage is given by [7]: V 2 I / (μ C K ) (1) GS TH OX Where K is the aspet ratio (=W/L) of the transistor, µis the arrier mobility, C OX is the gate-oxide apaitane per unit area, and V TH is the threshold voltage of MOSFET. In the urrent soure subiruit, the base-emitter voltage V BE2 in Q 2 is equal to the sum of the baseemitter voltage V BE3 inq 3 and the drain-soure voltage V SM4 inmn 4 : VBE 2 BE 3 SM 4 (2) The base-emitter voltage V BE =V T ln(i C /I S ), where V T is the thermal voltage, I S is the sale urrent whih is proportional to the base-emitter area and I C is the olletor urrent of the bipolar transistor [8]. Combining with (2), V SM4 an be written as V SM4 =V T ln(n), where N is the area ratio of emitters inq3 and Q2. MOS resistormn4 operates in the strong-inversion, deep-triode region.its resistane R M4 is given by[1]: 1 RM 4 (3) K μ C ( V ) M 4 OX GS 4 TH Therefore,the following expression is obtained as: VSM 4 I KM 4μ COX ( VGS 4 TH ) VT ln( N) (4) RM 4 The threshold voltage is expressed as V TH =V TH0 -kt, where V TH0 is the threshold voltage at 0Kand k is the TC of V TH [1]. Given I 6 =mi and using the relation of Vref=V GS4 =V GS6 from the iruit, we find that the output voltagevref of the iruit an bederived as: 2 mkm 4( VGS 4 TH 0 kt ) VT ln( N) Vref VTH 2 I 6 / ( COX K6) VTH 0 kt (5) K where V T =k B T/q, k B is the Boltzmann onstant, T is the absolute temperature, and q is the elementary harge. In regulate iruit, when TC has the smallest value,the relation ofvref=v GS4 =V GS6 =V TH0 an bedeveloped. As a result, Vrefis rewritten as: 2mK 4 ln( ) M kkb N Vref TH 0 T k (6) qk6 By (6), we find that a zero TC an be ahieved with the ondition of: 2mKM4kBln( N) k (7) qk6 Aording to (7), a zero TC voltage an be obtained by hoosinga proper W/L.Moreover, from (6), we have: Vref THO (8) 6 14 Page

3 A novel voltage referene without the operational amplifier and resistors 2.2 Priniple of enhaned PSRR As shown in Fig.1,the iruit shows a high insensibility to the supply variations. PSRR is enhaned by three feedbak loops. In this iruit, the negative feedbak is muh greater than the positive feedbak and our aim is to improve PSRR with negative feedbak. Therefore, we ignore thepositive feedbak in following analysis. There are three negative feedbak loops in this design, i.e., negative feedbak loop A-E-F-A,A-B-C-E-F-A and A-B--A. Ignoring hannel length modulation effet and body effet, ΔI an be written as: ( F ) gmp3 I (9) The expression of feedbak oeffiient a from A to F an be expressed as: F a (10) VA wherea is aused by feedbak A-E-F and A-B-C-E-F. Therefore, we get the following expression: F F E F E C B (11) A E A E C B A where: F gmn1 1 [ / /(1 gmn1ron 1) rq 12] 1 g r g E mn1 Q12 mp1 E gmn 2 1 g r A mn 2 Q12 B g r 1 g r mn 5 BG A mn 5 BG C B r r CV be 1 [ r / /(1 g r ) r ] op2 mn 2 on 2 Q12 E gmn 2[ rop 2 / /(1 gmn 2roN 2) rq 12] C Combining (4)~(8) and (3), a an be rewritten: F rop 2 rop 2gmN 2 rcv a 1 2 r g r g r A Q12 mp1 Q12 mp1 be whereδv A =ΔI r oa, and r oa is the output impedane at point A. Combining (9) and (10), we obtain: I gmp3 1 ar g oa mp3 The loop gain A loop of feedbak loop A-B--A an be written as rv Aloop 0 r (1 ) R be M 4 When assuming ΔV A is the voltage hange at point A, due tothe role of the feedbak loop A-B--A, the feedbak voltage beomes ΔV A A loop at point A. Therefore, onsidering the feedbak loop, the total voltage hange is ΔV A +ΔV A A loop at point A. Sine we have(δv A +ΔV A A loop )/ΔV A =(1+A loop ) and onsider the loop gain A loop, the PSRR of urrent I an be expressed as: I gmp3(1 Aloop ) PSRRI (20) 1 aroa gmp3 For regulate iruit, the relation -1<A loop is valid. Combining with (12),we obtain -1<A loop <0. Using (5) and I 6 =mi, we get the PSRR of output voltage as: ref 2mPSRR PSRR I (21) C K OX 6 In (9)~(21), ΔV refers to the amount of hange of supply voltage V, g m and r o are defined as the transondutane and output resistane of the transistors, respetively, subsript "N" means N-type, subsript "P" means P-type, and subsript number means the number of the transistors. Parameter r Q12 is the output (12) (13) (14) (15) (16) (17) (18) (19) 15 Page

4 A novel voltage referene without the operational amplifier and resistors resistane of Q1,Q2, r V and r CV is the resistane seen from or C to V, r BG is the resistane seen from B to ground, β is urrent gain of Q1 and Q2, and r be is the resistane between the base and emitter of bipolar transistor. In the iruit, sine a >>1 and -1<A loop <0, the value of PSRR of output voltage is very small.consequently, the PSRR is enhaned greatly by these three negative feedbak loops. The negative feedbak loop A-B-C-E-F-A and A-B--A are assoiated with MN5. So we design the aspet ratio (=W/L) of MN5 in order to have a better PSRR and it do not hange fast when supply voltage varies. 2.3 Proess variation Aording to (6), TC of Vref an be expressed as: dvref 2mKM 4kkBln( N) TC k (22) dt qk 6 In this expression,parameters m, k B, N and q are onstant and independent of the proess variation. ue tothe proess variations, the effet on the relative auray of the parameters K M4 and K 6 an be redued by using large-sized transistors.in addition, k shows a very small dependeny on proess variation [1]. Therefore, the TC of the output voltage beomes muh lessdependent on proess variation. V TH isgiven by [1]: Eg N 4 siqn AVT ln( N A / ni ) A VTH T ln( ) (23) 2q ni COX whereε si is the silion permittivity, N A is the hannel doping onentration, n i is the intrinsi arrier density, and E g is the bandgap energy of silion. Sine V TH is a funtion of N A and V TH =V TH0 -kt, V TH0 varies with the hange of N A. Here,ΔV TH,ΔV TH0,ΔVref mean the variation of V TH, V TH0,Vrefdue to theproessvariation.as a result,δv TH ΔV TH0 =ΔVrefan be obtained. III. Simulation results The proposed iruit is verifiedby simulationwith a 0.18μm CMOS tehnology. Fig.2 shows the simulation results of the temperature dependeny of the voltagereferene in the range from -20 to 120, where the supply voltage varies from 1.8 V to 3.0 V. The simulation TC is around 10.8 ppm/ with a supply voltage at 1.8 V and the output voltage is about mv. Fig.3 shows the PSRR at room temperature without any filtering apaitor, where the supply voltage alsovaries from 1.8 V to 3.0 V. The highest PSRR is -70 db at 100 Hz with the supply voltage of 1.8 V. The lowest PSRR is -53 db at 100 khz at the supply voltage of 3.0 V. Although PSRR hanges with different supply voltages, it is always less than -53 db, whih learly shows that these three feedbak loops is useful. Fig.4 shows the output voltage as a funtion of supply voltage at room temperature. The iruit operates orretly when the supply voltage is higher than 1.6 V. The line regulation is 0.75 mv/v when the supply voltage ranges from 1.6 V to 3.1 V. Thus, the proposed sheme is able to ahieve the voltage referene that is almost independent of temperature and supply voltage. The temperature dependene of Vref and V TH are shown in the Fig.5. CurvesVrefmos_ttbjt_tt, Vrefmos_ffbjt_tt, and Vrefmos_ssbjt_tt are similar and parallel with eah other.analogously,urves V TH mos_ttbjt_tt, and V TH mos_ffbjt_tt,v TH mos_ssbjt_ttbehave in the same way. In addition, we have ΔVref/ΔV TH 1 in thetemperature of 25.Therefore, the outputvoltagevariation ΔVref refletsthe threshold voltagevariation ΔV TH.Although the output voltage depends on proess variation, by utilizing ΔVref ΔV TH, the iruit an monitor the proess variation in MOSFET threshold voltage and provides a proess ompensation for the orresponding systems. As a result, this design has its pratial value. Fig.6 shows PSRR at different proess orners at 1.8 V. The highest PSRR is db at 100 Hz when orner of MOS is SS and orner of BJT is TT. The lowest PSRR is db at 100 Hz when orner of MOS is FF and orner of BJT is TT. Therefore PSRR is insensitive to proess variation.fig.7 shows the temperature harateristis of the output voltage for 9 orners, orresponding to the permutation of Fast, Slow and Typial orners of NMOS, PMOS and BJT transistors. The maximum deviation of output voltage at different proess orners is more than 60mv. Howeverin fat, the variation of the referene voltage beomes smaller than proess orners simulation [1], beause the hips are fabriated from the same water. TC from 10.8 ppm/ to 28.5 ppm/ were simulated at 9 different orners. This shows that the TC of the output voltage has a smaller dependene on proess variation. 16 Page

A novel voltage referene without the operational amplifier and resistors Fig.

3PSRR versus frequeny at different supply various supply voltages voltages Fig.

8 V Fig.6PSRR versus frequeny at different proess Fig.7Output voltage Vref versus temperature with orners at 1.

8 displays the layout of the proposed design, and the layout size is 0.012mm2 (100um*120um).

in Fig.9. Curve with plus signs is the simulation urve and the other one is the post layout simulation urve.

5 A novel voltage referene without the operational amplifier and resistors Fig.2Output voltage Vref versus temperature with Fig.3PSRR versus frequeny at different supply various supply voltages voltages Fig.4Vref versus supply voltage at room temperature Fig.5Vref/V TH versus temperature for different proess orners at 1.8 V Fig.6PSRR versus frequeny at different proess Fig.7Output voltage Vref versus temperature with orners at 1.8 Vvarious proess orners at 1.8 V IV. Layout and post layout simulation Fig.8 displays the layout of the proposed design, and the layout size is 0.012mm2 (100um*120um). The omparison of output voltage Vref as a funtion of temperature between simulation and post layout simulation is shown in Fig.9. Curve with plus signs is the simulation urve and the other one is the post layout simulation urve. They are very similar and the maximum deviation is 39.92uv. Fig.10 shows the omparison of PSRR versus frequeny. The urves of simulation and post layout simulation almost overlap when frequeny is less than 10KHz. These two simulation results are almost the same, whih shows that the parasiti parameters of this iruit are very small. Therefore, the design of the iruit is reasonable. 17 Page

A novel voltage referene without the operational amplifier and resistors Fig.8Layout of the proposed BGR Fig.

10Comparison of PSRR versus frequeny between simulation and post layout simulation Table I ompares the performane of the voltage referenes between our iruit and the previous CMOS voltage referenes

Although the iruit in [7] demonstrates a good TC, our design is simpler and needs fewer MOSFETs Table 1.Comparison With The Reported CMOS Voltage Referene Ciruits This work [7] [9] [10] Proess 0.

6 A novel voltage referene without the operational amplifier and resistors Fig.8Layout of the proposed BGR Fig.9Comparison of output voltage Vref versus temperature between simulation and post layout simulation (pls) Fig.10Comparison of PSRR versus frequeny between simulation and post layout simulation Table I ompares the performane of the voltage referenes between our iruit and the previous CMOS voltage referenes [7,9,10]. The voltage referene proposed in this brief shows the better performane in terms of PSRR and TC. Although the iruit in [7] demonstrates a good TC, our design is simpler and needs fewer MOSFETs Table 1.Comparison With The Reported CMOS Voltage Referene Ciruits This work [7] [9] [10] Proess 0.18µm 0.35µm 0.5µm 0.13µm Temperature range V V V 1 V 2.5 V Vref mv mv 723 mv V TC 10.8 ppm/ 13.6 ppm/ 34 ppm/ 25.3 ppm/ Line regulation 0.75 mv/v mv/v 1.07 mv/v NA PSRR -70 db(@100hz) -72 db(@c) NA -27 db(@c) Area 0.012mm mm mm mm 2 V. Conlusion We have proposed a novel voltage referene onsisting of saturated MOSFETs. The iruit generates two voltages with opposite TCs and produes an output voltage with a near-zero TC by adding these TCs together. The design uses the feedbak tehnique instead of operational amplifier to ompensate the supply variations. It 18 Page

7 A novel voltage referene without the operational amplifier and resistors is simulated in the 0.18 µm CMOS tehnology. The results show that TC and line regulation of output voltage are 10.8 ppm/ and 0.75 mv/v respetively. PSRR is -70dB, whih is greatly improved. The design an monitor the proess variation in MOSFET threshold voltage and has its pratial value. VI. Aknowledgements This work was supported partly by Guangdong Siene and Tehnology Program (No.2011B ). Referenes [1] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, A 300nW, 15ppm/ C, 20 ppm/v CMOS Voltage Referene Ciruit Consisting of subthreshold MOSFETs, IEEE J. Solid-State Ciruits, Vol. 44, No.7, 2009,pp [2] M. Ker and J. Chen, New urvature-ompensation tehnique for CMOS bandgap referenes with sub-1-v operation, IEEE Trans. Ciruits Syst. II, Exp. Briefs, Vol. 53, No. 8, 2006,pp [3] B. Ma and F. Yu, A Novel 1.2 V 4.5-ppm/ C Curvature-Compensated CMOS Bandgap Referene IEEE Trans. Ciruits Syst. I, Reg. Papers, Vol. 61, No. 4, 2014, pp [4] Jing-Hu Li, Xing-bao Zhang and Ming-yan Yu, A 1.2-V Pieewise Curvature-Correted Bandgap Referene in 0.5um CMOS Proess, IEEE Trans.Very Large Sale Integr.(VLSI) Syst. Vol. 19, No. 6,2011, pp [5] Inyeol Lee, Gyudong Kim, and Wonhan Kim, Exponential Curvature Compensated BiCMOSBandgap Referenes, IEEE J. Solid-State Ciruits, Vol. 29, No.11, 1994, pp [6] I.M. Filanovsky and Ahmed Allam, Mutual Compensation of Mobility and Threshold Voltage Temperature Effets with Appliations in CMOS Ciruits, IEEE Transations on Ciruits and Systems I: Fundamental Theory and Appliations, Vol. 48, No. 7, 2001, pp [7] Z. K. Zhou, P. S. Zhu, Y. Shi, H. Y. Wang, Y. Q. Ma, X. Z. Xu, L. Tan, X. Ming, and B. Zhang, A CMOS voltage referene based on mutual ompensation of Vtn and Vtp, IEEE Trans. Ciruits Syst. II, Exp. Briefs, Vol. 59, No. 6,2012, pp [8] C. M. Andreou, S. Koudounas, and J. Georgiou, A novel wide-temperature-range, 3.9 ppm/ C CMOS bandgap referene iruit, IEEE J. Solid-State Ciruits, Vol. 47, No. 2, 2012, pp [9] L. Lu, C. Z. Li. Offset error redution using gate-bulk-driven error orretion amplifier for low-voltage sub-bandgap referene, IEEE Eletronis Letters, Vo1.49,2013, pp [10]. Colombo, F. Werle, G. Wirth, and S. Bampi, A CMOS 25.3 ppm/ Bandgap Voltage Referene using Self-Casode Composite Transistor, IEEE Third Latin Amerian Symposium on Ciruits and Systems (LASCAS),2012,pp Page

A novel high-precision curvature-compensated CMOS bandgap reference without using an op-amp

International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 2320-9364, ISSN (Print): 2320-9356 Volume 4 Issue 1 ǁ January. 2016 ǁ PP.26-31 A novel high-precision curvature-compensated