ATF-501P8. Application Note MHz High Linearity Amplifier

Transcription

1 ATF-501P8 450 MHz High Linearity Amplifier Application Note 5058 ATF-501P8 Applications Information Description Avago Technologies ATF-501P8 is an enhancement mode PHEMT designed for high linearity and medium power applications. This application note covers a design approach for use in the 450 MHz band delivering good linearity (OIP3, ACPR, ACLR). Two additional application notes are available covering design approaches for the 900 MHz and 1900 MHz bands. The 450 MHz amplifier design example shown in this application note demonstrates a 41.5 dbm OIP3 with a 1.6 db noise figure, making the ATF 501P8 well suited as a base station transmit driver or a second or third stage LNA in a receiver chain when biased at 4.3V, 280 ma. The amplifier ia also targeted to have a greater than 13 db return loss, so as to eliminate unwanted in band ripple in cascaded amplifier designs. Application Guidelines The ATF-501P8 device operates as a normal FET requiring input and output matching, as well as DC biasing. Unlike a depletion mode transistor, this enhancement mode device only requires a single positive power supply, which means a positive voltage is needed on the drain and gate in order for the transistor to turn on. RF Input and Output Matching In order to achieve maximum linearity, the appropriate input (Γ s ) and output (Γ L ) impedances must be presented to the device. Input (Γ s ) and output (Γ L ) were not available at 450 MHz at the time this note was written. Correctly matching from these impedances to 50Ω will result in maximum linearity, but not necessarily maximum output power or minimum noise figure. Secondly, and not so fortunately, is the fact that any matching network created for good return loss undoubtedly has a very high Q factor. This is because both input and output return loss s-parameters are at low impedance far away from the center of the Smith Chart. In general, high Q matching circuits are undesirable because of their narrow band response and vulnerability to component variations.[1] Thirdly, and most importantly, amplifier stability has to be considered as part of the matching network. At 450 MHz the ATF-501P8 has over 27 db maximum stable gain. Without appropriate input (Γ s ) and output (Γ L ) impedance data, an empirical method was chosen to optimize the OIP3 while maintaining the design targets and unconditional stability. As background information, it is also important to note that OIP3 is largely dependent on the output match and partly dependent on termination of 2nd order mixing products. Passive Bias [2] Once the RF matching has been established, the next step is to DC bias the device. A passive biasing example is shown in Figure 2. In this example, the voltage drop across resistor R3 sets the drain current (Id) and is calculated by the following equation: R3 = V dd V ds I ds + I bb where, Vdd is the power supply voltage; (1) Vds is the device drain to source voltage; Ids is the device drain to source current; Ibb for DC stability is 10X the typical gate current. S11* S22* Figure 1. Matching for the ATF-501P8 at 450 MHz.

2 A voltage divider network with R1 and R2 establishes the typical gate bias voltage (Vg). R1 = V g I bb R2 = (V dd V g )x R1 V g (2) (3) Often the series resistor, R4, is added to enhance the low frequency stability. The complete passive bias example may be found in reference [2]. INPUT Zo R1 C1 L1 R4 R5 C2 C3 R2 Q1 Figure 2. Passive Biasing. I b L4 Vdd C5 R3 C6 C4 OUTPUT Zo Active Bias[3] Due to high DC power dissipation in a small 2x2 mm package, it is recommended that the ATF 501P8 use active biasing. The main advantage of an active biasing scheme is the ability to hold the drain to source current constant over a wide range of temperature variations and device variations. A very inexpensive method of accomplishing this is to use two PNP bipolar transistors arranged in a current mirror configuration as shown in Figure 8. Due to resistors R1 and R3, this circuit is not acting as a true current mirror. But, if the voltage drop across R1 and R3 is kept identical, then it still displays some of the more useful characteristics of a current mirror. For example, transistor Q1 is configured with its base and collector tied together. This acts as a simple PN junction, which helps temperature compensate the Emitter-Base junction of Q2. To calculate the values of R1, R2, R3, and R4 the following parameters must be known or chosen first: I ds the device drain-to-source current I R the reference current for active bias V dd the power supply voltage available V ds the device drain-to-source voltage V g the typical gate bias V be1 the typical Base-Emitter turn on voltage for Q1 & Q2 Therefore, resistor R3, which sets the desired device drain current, is calculated as follows: R3 = V dd V ds' I ds + I c2 (4) where I C2 is chosen for stability to be 10 times the typical gate current and also equal to the reference current I R. If resistor R6 is used, there is additional voltage drop, hence the use of V ds and V ds '. The next three equations are used to calculate the rest of the biasing resistors for Figure 8. Note that the voltage drop across R1 must be set equal to the voltage drop across R3, but with a current of I R. R1 = V dd V ds' I R (5) R2 sets the bias current through Q1. R2 = V ds' V bel I R (6) R4 sets the gate voltage for the ATF 501P8. R4 = V g I C2 (7) Thus, by forcing the emitter voltage (V E ) of transistor Q1 equal to V ds ', this circuit regulates the drain current. As long as Q2 operates in the forward active mode, this hold true. In other words, the Collector-Base junction of Q2 must be kept reverse biased. PCB Layout A recommended PCB pad layout for the Leadless Plastic Chip Carrier (LPCC) package used by the ATF-501P8 is shown in Figure 3. This layout provides plenty of plated through hole vias for good thermal and RF grounding. It also provides a good transition from microstrip to the device package. Using solder mask on the bottom layer often helps avoid solder wicking underneath the package. An AutoCAD drawing of the application demo board may be downloaded via the web at: Figure 3. PCB Package Layout. 2

3 Figure 4. LPCC Package for ATF-501P8. Using the recommended PCB layout also simplifies RF grounding by reducing the amount of inductance from the source to ground. It is also recommended to ground pins 1 and 4 since they are also connected to the device source. Pins 3, 5, 6, and 8 are not connected, but may be used to help dissipate heat from the package, or for better alignment when soldering the device. The ATF application demo board consists of three-layers, with a top layer of 10 mils and a bottom layer of 57 mils separated by a ground plane. The first layer is Getek ML200D material with a dielectric constant of 3.9. The second layer is for mechanical stability and consists of FR4 with a dielectric constant of 4.2. Spectrum Allocation With the complexity of the electromagnetic (EM) spectrum, perhaps it is useful to review the major mobile station and base station frequency allocations (Table 1). The uplink is defined as transmission from Mobile Station (MS) to Base Station (BTS), and the downlink is defined as transmission from the Base Station to Mobile Station. 450 MHz High Linearity Amplifier This application example presents a highly linear Tx driver amplifier for use in the 450 MHz frequency band or downlink. The input is matched for good return loss using a high pass network, and the output is matched for maximum linearity with another high pass network. Unconditional stability has also been a major consideration of the matching networks. The next step is to choose the proper DC bias conditions. From the data sheet, Avago Technologies ATF- 501P8 produces good linearity at a drain current of 280 ma and a drain to source voltage of 4.5V. Thus, to construct the active bias circuit described, the following parameters are given: Ids = 280 ma I R = 10 ma V dd = 5V V ds ' = 4.68V V ds = 4.50V (actual 4.3V) V g = 0.55V V be1 = 0.65V Using equations 4, 5, 6, and 7, the biasing resistor values are calculated in column 2 of table 2, and the actual values used are listed in column 3. Table 2. Resistors for Active Bias. Resistor Calculated Actual R1 32Ω 30.1Ω R2 403Ω 402Ω R3 1.1Ω 1.1Ω R4 55Ω 54.9Ω Table 1. Frequency Allocation in MHz. Uplink (reserve) Downlink (forward) AMPS CDMA CDMA CDMA WCDMA GSM GSM GSM GSM GSM TDMA TDMA iden The entire circuit schematic for a 450 MHz Tx driver is shown in Figure 8. Capacitors C4, C5, and C6 are added as a low frequency bypass. These terminate low frequency second order products and help improve linearity. Resistors R5 and R6 help attenuate low frequencies, and can prevent resonant frequencies between the two bypass capacitors. 3

4 Performance of ATF-501P8 in CDMA450 and GSM450 MHz Bands Avago Technologies ATF-501P8 delivers excellent performance in the CDMA and GSM frequency band. With a drain-to-source voltage of 4.3V and a drain current of 280 ma, this device produces 22.9 db of gain and 1.6 db of noise figure as show in Figure GAIN AND NOISE FIGURE, db Gain, db Noise Figure, db FREQUENCY, MHz Figure 5. Measured Gain and Noise Figure vs. Frequency. Input and output return loss are both greater than 13 db. Although somewhat narrowband, the response is adequate in the frequency range of 463 MHz to 467 MHz for the CDMA downlink or forward channel (Figure 6). If a wider band response is needed, using a balanced configuration improves return loss and doubles OIP3. INPUT AND OUTPUT RETURN LOSS, db FREQUENCY, MHz Input RL Output RL Figure 6. Measured Input and Output Return Loss vs. Frequency. Perhaps the most critical system level specification for the ATF 501P8 lies in its distortionless output power. Typically, amplifiers are characterized for linearity by measuring OIP3. This is a two-tone harmonic measurement using CW signals. The OIP3 was measured at 41.5 dbm at an output power of 4 dbm. Figure 7. Component Placement. Table MHz Bill of Materials. C1 = 22 pf Panasonic ECJ-OEC1H220J C2 = 12 pf Johanson 250R07C120JV4T C3 = 150 pf Panasonic ECJ-0EC1H151J C4,C5 = 10 nf KEMET C0402C103K3RACTU C6 = 1 µf KEMET C0805C105K8RACTU C7 = 180 pf Panasonic ECJ-0EC1H181J L1 = 6.8 nh TOKO LL1005-FH6N8J L2 = 18 nh TOKO LL1005-FH18NJ L3 = 47 nh TOKO LL1608-FS47NJ L4 = 10 nh TOKO LL1005-FS10NJ R1 = 30.1Ω KOA RK73H1J30R1F R2 = 402Ω KOA RK73H1JLTD4020F R3 = 1.1Ω KOA RK73H1J1R10F R4 = 54.9Ω KOA RK73H1J54R9F R5 = 6.8Ω KOA RK73H1JLTD6R81F R6 = 1.0Ω Yageo 9C04021A1R00FLHF3 R7 = 1.5 Ω Panasonic ERJ-2GEJ1R5X R8 = 10Ω Yageo 9C04021A10R0FLHF3 Q1, Q2 Philips BCV62C J1,J2 Johnson

5 R2=402 Q1 VE R1=30.1 Vdd Hence, very similar to Ohms Law, the temperature of the channel is calculated with equation 8 below. R4=54.9 Vg Q2 Vds' R3=1.1 C6=1 F T CH = P diss x (θ ch b + θ b s + θ s a ) + T amb (8) C4=10nF C3=150pF R5=6.8 R6=1 C5=10nF C7=180pF If no heat sink is used or heat sinking is incorporated into the PCB board, then equation 8 may be reduced to: RFin J1 C1=22pF L1=6.8nH L2=18nH 2 7 0PL ATF-501P8 L3=47nH C2=12pF RF out J2 L4=10nH T CH = P diss x (θ ch b + θ b a ) + T amb (9) where, θ ch b is the channel to board thermal resistance; θ b a is the board to ambient thermal resistance. R7=1.5 Figure 8. Schematic Circuit at 450 MHz Using Active Bias. Thermal Design When working with medium to high power FET devices, thermal dissipation should be a large part of the design. This is done to ensure that for a given ambient temperature the transistor s channel does not exceed the maximum rating, T CH, from the data sheet. For example, ATF 501P8 has a maximum channel temperature of 150 C and a channel to board thermal resistance of 23 C/W. Thus, the entire thermal design hinges on these key data points. The question that must be answered is whether this device can operate in extreme environments with ambient temperature fluctuations from -25 C to +85 C. From Figure 9, a very useful equation is derived to calculate the temperature of the channel for a given ambient temperature. These calculations are all incorporated into Avago Technologies AppCAD. The latest version can be downloaded for free at Pdiss=Vds x Ids θ ch-b θ b-s θ s-a Tch (channel) Tb (board or belly of the part)* Ts (sink) R8=10 Ta (ambient) *Note: For this example the board temperature is assumed to be the case temperature. Figure 9. Equivalent Circuit for Thermal Resistance. The board to ambient thermal resistance thus becomes very important, for this is the designer s major source of heat control. To demonstrate the influence of θ b a, thermal resistance at two extreme cases is compared. The first experiment is done with just the ATF-501P8 demo board and no heat sinking. The second case uses a much thinner demo board mounted on a 1/8" chassis with a fan. Calculating the temperature of the channel for these two scenarios gives a good indication of what type of heat sinking is needed at 85 C. Worst Case 1: 60 mil board with no heat sink, no 85 C Tch = P x (θ ch b + θ b a ) + Ta = 1.26W x ( ) C/W +85 C Tch = 155 C Best Case 2: 20 mil board chassis mounted with 85 C Tch = P x (θ ch b + θ b a ) + Ta = 1.26W x (23+3.0) C/W +85 C Tch = 118 C 5

6 In other words, if the board is mounted to a chassis as in case 2, the channel temperature is guaranteed to be 118 C, safely below the maximum temperature of 150 C. On the other hand, if no heat sinking is used,å as in case 1, then the channel temperature at 155 C slightly exceeds the absolute maximum rating. This is illustrated in Figure 10. Note power is derated at 18 mw/ C for the board with no heat sink and at 38 mw/ C for the chassis mounted board. Hence, for case 1, once the ambient temperature reaches 80 C, the device dissipated power must be derated in order to keep the channel temperature below 150 C. For reliable operation of the ATF 501P8 and extended MTBF, some form of thermal heat sinking is recommended, especially at high power dissipation. This may include any or all of the following suggestions: Table 4. Typical Performance for ATF-501P8. Results at 450 MHz Gain = 22.9 db OIP3 = 41.5 dbm P1dB = 25.0 dbm NF = 1.60 db Table 5. Thermal Resistance Measurements for various heat sinks. ATF Demoboard Fan 60 mil 20 mil θ b-a[ C/W] θ b-a[ C/W] PCB 1/8" Chassis ambient PCB 1/8 Chassis 350LFM Extrusion ambient Extrusion 350LFM Pin Fin ambient Pin Fin 350LFM PCB no HeatSink ambient PCB no HeatSink 350LFM Maximize vias underneath and around package Maximize exposed surface metal Use at least 1 oz copper clad Minimize board thickness Metal heat sinks or extrusions Fans or forced air Mount PCB to Chassis Summary A high linearity amplifier for CDMA450 and GSM450 has been presented and designed using Avago Technologies ATF-501P8. This includes RF, DC, and good thermal dissipation practices. A summary of the results is provided in Table 4. A plot of the stability factor, K, in Figure 11 shows the amplifier is unconditionally stable. Figure 10. Derating for ATF-501P8 at 1.26W. Figure 11. Measured stability factor, K, vs. Frequency, GHz. 6

7 References: [1] The Care and Feeding of High Speed Dividers, data/appnotes/an178.pdf. [Accessed 11 November, 2002]. [2] Ward, A. AN-1222 Avago Technologies ATF Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plasitic Package, [Accessed 22 August, 2002]. [3] Biasing Circuits and Considerations for GaAs MESFET Power Amplifiers, AN 0002_ajp.pdf. [Accessed 22 August, 2002]. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright Avago Technologies, Limited. All rights reserved EN May 19, 2010