Aspects of Digital Electronics Chemistry 838

Transcription

1 spects of Digital Electronics hemistry 838 Thomas V. tkinson, Ph.D. Senior cademic Specialist Department of hemistry Michigan State University East Lansing, MI Table of ontents TLE OF ONTENTS... TLE OF TLES... 2 TLE OF FIGURES INTRODUTION GENERI GTES ND FLIP FLOPS GTES FLIP FLOPS INRY VRILES GTES LOGI GTES GTE SYMOLS GTING SIGNLS nd Or Nand Nor Time Varying Example PHYSIL IMPLEMENTTIONS nd Or Inverse DIGITL IRUIT NLYSI LTHES SIMPLE LTH... 6 November 4, Version.

2 hemistry 838 Table of Tables spects of Digital Electronics 5.2. GTED LTH GTED LTH WITH PRESET DT LTH SIMPLE FLIP FLOP JK FLIP FLOP OUNTERS INRY Two Stages Three Stages n Stages VRILE MODULUS Modulo Modulo Modulo Modulo Modulo Modulo Modulo Modulo Modulo Timing Example (Modulo 5) INRY OUNTER WITH PRESET VRILE MODULUS OUNTER UP/DOWN OUNTER REVISION HISTORY... 4 Table of Tables TLE - GENERI GTE, SWITH, LTH - DEFINITIONS...5 TLE 2 - TRI-STTE GTE - TLE OF STTES...5 TLE 3 - DEFINING EHVIOR OF FLIP FLOP...6 TLE 4 - FLIP FLOP - SET ND LER...7 TLE 5 - INRY VRILES - TLE OF STTES...8 TLE 6 - LTERNTIVE REPRESENTTION...8 TLE 7 - LTERNTIVE REPRESENTTION TLE 8 - LOGI VRILES ND OPERTORS - TRUTH TLES...8 TLE 9 - XOR ND EULITY GTES...9 TLE - ND IRUIT - TLE OF STTES...4 TLE - OR IRUIT - TLE OF STTES...4 TLE 2 - INVERSE IRUIT - TLE OF STTES...5 TLE 3 - LOGI FMILIES...5 TLE 4-4 NND IRUIT - TLE OF STTES...6 TLE 5 SIMPLE LTH - TLE OF STTES...7 TLE 6 - GTED LTH - TLE OF STTES...8 TLE 7 - GTED LTH WITH PRESET TLE OF STTES...9 TLE 8 - D LTH - TLE OF STTES...2 TLE 9 JK FLIP FLOP TLE OF STTES...2 TLE 2-2 STGE OUNTER TLE OF STTES...23 TLE 2-3 STGE OUNTER TLE OF STTES...24 November 4, Version.

3 hemistry 838 Table of Figures spects of Digital Electronics TLE 22 - POWERS OF TLE 23 - SUMMRY OF VRILE MODULUS ONFIGURTIONS...27 TLE 24 4 STGE OUNTER WITH OVERFLOW - STTE TLE...36 TLE 25 MODULO 5 OUNTER, PRELOD VLUE =...37 TLE 26 MODULO 9 OUNTER, PRELOD VLUE = TLE IT MULTIPLEXER - TLE OF STTES...4 TLE IT MULTIPLEXER - TLE OF STTES (REVITED)...4 Table of Figures FIGURE - GENERI GTE, SWITH, ND LTH...4 FIGURE 2 - TRI-STTE GTE...5 FIGURE 3 - GENERI FLIP FLOP...6 FIGURE 4 - EXMPLE TIME OURSE...6 FIGURE 5 - FLIP FLOP - TIMING DIGRM...7 FIGURE 6 - INVERTER...9 FIGURE 7 - ONE PPROH TO IMPLEMENTING N INVERTER...9 FIGURE 8 - ND GTE...9 FIGURE 9 - OR GTE...9 FIGURE - NND GTE...9 FIGURE - NOR GTE...9 FIGURE 2 - NOR GTE (EUIVLENT)... FIGURE 3 - NND GTE (EUIVLENT)... FIGURE 4 - EXLUSIVE OR GTE - XOR... FIGURE 5 - EULITY GTE... FIGURE 6 - GTED SIGNL EXMPLE...2 FIGURE 7 - INRY VRILES - PHYSIL IMPLEMENTTION...3 FIGURE 8 - ND IRUIT...4 FIGURE 9 - OR IRUIT...4 FIGURE 2 - INVERSE IRUIT...5 FIGURE 2 - NLYSIS OF 4 NND IRUIT...6 FIGURE 22 - SIMPLE LTH...6 FIGURE 23 - GTED LTH...8 FIGURE 24 - GTED LTH - SYMOL...8 FIGURE 25 - GTED LTH WITH PRESET...9 FIGURE 26 - GTED LTH WITH PRESET - SYMOL...9 FIGURE 27 - D LTH...2 FIGURE 28 - SIMPLE FLIP FLOP...2 FIGURE 29 - RE ONDITION...2 FIGURE 3 TWO OUPLED FLIP FLOPS...22 FIGURE 3 - TWO OUPLED FLIP FLOPS - TIMING DIGRM...22 FIGURE 32 - THREE STGE RIPPLE OUNTER...23 FIGURE 33 - VRILE MODULUS OUNTER...27 FIGURE 34 - MODULO 5 OUNTER TIMING...34 FIGURE 35-4 PULSE TRINS...34 FIGURE 36 - INRY OUNTER WITH PRELOD...35 FIGURE 37 MODULO-5 OUNTER TIMING...37 FIGURE 38 MODULO-9 OUNTER TIMING...39 FIGURE 39 2-IT DIGITL MULTIPLEXER...39 FIGURE 4 - SIMPLE UP/DOWN OUNTER...4 November 4, Version.

4 hemistry 838. Introduction Introduction spects of Digital Electronics Digital electronics is the basis of all modern computing and digital instrumentation including the digital watches that many people wear. This document provides an introduction to the subject and is the transcription of my lecture notes as they have evolved over the past three plus decades. 2. Generic Gates and Flip Flops 2.. Gates Figure and Table define three generic devices, which may be either analog or digital devices. The devices are three port devices with two inputs, e.g. e in and a control signal e G, e S, or e L, and one output, e out. The devices have two states. The control signal determines in which of the two states the device is at a particular time. GateSwitchLatch_.cdr 7-Oct-24 e in Gate e out e in Switch e out e in Latch e out e G e S e L Switch ontrol e S Figure - Generic Gate, Switch, and Latch The gate nomenclature comes from the barnyard gate, i.e. when the gate is open, the animals can go through the gate; when the gate is closed then animals can not go through the gate. The latch is basically a camera, i.e. it captures a snapshot of the value of e in at the time of the transition of e L and holds it for later inspection. November 4, Version.

5 hemistry 838 Generic Gates and Flip Flops Table - Generic Gate, Switch, Latch - Definitions spects of Digital Electronics Device State ontrol Signal ehavior Gate Open e G = Open e out = e in losed e G = losed e out = constant ( also may be disconnected) Switch losed e S = losed e out = e in Open e S = Open e out = constant Latch Follow e L = Follow e out = e in Latched e L = Latch e out = e in (t = Latch Follow ) Figure 2 illustrates a derivative combination, the tri-state gate which has the characteristics shown in Table 2. This device derives its name from the fact that there are essentially three states: high, low, and disconnected. Such devices have great utility when constructing a bus, i.e. a party line or shared communication facility. The digital bus is discussed further in spects of omputer rchitecture. TriStateGate_.cdr -Oct-24 e in Gate Switch e out e G e S Figure 2 - Tri-State Gate Table 2 - Tri-State Gate - Table of States Switch ontrol Gate ontrol ehavior e S = losed e G = Open e out = e in e S = losed e G = losed e out = constant e S = Open e G = Open Device is disconnected from the following circuitry. e S = Open e G = losed Device is disconnected from the following circuitry. These generic concepts have widespread application in both digital and analog electronics. The remainder of this document will explore how these devices are implemented and applied in the digital domain. November 4, Version.

6 hemistry 838 Generic Gates and Flip Flops spects of Digital Electronics 2.2. Flip Flops Figure 3 is the symbol used for the generic flip flop. The behavior of the device is shown in Table 3 and Figure 4 FlipFlops_.cdr 5-Oct-24 FlipFlop_2.cdr 5-Oct-24 Set lock lock lear Figure 3 - Generic Flip Flop t t t 2 t 3 t 4 t 5 t 6 Time Figure 4 - Example Time ourse Table 3 - Defining ehavior of Flip Flop Time ctually, the transitions occur on a rising edge ( ) or a falling edge ( ) of the lock signal depending on the implementation of the device. The roles of the Set and lear inputs are described in Table 4. Notice that the toggle behavior is only seen when neither Set nor lear is asserted. The term asserted was chosen because some actual devices have these two input signals being asserted on a Hi, while other devices assert on a Lo. November 4, Version.

7 hemistry 838 inary Variables Table 4 - Flip Flop - Set and lear spects of Digital Electronics ction Results of ction ction ssert Set Flip Flop is set ssert lear Flip Flop is cleared ssert neither Set or lear Flip Flop is allowed to toggle ssert both Set or lear?? Undefined, not allowed If lock is a periodic signal, the behavior shown in Figure 5 occurs. Notice that p = 2p or flock f =. Thus, the flip flop is also called a divide by 2 circuit. Don t forget that this holds 2 only for periodic signals. FlipFlop_4.cdr 5-Oct-24 p lock lock lock p p Figure 5 - Flip Flop - Timing Diagram 3. inary Variables Logic is a traditional subject found in philosophy and mathematics that deals with the manipulation of entities that can exist in only two forms or states. In traditional logic, the two forms are named true and false. ombinations of these entities can be created using the operations of logic. The combinations are in themselves members of the set of logical entities. nother naming convention uses and. With the advent of physical implementations of this subject during the 94 s and 95 s, an additional naming conventions of High and Low came into use to reflect the voltage levels used to represent the logical entities. The additional naming conventions Hi and Lo, and Open and losed are also used. The mathematics of entities that exist in only two states and the attendant operations is called oolean lgebra. Typically, the two state entities are called variables and are identified with names or strings of characters such as,,, D,,, lock, pple, lear, Set, Orange, xxyy, etc. Table 5 November 4, Version.

8 hemistry 838 Gates spects of Digital Electronics shows the conventions used in this document. In this example, the two possible values of the variable, are labeled and. Table 6 and Table 7 illustrate two analogous representations. The concept of inverse is also included in Table 5 and Table 6 and Table 7. The inverse of a variable is defined as a new binary variable, identified with the symbol for the original variable, that is always in the opposite state. ny variable with the bar over the name is the inverse of the original variable. The bar is a unary operator called inverse, bar, or not. Table 5 - inary Variables - Table of States Table 6 - lternative Representation Table 7 - lternative Representation 2 lo hi F T hi lo T F 4. Gates 4.. Logic Gates The discussion of gates in digital electronics begins with a discussion of the operators of traditional logic. Table 8 defines two of the basic operators, and and or, of binary logic. The third basic operator is the not or inverse operator. fourth operator, xor, will be introduced later. The behavior of these operators is based in the following four definitions. The inverse of a logic variable is a logic variable that is always in the opposite state. The and of any number of logic variables is a logic variable that is true only when all of the variables being combined are true. The or of any number of logic variables is a logic variable that is true when any of the variables being combined are true. The exclusive or ( xor ) of two logic variables is a logic variable that is true when one and only one variable is true. Table 8 - Logic Variables and Operators - Truth Tables.ND. +.OR..ND. +.OR..ND..OR. + November 4, Version.

9 hemistry 838 Gates spects of Digital Electronics Table 9 shows the definition of the exclusive or, i.e. xor, and equality operations. These operators can be derived from the basic three operators, and, or, and not. Table 9 - Xor and Equality Gates Notice that the two following are true. + = = + These are De Morgan Theorems and are examples of oolean lgebra. This section contains the total basis of digital electronics and computing. Everything else can be derived from these basic principles Gate Symbols The following symbols are used to represent both the logic operations and the physical devices that implement the logic operations. When the symbols refer to physical devices remember that the real devices require connections to power and common. These connections will be understood and not included in the symbols. Logicc _ Figure 6 - Inverter Logicb _ M = Figure 7 - One pproach to Implementing an Inverter Logica M = Figure 8 - nd Gate Logic3a Figure 9 - Or Gate M = + Logic M = Figure - Nand Gate Logic3 M = + Figure - Nor Gate November 4, Version.

10 hemistry 838 Gates spects of Digital Electronics Logic M = = + Figure 2 - Nor Gate (Equivalent) Logic2.cdr M = + = Figure 3 - Nand Gate (Equivalent) Logic3.cdr Logic9 M = + M Figure 4 - Exclusive Or Gate - Xor Figure 5 - Equality Gate 4.3. Gating Signals These devices are commonly called gates. The motivation for this nomenclature can be seen in the following four examples where each of the basic gates is shown to have the gating behavior, i.e. one signal controls whether the other passes through the device or not nd Logica M =.ND. Let be the gate control: If =, then M = = =. Thus, the gate is OPEN, the signal can pass through. If =, then M = = = Thus, the gate is LOSED, the output is independent of the signal Or November 4, Version.

11 hemistry 838 Gates spects of Digital Electronics Logic3a M = + +.OR. Let be the gate control: If =, then M = + = + = Thus, the gate is LOSED, the output is independent of the signal. If =, then M = + = + =. Thus, the gate is OPEN, the signal can pass through Nand Logic M =.ND. Let be the gate control: If =, then M = = =. Thus, the gate is OPEN, the signal can pass through but the signal is inverted. If =, then M = = = =. Thus, the gate is LOSED, the output is independent of the signal Nor Logic3 M = + +.OR. Let be the gate control: If =, then M = + = + = = Thus, the gate is LOSED, the output is independent of the signal. November 4, Version.

12 hemistry 838 Gates spects of Digital Electronics If =, then M = + = + =. Thus, the gate is OPEN, the signal can pass through but the signal is inverted Time Varying Example Figure 6 contains an example of gating a time varying signal. In this case, the Nor gate is being used to control the flow of the signal. Input is to be considered as the gate control. Notice that signal is not periodic and was chosen to illustrate that arbitrary signals can be manipulated by the gate. The inverse of the signal is passed through the gate during the period of time between t and t 2, i.e. when the gate is open. GatedSignal.cdr 7-Oct Physical Implementations t t 2 Figure 6 - Gated Signal Example Physical devices can be built that implement the logic operations illustrated in Table 8 and Table 9. elow are the symbols for these devices. Each of the logic states is represented by a voltage range as illustrated in Figure 7. The voltages shown here are but an example, each logic family will have a definition of the ranges. Notice that there is a buffer region between the two states. This makes it easier to differentiate between signals that are high and signals that are low. In effect, this decreases the effect that noise has in the circuits. This is often called the source of the digital advantage over analog techniques. November 4, Version.

13 hemistry 838 Gates Digitaldvantage_.cdr 9-Oct-24 spects of Digital Electronics 5 volts 4 volts Hi High Hi Low High uffer Region volts volts Lo High Lo Low Low Figure 7 - inary Variables - Physical Implementation elow are three physical implementations of logic function. The implementations included in a particular family of logic will vary as the designers seek to optimize the figures of merit. November 4, Version.

14 hemistry nd Gates spects of Digital Electronics PhysicalGates_.cdr 7-Oct volts R Table - nd ircuit - Table of States e out S 2 S 2 e out M Switch ontrol S 2 Switch ontrol S losed losed losed Open Open losed Open Open 5 volts 2 Figure 8 - nd ircuit Or +5 volts PhysicalGates_2.cdr 7-Oct-24 Table - Or ircuit - Table of States Switch ontrol 2 S 2 Switch ontrol S R Figure 9 - Or ircuit e out S 2 S 2 e out M Open Open Open losed 5 volts losed Open 5 volts losed losed 5 volts November 4, Version.

15 hemistry Inverse Gates spects of Digital Electronics PhysicalGates_3.cdr 7-Oct volts R e out Table 2 - Inverse ircuit - Table of States S S e out M Open 5 volts Switch ontrol losed Figure 2 - Inverse ircuit Table 3 - Logic Families Name Full Name ontains 94 s- 95 s Vacuum tubes, R, RTL Resistor Transistor Logic Transistors, R, DTL Diode Transistor Logic Diodes, transistors, R, TTL Transistor Transistor Logic Transistors, R, EL Emitter oupled Logic Transistors, R, MOS omplementary Metal Oxide Semiconductor Fet Logic Fet transistors, R, Figures of merit for Logic Families Speed Power onsumption Fan out How many gates the output of a gate can drive Size ost November 4, Version.

16 hemistry Digital ircuit nalysi Latches spects of Digital Electronics 2 Logic 4 M = + 3 Figure 2 - nalysis of 4 Nand ircuit Table 4-4 Nand ircuit - Table of States Inputs Nand Outputs Latches 5.. Simple Latch Latch_.cdr 7-Oct-24 S M R M 2 Figure 22 - Simple Latch November 4, Version.

17 hemistry 838 Latches spects of Digital Electronics The behavior of the device is derived by examining the six cases below. The notation, M ip, is used to indicate the value of M i at the time of the transition from the previous state to the present. S =, R = = S M = M = M is forced to be M 2 2 = M 2 = = R M = M = M M 2 is forced to be. Thus the device is Set. S =, R = = R M = M = M 2 is forced to be M 2 = M 2 = = S M 2 = M 2 = M M is forced to be. Thus the device is leared. S =, R = M P = M 2P = M = R M = M = = M 2 remains = M 2P. 2 P P = M 2 = = S M 2P = M 2P = M = M remains = M P, thus latch is achieved. M P =, M 2P = M = R M = M = = M 2 remains = M 2P. M 2 P P = = S M 2P = M 2P = M 2P = M remains = M P, thus latch is achieved. = S =, R = M 2 = R M = M = = This is an undesirable situation. M 2 2 = S M = M = = Table 5 Simple Latch - Table of States Set Reset S R M M 2 omments M P M Latched P Reset Set Undesirable disadvantage of this simple latch is that the outputs change whenever the inputs change. November 4, Version.

18 hemistry Gated Latch Latches spects of Digital Electronics Figure 23 shows an approach to separate the inputs from the latched device. When Load =, the inputs are uncoupled from the Simple Latch. Latch_2.cdr 7-Oct-24 S M 3 M 3 Latch_3.cdr 7-Oct-24 S Load (lock) lock R R 2 M 2 Figure 23 - Gated Latch 4 M 4 Figure 24 - Gated Latch - Symbol Table 6 - Gated Latch - Table of States Load Set Reset S R M M 2 omment X X M P M P M Latched P M Latch new P value Reset Set Undesirable November 4, Version.

19 hemistry Gated Latch with Preset Latches spects of Digital Electronics Latch_4.cdr 8-Oct-24 Preset Latch_4.cdr 7-Oct-24 S M M 3 Preset S Load (lock) lock R lear R M 2 M 4 lear Figure 25 - Gated Latch with Preset Figure 26 - Gated Latch with Preset - Symbol Table 7 - Gated Latch with Preset Table of States lear PreSet Load Set Reset S R M 3 M 4 omment X X X Undesirable X X X Reset X X X Set X X Latched M P M Latch new P value Reset Set Undesirable November 4, Version.

20 hemistry Data Latch Latches spects of Digital Electronics Latch_6.cdr 7-Oct-24 Data X X _ X M 3 M 3P X M 3 Load _ X 2 X M 2 4 M 3P X M 4 M 3P is the previous value of M 3, i.e. that at the time of the last transition of LOD from to. Figure 27 - D Latch Table 8 - D Latch - Table of States Load Data S R M 3 M 4 omment X M P M Latched P X Reset Set 5.5. Simple Flip Flop The next step is to fashion a flip flop out of these real devices. This is attempted by cross coupling the inputs and outputs as in Figure 28. ssume the flip flop is set initially and lock is not asserted. s soon as the clock is asserted, the inputs cause the outputs to change, which in turn presents new values to the inputs, which cause the outputs to change again. This oscillation keeps up as long as lock is asserted. Furthermore, the state in which the circuit lands when the assertion of lock is removed is indeterminate. Figure 29 illustrates the time course of this undesirable race condition. SimpleFlipFLop_.cdr -Oct-24 S lock R Figure 28 - Simple Flip Flop November 4, Version.

21 hemistry 838 Latches spects of Digital Electronics SimpleFlipFLop_2.cdr -Oct-24 S R Figure 29 - Race ondition 5.6. jk Flip Flop Latch_8.cdr 7-Oct-24 j M S S lock lock M 2 k R R Master Slave lock Latch_8.cdr 7-Oct-24 lock Master latched Slave follows Master follows Slave latched Master latched Slave follows Table 9 jk Flip Flop Table of States j k omments Latched Reset Set t- t- Toggles November 4, Version.

22 hemistry ounters ounters spects of Digital Electronics The next topic is the examination of digital counters, which have utility in the measurement of time and frequency, computing and many modern instrumental techniques. For this topic, the generic flip flops will be used. 6.. inary 6... Two Stages Returning to the discussion of the generic flip flop (see Section 2.2. step is to combine two of the devices as shown in Figure 3. FlipFlops_5.cdr 5-Oct-24 Flip Flops), the next In Set lock Set lock lear lear Figure 3 Two oupled Flip Flops p In FlipFlop_6.cdr 5-Oct-24 In t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 p Figure 3 - Two oupled Flip Flops - Timing Diagram p If In is a periodic signal and both flip flops are initially in the cleared state, then the circuit behaves as shown in Figure 3. Notice that the initial state is seen at t, t 4, and t 8. Further, notice f fin that p = 2 p = 4pIn or f = =. Thus, this combination of the two flip flops is often 2 4 called a divide by 4 circuit. Don t forget that this holds only for periodic signals. November 4, Version.

23 hemistry 838 ounters spects of Digital Electronics n alternative approach to describing this circuit is shown in Table 2 where the state of the device after each pulse on In is listed. Table 2-2 Stage ounter Table of States Values at t i Decimal i Notice that the counter rolls over every 4 counts and returns to the initial state Three Stages Next, three flip flops will be cascaded as shown in Figure 32 FlipFlops_8.cdr 5-Oct-24 Set Set Set In lock lock lock lear lear lear Figure 32 - Three Stage Ripple ounter The behavior of this circuit could be described with timing diagrams as was done for the case of one and two flip flops. However, as the number of stages increase, the approach embodied in Table 2 becomes more economical. November 4, Version.

24 hemistry 838 spects of Digital Electronics ounters f f fin p = 2 p = 4p = 8p f = = = In Thus, or and this combination of the three flip flops is also called a divide by 8 circuit. Don t forget that this holds only for periodic signals. Table 2-3 Stage ounter Table of States Decimal fter Pulse on In Notice that the counter rolls over every 8 counts and returns to the initial state. November 4, Version.

25 hemistry n Stages ounters Table 22 - Powers of 2 spects of Digital Electronics n DE OT HEX ommon Name K K K K K K K K K K M or Meg M or 2Meg M or 4Meg M or 8Meg M or 6Meg M or 32Meg M or 64Meg M or 28Meg M or 256Meg M or 52Meg G or Gig G or 2Gig G or 4Gig If the,, and are considered digits of a binary number, this circuit can be seen to be counting the number of pulses presented at In. This behavior can be generalized. Given n stages of flip flops cascaded as described above, the results is a counter that has 2 n unique states and November 4, Version.

26 hemistry 838 ounters spects of Digital Electronics counts from to 2 n -. The 2 n th count causes the counter to roll over or reset to the initial state, i.e. all zeros. ctually, adding one to the counts causes a carry to be generated, which is disregarded in these devices. Table 22 contains the values of the first 32 powers of 2 expressed in base (decimal or DE), base 8 (octal or Oct), and base 6 (hexadecimal or Hex). The right most column of Table 22 contains the common names often given to the corresponding quantities. This nomenclature is an artifact of the computer industry which early on chose to use the short hand name one K to represent the much longer and more appropriate name One thousand twenty four, etc. real flip flop, as with any real device, takes time to change states, i.e. there is a delay between the time new values occur on the inputs of the device and the outputs change to reflect the new inputs. When devices are cascaded as seen here, the first device takes an amount of time to settle to the new state after the clock pulse and the next stage doesn t even see the effect of the pulse until after the first delay has occurred. The third device has to wait for the second stage to settle, and so on. Thus, the new value ripples through the counter. For a counter with n stages, the time for a new value to settle is on the order of n*t delay where t delay is the time required for one flip flop to settle. This defines the maximum speed at which the counter can properly operate, i.e. the new value settles in before the next clock pulse occurs at the input of the circuit. To count faster, one must use faster flip flops or go to other techniques, e.g. synchronous counters Variable Modulus The approach seen above can be extended to counters of other than modulo 2. These counters can be implemented by resetting the flip flops of the binary counter at the proper point during the accumulation of counts. This section will explore a few of these. The circuit of Figure 33 is completed by connecting various outputs of the flip-flops to the inputs, X, Y, and Z, of the three input Nand gate. pulse train (periodic or not) is connected to the input IN. ll three flip flops are initially cleared. The flip flops are cleared by a low on the lear inputs. The Shot or monostable outputs a pulse of constant width that is determined by R. This is done to insure that LERLL is low long enough to cause all stages to clear. s you will see, only the configurations for modulo 5, 6, 7, and 8 are worthwhile. In fact, the Modulo 8 configuration is exactly the case of Figure 32. Modulo 4 can be accomplished with two flip-flops with out the extra logic. Modulo 3 can be achieved with two flip-flops and a two input Nand Gate. The modulo and configurations have no value. November 4, Version.

27 hemistry 838 ounters spects of Digital Electronics VariableModulusounter.cdr -Oct-24 Set Set Set In lock lock lock lear lear lear LERLL X Y Z Shot Trig R Figure 33 - Variable Modulus ounter Table 23 - Summary of Variable Modulus onfigurations Modulo Z Y X omment 8 none none none Only need the three flip-flops without the extra logic. 7 Valid use of circuit. 6 Valid use of circuit. 5 Valid use of circuit. 4 Why not just use the two flip-flops without the extra logic? 3 Why not just use two flip-flops with a two input Nand? 2 Why not just use a single flip-flop? Why bother? Does nothing. In the tables below, the following convention is used. This state is very short lived. Flip-flops are immediately reset within the delay time that is characteristic of the devices. November 4, Version.

28 hemistry Modulo onnections: to X, to Y, to Z ounters spects of Digital Electronics LERLL = Decimal fter Pulse # Modulo onnections: efore st to X, lear is always asserted, flip-flops will never toggle. to Y, to Z LERLL = Decimal fter Pulse # efore st * clear immediately * 2 clear immediately * 3 clear immediately * 4 clear immediately * 5 clear immediately * 6 clear immediately * 7 clear immediately * 8 clear immediately * Transitory. Disappears immediately. November 4, Version.

29 hemistry Modulo 2 onnections: to X, to Y, to Z ounters spects of Digital Electronics LERLL = Decimal fter Pulse # efore st 2* 2 clear immediately 3 2* 4 clear immediately 5 2* 6 clear immediately 7 2* 8 clear immediately * Transitory. Disappears immediately Modulo 3 onnects: to X, to Y, to Z LERLL = Decimal fter Pulse # efore st 2 2 3* 3 clear immediately * 6 clear immediately * 9 clear immediately * Transitory. Disappears immediately. November 4, Version.

30 hemistry Modulo 4 onnections: to X, to Y, to Z ounters spects of Digital Electronics LERLL = Decimal fter Pulse # Modulo 5 onnections: efore st * 4 clear immediately * 8 clear immediately to X, to Y, * Transitory. Disappears immediately. to Z LERLL = Decimal fter Pulse # efore st * 5 clear immediately * clear immediately * Transitory. Disappears immediately. November 4, Version.

31 hemistry Modulo 6 onnections: to X, to Y, to Z ounters spects of Digital Electronics LERLL = Decimal fter Pulse # efore st * 6 clear immediately * 2 clear immediately * Transitory. Disappears immediately. November 4, Version.

32 hemistry Modulo 7 onnections: to X, to Y, to Z ounters spects of Digital Electronics LERLL = Decimal fter Pulse # efore st * 7 clear immediately * 4 clear immediately * Transitory. Disappears immediately. November 4, Version.

33 hemistry Modulo 8 onnections: None ounters spects of Digital Electronics Decimal fter Pulse # efore st November 4, Version.

34 hemistry Timing Example (Modulo 5) ounters spects of Digital Electronics p In Modulo5Timing.cdr -Oct-24 In t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t t t 2 t 3 t 4 t 5 t 6 p Figure 34 - Modulo 5 ounter Timing Figure 34 illustrates the timing for the modulo 5 counter. Notice that p = 5p or and this combination of the three flip flops can be called a divide by 5 circuit. In f = fin 5 ountingedges.cdr -Oct-24 D Figure 35-4 Pulse Trains n important fact to remember is that all of the binary and variable modulo counters are really counting edges. Thus, all 4 pulse trains in Figure 35 would give the same answer, i.e. 8, when November 4, Version.

35 hemistry 838 ounters spects of Digital Electronics input to the counter of Figure 32. The circuits have divide by n property only when the input signal is periodic inary ounter with Preset Up to this point, the assumption has been made that the counters begin zeroed, i.e. all flip flops are in the cleared state. Figure 36 illustrates a 4 stage binary counter where a starting value can be loaded before the counting begins by presenting the value to the Preset i and strobing Load. The counter also has a fifth stage to indicate when an overflow occurs. Table 24 is the table of states for the counter. ounter_presets.cdr 28-Oct-24 D Overflow IN Set lock Set lock Set lock Set lock Set lock Over lear lear lear lear lear Under Load Preset Preset Preset Preset D Figure 36 - inary ounter with Preload November 4, Version.

36 hemistry 838 ounters Table 24 4 Stage ounter with Overflow - State Table spects of Digital Electronics Hex Dec Under D Hex Dec Over D fter Pulse # F 5, efore st E 4 D D 3 3 E 4 4 F 5 5 F Variable Modulus ounter The preload feature provides the ability to implement a counter of variable modulus. Such a counter with n stages plus the overflow stage may have any modulus between 2 and 2 n. The selection of the modulus is made by the choice of the value to be preloaded. If the modulus m is desired, the value to be preloaded will be 2 n m for an n stage counter. There will also have to be logic added to automatically reload the counter with the preload value every time the counter overflows. This logic will not be shown here. Table 25 and Figure 37 show the behavior of a modulo-5 counter with a periodic signal on In. Table 26 and Figure 38 illustrate a modulo-9 counter. November 4, Version.

37 hemistry 838 ounters Table 25 Modulo 5 ounter, Preload Value = spects of Digital Electronics Hex Dec Under D Over Hex Dec D fter Pulse # 4 4 efore st D 3 2 E 4 3 F F Preload immediately D 3 7 E 4 8 F F 4 4 Preload immediately D 3 2 E 4 3 F F 5 Mod5ounterTiming.cdr 28-Oct-24 IN D Over Figure 37 Modulo-5 ounter Timing November 4, Version.

38 hemistry 838 ounters Table 26 Modulo 9 ounter, Preload Value = 7 spects of Digital Electronics Hex Dec Under D Hex Dec Over D fter Pulse # efore st D 3 6 E 4 7 F 5 8 F Preload immediately D 3 5 E 4 6 F 5 7 F Preload immediately D 3 24 E 4 25 F 5 26 F November 4, Version.

39 hemistry 838 Mod5ounterTiming.cdr 28-Oct-24 ounters spects of Digital Electronics IN D Over Figure 38 Modulo-9 ounter Timing 6.5. Up/Down ounter Table 24 is the Table of States for a 4 stage binary counter with an additional stage to indicate when the counter rolls over or overflows. Included are not only the values for the i but also the i. Notice that as the i count up, the i.are counting down. This fact makes provides the basis for implementing a counter that will count either up or down. Figure 4 illustrates one approach to implement the desired counter. The signal Up selects whether i or i, will be presented at the outputs, Out i. The starting value is presented to the Preset i and Load is strobed. The circuit takes advantage of the 2-bit multiplexer that is shown in Figure 39. Table 27 is the table of states for the 2-it Multiplexer. areful inspection of Table 27 indicates that the behavior is completely described by the abbreviated table of states shown in Table 28 ounter_updn_2.cdr 2-Oct-24 Out Up Figure 39 2-it Digital Multiplexer November 4, Version.

40 hemistry 838 ounters spects of Digital Electronics Table it Multiplexer - Table of States 2 3 Out Table it Multiplexer - Table of States (bbreviated) Out ounter_updn.cdr -Oct-24 Out Out Out Out D OverUnder Up Set Set Set Set Set Over IN lock lock lock lock lock lear lear lear lear lear Under Load Preset Preset Preset Preset D D Figure 4 - Simple Up/Down ounter OverFlow November 4, Version.

41 hemistry REVISION HISTORY REVISION HISTORY spects of Digital Electronics Revision History for spects of Digital Electronics Version Date uthors Description. 2-Oct-24 T V tkinson This document is the transcription of my lecture notes as distilled over 3 decades of EM 838. This is the first edition of the material in this form.. 4-Nov-24 T V tkinson dded the variable modulus and up/down counters. November 4, Version.