6.0.2 V-Series High Power IPMs. The V-Series IPM was developed in order to address newly emerging. Table 6.1 Powerex Intelligent Power Modules

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1 6. Introduction to Intellimod Intelligent Power Modules Powerex Intellimod Intelligent Power Modules (IPMs) are advanced hybrid power devices that combine high speed, low loss IGBTs with optimized gate drive and protection circuitry. Highly effective over-current and shortcircuit protection is realized through the use of advanced current sense IGBT chips that allow continuous monitoring of power device current. System reliability is further enhanced by the IPM s integrated over temperature and under voltage lock out protection. Compact, automatically assembled Intelligent Power Modules are designed to reduce system size, cost, and time to market. Powerex in alliance with Mitsubishi Electric introduced the first full line of Intelligent Power Modules in November, 99. Continuous improvements in power chip, packaging, and control circuit technology have lead to the Intellimod lineup shown in Table Third Generation Intelligent Power Modules The Powerex/Mitsubishi third generation intelligent power module family shown in Table 6. represents the industries most complete line of IPMs. Since their original introduction in 993 the series has been expanded to include 36 types with ratings ranging from A 6V to 8A V. The power semiconductors used in these modules are based on the field proven H-Series IGBT and diode processes. In Table 6. the third generation family has been divided into two groups, the Low Profile Series and High Power Series based on the packaging technology that is used. The third generation IPM has been optimized for minimum switching losses in order to meet industry demands for acoustically noiseless inverters with carrier frequencies up to Hz. The built in gate drive and protection has been carefully designed to minimize the components required for the user supplied interface circuit. 6.. V-Series High Power IPMs The V-Series IPM was developed in order to address newly emerging Table 6. Powerex Intelligent Power Modules Third Generation Low Profile Series - 6V PMCSJ6 Six IGBTs PM5CSJ6 5 Six IGBTs PMCSJ6 Six IGBTs PM3CSJ6 3 Six IGBTs PM5RSK6 5 Six IGBTs Brake ckt. PM75RSK6 75 Six IGBTs Brake ckt. Third Generation Low Profile Series - V PMCZF Six IGBTs PMRSH Six IGBTs Brake ckt. PM5CZF 5 Six IGBTs PM5RSH 5 Six IGBTs Brake ckt. PM5RSK 5 Six IGBTs Brake ckt. Third Generation High Power Series - 6V PM75RSA6 75 Six IGBTs Brake ckt. PMCSA6 Six IGBTs PMRSA6 Six IGBTs Brake ckt. PM5CSA6 5 Six IGBTs PM5RSA6 5 Six IGBTs Brake ckt. PMCSA6 Six IGBTs PMRSA6 Six IGBTs Brake ckt. PMDSA6 Two IGBTs: Half Bridge PM3DSA6 3 Two IGBTs: Half Bridge PM4DAS6 4 Two IGBTs: Half Bridge PM6DSA6 6 Two IGBTs: Half Bridge PM8HSA6 8 One IGBT industry requirements for higher reliability, lower cost and reduced EMI. By utilizing the low inductance packaging technology developed for the U-Series IGBT module (described in Section 4..5) combined with an advanced super soft free-wheel diode and optimized gate drive and protection circuits the V-Series IPM family achieves improved performance at reduced cost. The detailed descriptions of IPM operation and interface requirements presented in Sections 6. through 6.8 apply to V-Series as well as third generation IPMs. The only exception being that V-Series IPMs have a unified short circuit protection function that Type Number Amps Power Circuit Type Number Amps Power Circuit Third Generation High Power Series - V PM5RSB 5 Six IGBTs Brake ckt. PM5RSA 5 Six IGBTs Brake ckt. PM75CSA 75 Six IGBTs PM75DSA 75 Two IGBTs: Half Bridge PMCSA Six IGBTs PMDSA Two IGBTs: Half Bridge PM5DSA 5 Two IGBTs: Half Bridge PMDSA Two IGBTs: Half Bridge PM3DSA 3 Two IGBTs: Half Bridge PM4HSA 4 One IGBT PM6HSA 6 One IGBT PM8HSA 8 One IGBT V-Series High Power - 6V PM75RVA6 75 Six IGBTs Brake ckt. PMCVA6 Six IGBTs PM5CVA6 5 Six IGBTs PMCVA6 Six IGBTs PM3CVA6 3 Six IGBTs PM4DVA6 4 Two IGBTs: Half Bridge PM6DVA6 6 Two IGBTs: Half Bridge V-Series High Power - V PM5RVA 5 Six IGBTs Brake ckt. PM75CVA 75 Six IGBTs PMCVA Six IGBTs PM5CVA 5 Six IGBTs PMDVA Two IGBTs: Half Bridge PM3DVA 3 Two IGBTs: Half Bridge A-7

2 takes the place of the separate short circuit and over current functions described in Sections and The unified protection was made possible by an advanced RTC (Real Time Control) current clamping circuit that eliminates the need for the over current protection function. In V-Series IPMs a unified short circuit protection with a delay to avoid unwanted operation replaces the over current and short circuit modes of the third generation devices. 6. Structure of Intelligent Power Modules multilayer epoxy based isolation system. In this system, alternate layers of copper and epoxy are used to create a shielded printed circuit directly on the aluminum base plate. Power chips and gate control circuit components are Figure 6. Power Circuit Configuration TYPE C P U V W soldered directly to the substrate eliminating the need for a separate printed circuit board and ceramic isolation materials. Modules constructed using this technique are easily identified by their extremely low profile packages. This package design is ideally suited for consumer and industrial applications where low cost and compact size are important. Figure 6. shows a cross section of this type of Intellimod package. Figure 6.3 is a PMCSJ6 A, 6V Intellimod. Figure 6. Multilayer Epoxy Construction Powerex Intelligent Power Modules utilize many of the same field proven module packaging technologies used in Powerex IGBT modules. Cost effective implementation of the built in gate drive and protection circuits over a wide range of current ratings was achieved using two different packaging techniques. Low power devices use a multilayer epoxy isolation system while medium and high power devices use ceramic isolation. These packaging technologies are described in more detail in Sections 6.. and 6... Intellimods are available in four power circuit configurations, single (H), dual (D), six pack (C), and seven pack (R). Table 6. indicates the power circuit of each Intellimod and Figure 6. shows the power circuit configurations. N TYPE R P N TYPE D B C U V TYPE H C W Case. Epoxy Resin 3. Input Signal Terminal 4. SMT Resistor 5. Gate Control IC 6. SMT Capacitor 7. IGBT Chip 8. Free-wheel Diode Chip 9. Bond Wire. Copper Block. Baseplate with Epoxy Based Isolation Figure 6.3 PMCSJ Multilayer Epoxy Construction CE E Low power Intellimods (-5A, 6V and -5A, V) use a E A-73

3 6.. Ceramic Isolation Construction Higher power IPMs are constructed using ceramic isolation material. A direct bond copper process in which copper patterns are bonded directly to the ceramic substrate without the use of solder is used in these modules. This substrate provides the improved thermal characteristics and greater current carrying capabilities that are needed in these higher power devices. Gate drive and control circuits are contained on a separate PCB mounted directly above the power devices. The PCB is a multilayer construction with special shield layers for EMI noise immunity. Figure 6.4 shows the structure of a ceramic isolated Intelligent Power Module. Figure 6.5 is a PM75RSA6 75 A, 6V Intellimod. Figure 6.4 CASE BASE PLATE Ceramic Isolation Construction SILICON GEL SILICON CHIP DBC PLATE MAIN TERMINAL SHIELD LAYER EPOXY RESIN CONTROL BOARD PCB RESISTOR SHIELD LAYER SIGNAL TRACE GUIDE PIN INPUT SIGNAL TERMINAL INTERCONNECT ELECTRODE TERMINAL ALUMINUM WIRE Figure 6.5 PM75RSA6 A-74

4 6..3 V-Series IPM Construction V-Series IPMs are similar to the ceramic isolated types described in Section 6.. except that an insert molded case similar to the U-Series IGBT is used. Like the U-Series IGBT described in Section 4..5, the V-Series IPM has lower internal inductance and improved power cycle durability. Figure 6.6 is a cross section drawing showing the construction of the V-Series IPM. The insert molded case makes the V-Series IPM is easier to manufacture and lower in cost. Figure 6.7 shows a PM5CVA which is a 5A V V-Series IPM Advantages of Intelligent Power Module Intellimod Intelligent Power Module products were designed and developed to provide advantages to OEMs by reducing design, development, and manufacturing costs as well as providing improvement in system performance and reliability over conventional IGBTs. Design and development effort is simplified and successful drive coordination is assured by the integration of the drive and protection circuitry directly into the IPM. Reduced time to market is only one of the additional benefits of using an IPM. Others include increased system reliability through automated IPM assembly and test and reduction in the number of components that must be purchased, stored, and assembled. Often the system size can be reduced through smaller heatsink requirements as a result of lower on-state and switching losses. All IPMs use the same standardized gate control interface with logic level control circuits allowing extension of the product line without additional drive circuit design. Finally, the ability of the IPM to self protect in fault situations reduce the chance of device destruction during development testing as well as in field stress situations. 6. IPM Ratings and Characteristics IPM datasheets are divided into three sections: Maximum Ratings Characteristics (electrical, thermal, mechanical) Recommended Operating Conditions The limits given as maximum rating must not be exceeded under any circumstances, otherwise destruction of the IPM may result. Key parameters needed for system design are indicated as electrical, thermal, and mechanical characteristics. The given recommended operating conditions and application circuits should be considered as a preferable design guideline fitting most applications. Figure 6.6 V-Series IPM Construction Figure 6.7 PM5CVA SILICONE GEL POWER TERMINALS COVER SIGNAL TERMINALS INSERT MOLD CASE PRINTED CIRCUIT BOARD ALUMINUM BOND WIRES DBC AIN CERAMIC SUBSTRATE BASE PLATE SILICON CHIPS A-75

5 6.. Maximum Ratings Symbol Parameter Definition Inverter Part V CC Supply Voltage Maximum DC bus voltage applied between P-N V CES Collector-Emitter Voltage Maximum off-state collector-emitter voltage at applied control input off signal ±I C Collector-Current Maximum DC collector and FWDi T j 5 C ±I CP Collector-Current (peak) Maximum peak collector and FWDi T j 5 C P C Collector Dissipation Maximum power dissipation per IGBT switch at T j = 5 C T j Junction Temperature Range of IGBT junction temperature during operation Brake Part V R(DC) FWDi Reverse Voltage Maximum reverse voltage of FWDi I F FWDi Forward Current Maximum FWDi DC current at T j 5 C Control Part V D Supply Voltage Maximum control supply voltage V CIN Input Voltage Maximum voltage between input (I) and ground (C) pins V FO Fault Output Supply Voltage Maximum voltage between fault output (FO) and ground (C) pins I FO Fault Output Current Maximum sink current of fault output (FO) pin Total System V CC(prot) Supply Voltage Protected Maximum DC bus voltage applied between P-N with guaranteed OC and SC protection by OC & SC T C Module Case Operating Range of allowable case temperature at specified reference point during operation Temperature T stg Storage Temperature Range of allowable ambient temperature without voltage or current V iso Isolation Voltage Maximum isolation voltage (AC 6Hz min.) between baseplate and module terminals (all main and signal terminals externally shorted together) 6.. Thermal Resistance Symbol Parameter Definition R th(j-c) Junction to Case Maximum value of thermal resistance between junction and case per switch Thermal Resistance R th(c-f) Contact Thermal Maximum value of thermal resistance between case and fin (heatsink) per IGBT/FWDi pair Resistance with thermal grease applied according to mounting recommendations 6..3 Electrical Characteristics Symbol Parameter Definition Inverter and Brake Part V CE (SAT) Collector-Emitter IGBT on-state voltage at rated collector current under specified conditions Saturation Voltage V EC FWDi Forward Voltage FWDi forward voltage at rated current under specified conditions t on Turn-on Time t rr FWDi Recovery Time Inductive load switching times under rated conditions t c(on) Turn-on Crossover Time (See Figure 6.) t off Turn-off Time t c(off) Turn-off Crossover Time I CES Collector-Emitter Cutoff Collector-Emitter current in off-state at V CE = V CES under specified conditions A-76

6 6..3 Electrical Characteristics (continued) Symbol Parameter Definition Control Part V D Supply Voltage Range of allowable control supply voltage in switching operation I D Circuit Current Control supply current in stand-by mode V CIN(on) Input ON-Voltage A voltage applied between input (I) and ground (C) pins less than this value will turn on the IPM V CIN(off) Input OFF-Voltage A voltage applied between input (I) and ground (C) pins higher than this value will turn off the IPM f PWM PWM Input Frequency Range of PWM frequency for VVVF inverter operations t DEAD Arm Shoot Through Time delay required between high and low side input off/on signals to prevent an Blocking Time arm shoot through OC Over-Current Trip Level Collector that will activate the over-current protection SC Short-Circuit Trip Level Collector current that will activate the short-circuit protection t off(oc) Over-Current Delay Time Time delay after collector current exceeds OC trip level until OC protection is activated OT Over-Temperature Trip Level Baseplate temperature that will activate the over-temperature protection OT r Over-Temperature Temperature that the baseplate must fall below to reset an over-temperature fault Reset Level UV Control Supply Control supply voltage below this value will activate the undervoltage protection Undervoltage Trip Level UV r Control Supply Control supply voltage that must exceed to reset an undervoltage fault Undervoltage Reset Level I FO(H) Fault Output Inactive Current Fault output sink current when no fault has occurred I FO(L) Fault Output Active Current Fault Output sink current when a fault has occurred t FO Fault Output Pulsed Width Duration of the generated fault output pulse V SXR SXR Terminal Output Voltage Regulated power supply voltage on SXR terminal for driving the external optocoupler 6..4 Recommended Operation Conditions Symbol Parameter Definition V CC Main Supply Voltage Recommended DC bus voltage range V D Control Supply Voltage Recommended control supply voltage range V CIN(on) Input ON-Voltage Recommended input voltage range to turn on the IPM V CIN(off) Input OFF-Voltage Recommended input voltage range to turn off the IPM f PWM PWM Input Frequency Recommended range of PWM carrier frequency using the recommended application circuit t DEAD Arm Shoot Through Recommended time delay between high and low side off/on signals to the optocouplers Blocking Time using the recommended application circuit 6..5 Test Circuits and Conditions The following test circuits are used to evaluate the IPM characteristics. Figure 6.8 V CE (SAT) Test Figure 6.9 V EC Test C(C) C(C). V CE (SAT) and V EC To ensure specified junction temperature, T j, measurements of V CE (SAT) and V EC must be performed as low duty factor pulsed tests. (See Figures 6.8 and 6.9) V D VX SXR CX VXC V I C E(E) V D VX SXR CX VXC V I C E(E) A-77

7 . Half-Bridge Test Circuit and Switching Time Definitions. Figure 6. Half-bridge Test Circuit and Switching Time Definitions Figure 6. shows the standard half-bridge test circuit and switching waveforms. Switching times and FWDi recovery characteristics are defined as shown in this figure. V D V D OFF SIGNAL ON PULSE INTEGRATED GATE CONTROL CIRCUIT INTEGRATED GATE CONTROL CIRCUIT V CE I C V CC 3. Overcurrent and Short-Circuit Test t rr I trip levels and timing specifications in short circuit and overcurrent are defined as shown in Figure 6.. By using a fixed load resistance the supply voltage, V CC, is gradually increased until OC and SC trip levels are reached. I CIN td (on) % t c (on) 9% tr I rr I C t c (off) td (off) 9% % tf V CE I C Precautions: A. Before applying any main bus voltage, V CC, the input terminals should be pulled up by resistors to their corresponding control supply (or SXR) pin, each input signal should be kept in OFF state, and the control supply should be provided. After this, the specified ON and OFF level for each input signal should be applied. The control supply should also be applied to the non-operating arm of the module under test and inputs of these arms should be kept to their OFF state. B. When performing OC and SC tests the applied voltage, V CC, must be less than V CC(prot) and the turn-off surge voltage spike must not be allowed to rise above the V CES rating of the device. (These tests must not be attempted using a curve tracer.) Figure 6. ON PULSE SC OC I C SC OC I C SC OC I C V C (t on = td (on) tr) ON PULSE t off (OC) (t off = td (off) tf) Over-current and Short Circuit Test Circuit INTEGRATED GATE CONTROL CIRCUIT R* I C V CC * R IS SIZED TO CAUSE SC AND OC CONDITIONS INPUT SIGNAL NORMAL OPERATION OVER CURRENT SHORT CIRCUIT A-78

8 6.3 Area of Safe Operation for Intelligent Power Modules The Intellimod s built-in gate drive and protection circuits protect it from many of the operating modes that would violate the Safe Operation Area (SOA) of nonintelligent IGBT modules. A conventional SOA definition that characterizes all possible combinations of voltage, current, and time that would cause power device failure is not required. In order to define the SOA for IPMs, the power device capability and control circuit operation must both be considered. The resulting easy to use short circuit and switching SOA definitions for Intelligent Power Modules are summarized in this section Switching SOA Switching or turn-off SOA is normally defined in terms of the maximum allowable simultaneous voltage and current during repetitive turn-off switching operations. In the case of the IPM the built-in gate drive eliminates many of the dangerous combinations of voltage and current that are caused by improper gate drive. In addition, the maximum operating current is limited by the over current protection circuit. Given these constraints the switching SOA can be defined using the waveform shown in Figure 6.. This waveform shows that the IPM will operate safely as long as the DC bus voltage is below the data sheet V CC(prot) specification, the turn-off transient voltage across C-E terminals of each IPM switch is maintained below the V CES specification, T j is less than 5 C, and the control power supply voltage is between 3.5V and 6.5V. In this waveform I OC is the maximum current that the IPM will allow without causing an Over Current (OC) fault to occur. In other words, it is just below the OC trip level. This waveform defines the worst case for hard turn-off operations because the IPM will initiate a controlled slow shutdown for currents higher than the OC trip level Short Circuit SOA The waveform in Figure 6.3 depicts typical short circuit operation. The standard test condition uses a minimum impedance short circuit which causes the maximum short circuit current to flow in the device. In this test, the short circuit current (I SC ) is limited only by the device characteristics. The IPM is guaranteed to survive nonrepetitive short circuit and over current conditions as long as the initial DC bus voltage is less than the V CC(prot) specification, all transient voltages across C-E terminals of each IPM switch are maintained less than the V CES specification, T j is less than 5 C, and the control supply voltage is Figure 6. Turn-off Waveform I OC V CES V CC(PROT) between 3.5V and 6.5V. The waveform shown depicts the controlled slow shutdown that is used by the IPM in order to help minimize transient voltages. Note: The condition V CE V CES has to be carefully checked for each IPM switch. For easing the design another rating is given on the data sheets, V CC(surge), i.e., the maximum allowable switching surge voltage applied between the P and N terminals Active Region SOA Like most IGBTs, the IGBTs used in the IPM are not suitable for linear or active region operation. Normally device capabilities in this mode of operation are described in terms of FBSOA (Forward Biased Safe Operating Area). The IPM s internal gate drive forces the IGBT to operate with a gate voltage of either zero for the off state or the control supply voltage (V D ) for the on state. The IPMs under-voltage lock out prevents any possibility of active or linear operation by automatically turning the power device off if V D drops to a level that could cause desaturation of the IGBT. Figure 6.3 I SC t off(oc) Short Circuit Operation V CES V CES V CC(PROT) A-79

9 6.4. IPM Self Protection 6.4. Self Protection Features The operation and timing of each protection feature is described in Sections 6.4. through down and failure on the power device gate drive and fault output are shown. Intellimod Intelligent Power Modules have sophisticated built-in protection circuits that prevent the power devices from being damaged should the system malfunction or be over stressed. Our design and applications engineers have developed fault detection and shut down schemes that allow maximum utilization of power device capability without compromising reliability. Control supply under-voltage, overtemperature, over-current, and short-circuit protection are all provided by the IPM's internal gate control circuits. A fault output signal is provided to alert the system controller if any of the protection circuits are activated. Figure 6.4 is a block diagram showing the IPM's internally integrated functions. This diagram also shows the isolated interface circuits and control power supply that must be provided by the user. The internal gate control circuit requires only a simple 5V DC supply. Specially designed gate drive circuits eliminate the need for a negative supply to off bias the IGBT. The Intellimod 's control input is designed to interface with optocoupled transistors with a minimum of external components. Figure 6.4 IPM Functional Diagram INPUT SIGNAL FAULT OUTPUT ISOLATED POWER SUPPLY ISOLATING INTERFACE CIRCUIT ISOLATING INTERFACE CIRCUIT GATE CONTROL CIRCUIT GATE DRIVE OVER TEMP UV LOCK-OUT OVER CURRENT SHORT CIRCUIT 6.4. Control Supply Under-voltage Lock Out The Intelligent Power Module's internal control circuits operate from an isolated 5V DC supply. If, for any reason, the voltage of this supply drops below the specified under-voltage trip level (UV t ), the power devices will be turned off and a fault signal will be generated. Small glitches less than the specified t duv in length will not affect the operation of the control circuitry and will be ignored by the under-voltage protection circuit. In order for normal operation to resume, the supply voltage must exceed the under-voltage reset level (UV r ). Operation of the undervoltage protection circuit will also occur during power up and power down of the control supply. This operation is normal and the system controller's program should take the fault output delay (t fo ) into account. Figure 6.5 is a timing diagram showing the operation of the under-voltage lock-out protection circuit. In this diagram an active low input signal is applied to the input pin of the Intellimod by the system controller. The effects of control supply power up, power INTELLIGENT POWER MODULE SENSE CURRENT TEMPERATURE SENSOR CURRENT SENSE IGBT COLLECTOR EMITTER Caution:. Application of the main bus voltage at a rate greater than V/µs before the control power supply is on and stabilized may cause destruction of the power devices.. Voltage ripple on the control power supply with dv/dt in excess of 5V/µs may cause a false trip of the UV lock-out Over-temperature Protection The Intelligent Power Module has a temperature sensor mounted on the isolating base plate near the IGBT chips. If the temperature of the base plate exceeds the overtemperature trip level (OT) the Intellimod s internal control circuit will protect the power devices by disabling the gate drive and ignoring the control input signal until the over temperature condition has subsided. In six and seven pack modules all three low side devices will be turned off and a low side fault signal will be generated. High side switches are unaffected and can still be turned on and off by the system controller. Similarly, in dual type modules only the low side device is disabled. The fault output will remain as long as the over-temperature condition exists. When the temperature falls below the over-temperature reset level (OT r ), and the control input is high (off-state) the power device will be enabled and normal operation will resume at the next low (on) input signal. Figure 6.6 is a timing A-8

10 diagram showing the operation of the over-temperature protection circuit. The over temperature function provides effective protection against overloads and cooling system failures in most applications. However, it does not guarantee that the maximum junction temperature rating of the IGBT chip will never be exceeded. In cases of abnormally high losses such as failure of the system controller to properly regulate current or excessively high switching frequency it is possible for IGBT chip to exceed T j(max) before the base plate reaches the OT trip level. initiated and a fault output is generated. The controlled shutdown lowers the turn-off di/dt which helps to control transient voltages that can occur during shut down from high fault currents. Most Intelligent Modules use the two step shutdown depicted in Figure 6.7. In the two step shutdown, the gate voltage is reduced to an intermediate voltage Figure 6.5 INPUT SIGNAL CONTROL SUPPLY VOLTAGE UV r UV t Operation of Under-Voltage Lockout causing the current through the device to drop slowly to a low level. Then, about 5µs later, the gate voltage is reduced to zero completing the shut down. Some of the large six and seven pack IPMs use an active ramp of gate voltage to achieve the desired reduction in turn off di/dt under high fault currents. The oscillographs in Figure 6.8 illustrate the effect of Caution: Tripping of the over-temperature protection is an indication of stressful operation. Repetitive tripping should be avoided Over-current Protection FAULT OUTPUT CURRENT (I FO) INTERNAL GATE VOLTAGE V GE t FO t duv t FO t duv The IPM uses current sense IGBT chips to continuously monitor power device current. If the current though the Intelligent Power Module exceeds the specified overcurrent trip level (OC) for a period longer than t off(oc) the IPMs internal control circuit will protect the power device by disabling the gate drive and generating a fault output signal. The timing of the over-current protection is shown in Figure 6.7. The t off(oc) delay is implemented in order to avoid tripping of the OC protection on short pulses of current above the OC level that are not dangerous for the power device. When an over-current is detected a controlled shutdown is Figure 6.6 INPUT SIGNAL BASE PLATE TEMPERATURE (Tb) FAULT OUTPUT CURRENT (I FO) INTERNAL GATE VOLTAGE V GE CONTROL SUPPLY ON Operation of Over-Temperature OT OT r SHORT GLITCH IGNORED POWER SUPPLY FAULT AND RECOVERY CONTROL SUPPLY OFF A-8

11 the controlled shutdown (for obtaining the oscillograph in A the internal soft shutdown was intentionally deactivated). The Intellimod uses actual device current measurement to detect all types of over current conditions. Even resistive and inductive shorts to ground that are often missed by conventional desaturation and bus current sensing protection schemes will be detected by the Intellimod s current sense IGBTs. Note: V-Series IPMs do not have an overcurrent protection function. Instead a unified short circuit protection function that has a delay like the over current protection described in this section is used. Figure 6.7 Operation of Over-Current and Short Circuit Protection INPUT SIGNAL INTERNAL GATE VOLTAGE (V GE) SHORT CIRCUIT TRIP LEVEL t off (OC) t hold t hold OVER CURRENT TRIP LEVEL COLLECTOR CURRENT I FO FAULT OUTPUT CURRENT t FO t FO NORMAL OPERATION FWD RECOVERY CURRENT IGNORED BY OC PROTECTION OVER CURRENT FAULT AND RECOVERY SHORT CIRCUIT FAULT AND RECOVERY NORMAL OPERATION Figure 6.8 OC Operation of PMDSA6 (I C : A/div; V/div; t: µs/div) OC PROTECTION WITHOUT SOFT SHUTDOWN OC PROTECTION WITH SOFT SHUTDOWN V CE (surge) V CE (surge) I C V CE I C V CE A-8

12 6.4.5 Short Circuit Protection If a load short circuit occurs or the system controller malfunctions causing a shoot through, the Intellimod s built in short circuit protection will prevent the IGBTs from being damaged. When the current, through the IGBT exceeds the short circuit trip level (SC), an immediate controlled shutdown is initiated and a fault output is generated. The same controlled shutdown techniques used in the over current protection are used to help control transient voltages during short circuit shut down. The short circuit protection provided by the Intellimod uses actual current measurement to detect dangerous conditions. This type of protection is faster and more reliable than conventional out-of-saturation protection schemes. Figure 6.7 is a timing diagram showing the operation of the short circuit protection. To reduce the response time between SC detection and SC shutdown, a real time current control circuit (RTC) has been adopted. The RTC bypasses all but the final stage of the IGBT driver in SC operation thereby reducing the response time to less than ns. The oscillographs in Figure 6.9 illustrate the effectiveness of the RTC technique by comparing short circuit operation of second generation IPM (without RTC) and third generation IPM (with RTC). A significant improvement can be seen as the power stress is much lower as the time in short circuit and the magnitude of the short circuit current are substantially reduced. Note: The short circuit protection in V-Series IPMs has a delay similar to the third generation over current protection function described in The need for a quick trip has been eliminated through the use of a new advanced RTC circuit. Caution:. Tripping of the over current and short circuit protection indicates stressful operation of the IGBT. Repetitive tripping must be avoided.. High surge voltages can occur during emergency shutdown. Low inductance buswork and snubbers are recommended. Figure 6.9 Waveforms Showing the Effect of the RTC Circuit SHORT CIRCUIT OPERATION WITHOUT RTC CIRCUIT A, 6V, IPM VCE T T IC SHORT CIRCUIT OPERATION WITH RTC CIRCUIT A, 6V, IPM VCE IC T T 8A IC=A/div, VCE=V/div, t=µs/div 4A IC=A/div, VCE=V/div, t=µs/div 6.5 IPM Selection There are two key areas that must be coordinated for proper selection of an IPM for a particular inverter application. These are peak current coordination to the IPM overcurrent trip level and proper thermal design to ensure that peak junction temperature is always less than the maximum junction temperature rating (5 C) and that the baseplate temperature remains below the over-temperature trip level Coordination of OC Trip Peak current is addressed by reference to the power rating of the motor. Tables 6., 6.3 and 6.4 give recommended IPM types derived from the OC trip level and the peak motor current requirement based on several assumptions for the inverter and motor operation regarding efficiency, power factor, maximum overload, and current ripple. For the purposes of this table, the maximum motor current is taken from the NEC table. This already includes the motor efficiency and power factor appropriate to the particular motor size. Peak inverter current is then calculated using this RMS current, a % overload requirement, and a % ripple factor. An IPM is then selected which has a minimum overcurrent trip level that is above this calculated peak operating requirement. A-83

13 Table 6. Motor Rating vs. OC Protection (3 VAC Line) Current Motor Rating (HP) NEC Current Rating A(RMS) Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A) PMCSJ PMCSJ PM5CSJ PM5CSJ PMCSJ PM3CSJ6, PM3RSF PM5RSA6, PM5RSK PM75RSA6, PM75RSK PM75RSA6, PM75RSK PMCSA6, PMRSA PM5CSA6, PM5RSA PMCSA6, PMRSA6, 3 PMDSA6 x PMCSA6, PMRSA6, 3 PMDSA6 x PM3DSA6 x PM4DSA6 x PM6DSA6 x PM6DSA6 x PM8HSA6 x6 - From NEC Table 43-5 * - Inverter peak current is based on % overload requirement and a % current ripple factor. Table 6.3 Motor Rating vs. OC Protection (46 VAC Line) Current Motor Rating (HP) NEC Current Rating A(RMS) Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A) PMRSH, PMCZF PMRSH, PMCZF PMRSH, PMCZF PMRSH, PMCZF PMRSH, PMCZF PM5RSH, PM5CZF PM5RSB, PM5RSK PM5RSA PM5RSA PM75CSA, PM75DSA x PM75CSA, PM75DSA x PMCSA, PMDSA x PMCSA, PMDSA x PM5DSA x PMDSA x PM3DSA x PM3DSA x PM4HSA x PM6HSA x PM6HSA x PM8HSA x PM8HSA x6 6 - From NEC Table 43-5 * - Inverter peak current is based on % overload requirement and a % current ripple factor. A-84

14 Table 6.4 Motor Rating vs. SC Protection for V-Series IPMs Current Motor Rating (HP) NEC Current Rating A(RMS) Inverter Peak Current (A)* Applicable IPM Minimum SC Trip (A) 4VAC Line 8 95 PM75RVA PMCVA PM5CVA PMCVA PM3CVA PM4DVA PM6DVA6 46VAC Line 4 48 PM5RVA PM75CVA PMCVA PM5CVA 5 65 PMDVA PM3DVA 38 - From NEC Table 43-5 * - Inverter peak current is based on % overload requirement and a % current ripple factor Estimating Losses Once the coordination of the OC trip with the application requirements has been established the next step is determining the cooling system requirements. Section 3.4 provides a general description of the methodology for loss estimation and thermal system design. Figure 6. shows the total switching energy (E SW(on) E SW(off) ) versus I C for all third generation IPMs. Figure 6. shows total switching energy versus I C for V-Series IPMs. A detailed explanation of these curves and their use can be found in Section Figures 6. through 6.34 show simulation results calculating total power loss (switching and conduction) per arm in a sinusoidal output PWM inverter application using V-Series IPMs. Figure 6. Switching Energy vs. I C for Third Generation IPMs SWITCHINTG DISSIPATION, (mj/pulse) 3 CONDITIONS: INDUCTIVE LOAD SWITCHING OPERATION T j = 5 o C V CC = / V CES V D = 5V V SERIES 6V SERIES SWITCHING DISSIPATION = TURN-ON DISSIPATION TURN-OFF DISSIPATION COMPATIBLE I C RANGE: RATED I C. ~ COLLECTOR CURRENT, I C, (AMPERES) APPLICABLE TYPES: THIRD-GENERATION IPM PMDSA6, PM3DSA6, PM4DSA6, PM6DSA6, PM75DSA, PMDSA, PM5DSA, PMDSA, PM3DSA, PMCSA6, PM5CSA6, PMCSA6, PM75CSA, PMCSJ6, PMCSA, PMCSJ6, PM3CSJ6, PM3RSF6, PM5CSJ6, PM5RSA6, PM5RSK6, PM75RSA6, PMRSA6, PM5RSA6, PMRSH, PM5RSH, PM5RSB, PM5RSA A-85

15 Figure 6. Figure 6. Power Loss Simulation of SWITCHING ENERGY, (mj/pulse) 3 SWITCHING ENERGY LOSS FOR V-SERIES IPMs CONDITIONS: INDUCTIVE LOAD T j = 5 o C V CC = / V CES V D = 5V V SERIES 6V SERIES E SW (ON) E SW (OFF) COMPATIBLE I C RANGE: RATED I C. ~ COLLECTOR CURRENT, I C, (AMPERES) P(W) PM75RVA6 (Typ.) V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS I O (ARMS) Figure 6.3 P(W) V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS Power Loss Simulation of PMCVA6 (Typ.) I O (ARMS) Figure 6.4 Power Loss Simulation of PM5CVA6 (Typ.) Figure 6.5 Power Loss Simulation of PMCVA6 (Typ.) Figure 6.6 Power Loss Simulation of PM3CVA6 (Typ.) P(W) 5 5 V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS P(W) 5 5 V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS P(W) 5 5 V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS I O (ARMS) I O (ARMS) I O (ARMS) Figure 6.7 Power Loss Simulation of PM4DVA6 (Typ.) Figure 6.8 Power Loss Simulation of PM6DVA6 (Typ.) Figure 6.9 Power Loss Simulation of PM5RVA(Typ.) P(W) 5 5 V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS P(W) V CC = 3V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS P(W) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS I O (ARMS) I O (ARMS) I O (ARMS) A-86

16 Figure 6.3 P(W) Figure 6.3 P(W) Figure 6.34 P(W) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS Power Loss Simulation of PM75RVA (Typ.) I O (ARMS) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS Power Loss Simulation of PM5CVA (Typ.) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS I O (ARMS) Power Loss Simulation of PM3DVA (Typ.) I O (ARMS) Figure 6.3 P(W) Figure 6.33 P(W) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS Power Loss Simulation of PMCVA (Typ.) V CC = 6V V D = 5V T j = 5 C P.F. =.8 fc = khz DC LOSS SW LOSS TOTAL LOSS I O (ARMS) Power Loss Simulation of PMDVA (Typ.) I O (ARMS) 6.6 Controlling the Intelligent Power Module Intellimod Intelligent Power Modules are easy to operate. The integrated drive and protection circuits require only an isolated power supply and a low level on/off control signal. A fault output is provided for monitoring the operation of the modules internal protection circuits The Control Power Supply Depending on the power circuit configuration of the module one, two, or four isolated power supplies are required by the Intellimod s internal drive and protection circuits. In high power 3-phase inverters using single or dual type IPMs it is good practice to use six isolated power supplies. In these high current applications each low side device must have its own isolated control power supply in order to avoid ground loop noise problems. The control supplies should be regulated to 5V /-% in order to avoid over-voltage damage or false tripping of the under-voltage protection. The supplies should have an isolation voltage rating of at least two times the IPM s V CES rating (i.e. V iso = 4V for V module). The current that must be supplied by the control power supply is the sum of the quiescent current needed to power the internal control circuits and the current required to drive the IGBT gate. Table 6.5 summarizes the typical and maximum control power supply current requirements for third generation Intelligent Power A-87

17 Modules. Table 6.6 summarizes control supply requirements for V-Series IPMs. These tables give control circuit currents for the quiescent (not switching) state and for Hz switching. This data is provided in order to help the user design appropriately sized control power supplies. Power requirements for operating frequencies other than Hz can be determined by scaling the frequency dependent portion of the control circuit current. For example, to determine the maximum control circuit current for a PM3DSA operating at 7kHz the maximum quiescent control circuit current is subtracted from the maximum Hz control circuit current: 7mA 3mA = 4mA 4mA is the frequency dependent portion of the control circuit current for Hz operation. For 7kHz operation the frequency dependent portion is: 4mA x (7kHz Hz) = 4mA To get the total control power supply current required, the quiescent current must be added back: 3mA 4mA = 44mA 44mA is the maximum control circuit current required for a PM3DSA operating at 7kHz. Capacitive coupling between primary and secondary sides of isolated control supplies must be minimized as parasitic capacitances in excess of pf can cause noise that may trigger Table 6.5 Control Power Requirements for Third Generation IPMs (V D = 5V, Duty = 5%) ma N Side P Side (Each Supply) DC Hz DC Hz Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max. 6V Series PMCSJ PM5CSJ PMCSJ PM3CSJ PMCSA PM5CSA PMCSA PM3RSF PM5RSA PM5RSK PM75RSA PMRSA PM5RSA PMRSA PMDSA PM3DSA PM4DSA PM6DSA PM8HSA V SERIES PMRSH PMCZF PM5RSH PM5CZF PM5RSB PM5RSK PM5RSA PM75CSA PMCSA PM75DSA PMDSA PM5DSA PMDSA PM3DSA PM4HSA PM6HSA PM8HSA 3 4 A-88

18 Table 6.6 V-Series IPM Control Power Supply Current N Side the control circuits. An electrolytic or tantalum decoupling capacitor should be connected across the control power supply at the Intellimod s terminals. This capacitor will help to filter common noise on the control power supply and provide the high pulse currents required by the Intellimod s internal gate drive circuits. Isolated control power supplies can be created using a variety of techniques. Control power can be derived from the main input line using either a switching power supply with multiple outputs or a line frequency transformer with multiple secondaries. Control power supplies can also be derived from the main logic power supply using DC-to-DC converters. Using a compact DC-to-DC converter for each isolated supply can help to simplify the interface circuit layout. A distributed DC-to-DC converter in which a single oscillator is used to drive several small isolation P Side (Each Supply) DC Hz DC Hz Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max. 6V Series PM75RVA PMCVA PM5CVA PMCVA PM3CVA PM4DVA PM6DVA V SERIES PM5RVA PM75CVA PMCVA PM5CVA PMDVA PM3DVA transformers can provide the layout advantages of separate DC-to-DC converters at a lower cost. In order to simplify the design of the required isolated power supplies, Powerex has developed two DC-to-DC converter modules to work with the IPMs. The M57L is a high input voltage step down converter. When supplied with 3 to 4VDC the M57L will produce a regulated VDC output. The VDC can then be connected to the M574- to produce four isolated 5VDC outputs to power the IPMs control circuits. The M574- can also be used as a stand alone unit if VDC is available from another source such as the main logic power supply. Figure 6.35 shows an isolated interface circuit for a seven pack IPM using M574-. Figure 6.36 shows a complete high input voltage isolated power supply circuit for a dual type intelligent power module. Caution: Using bootstrap techniques is not recommended because the voltage ripple on VD may cause a false trip of the undervoltage protection in certain inverter PWM modes Interface Circuit Requirements The IGBT power switches in the Intellimod are controlled by a low level input signal. The active low control input will keep the power devices off when it is held high. Typically the input pin of the Intellimod is pulled high with a resistor connected to the positive side of the control power supply. An ON signal is then generated by pulling the control input low. The fault output is an open collector with its maximum sink current internally limited. When a fault condition occurs the open collector device turns on allowing the fault output to sink current from the positive side of the control supply. Fault and on/off control signals are usually transferred to and from the system controller using isolating interface circuits. Isolating interfaces allow high and low side control signals to be referenced to a common logic level. The isolation is usually provided by optocouplers. However, fiber optics, pulse transformers, or level shifting circuits could be used. The most important consideration in interface circuit design is layout. Shielding and careful routing of printed circuit wiring is necessary in order to avoid coupling of dv/dt noise into control circuits. Parasitic capacitance between high side A-89

19 Figure 6.35 Isolated Interface Circuit for Seven-Pack IPMs FO N 3 PC87 4 W N HCPL454. F F O 9 V N HCPL454. F W N V N 8 7 U N HCPL454. F 4.7k U N B R V NI B PC V NC 3 C W P FO WP HCPL454 3 PC87 4. F V WP W P W FO V WPC 9 C VIN F V P HCPL454. F V VP V P V FO C M574- FO VP 3 PC87 4 V VPC 5 U P HCPL454. F V UP U P 4 3 U FO C FO UP 3 PC87 4 V UPC V SEVEN PACK IPM NOTE: FOR C AND C SEE SECTION A-9

20 Figure 6.36 Isolated Interface Circuit for Dual Intelligent Power Modules 3-4 VDC. F M57L F 5V 33 F 5V VIN - P IN P FO N IN N FO HCPL454 3 PC HCPL454 3 PC k. F C. F 6.8k C I V () S R (5) C IN V C (-) F O V () S R (5) C IN V C (-) F O P N C M574- DUAL IPM interface circuits, high and low side interface circuits, or primary and secondary sides of the isolating devices can cause noise problems. Careful layout of control power supply and isolating circuit wiring is necessary. The following is a list of guidelines that should be followed when designing interface circuits. Figure 6.37 shows an example interface circuit layout for dual type IPMs. Figure 6.38 shows an example interface circuit layout for a V-Series IPMs.The shielding and printed circuit routing techniques used in this example are intended to illustrate a typical application of the layout guidelines. INTERFACE CIRCUIT LAYOUT GUIDELINES I. Maintain maximum interface isolation. Avoid routing printed circuit board traces from primary and secondary sides of the isolation device near to or above and below each other. Any layout that increases the primary to secondary capacitance of the isolating interface can cause noise problems. II. III. IV. Maintain maximum control power supply isolation. Avoid routing printed circuit board traces from UP, VP, WP, and N side supplies near to each other. High dv/dts exist between these supplies and noise will be coupled through parasitic capacitances. If isolated power supplies are derived from a common transformer interwinding capacitance should be minimized. Keep printed circuit board traces between the interface circuit and Intellimod short. Long traces have a tendency to pick up noise from other parts of the circuit. Use recommended decoupling capacitors for power supplies and optocouplers. Fast switching IGBT power circuits generate dv/dt and di/dt noise. Every precaution should be taken to protect the control circuits from coupled noise. V. Use shielding. Printed circuit board shield layers are helpful for controlling coupled dv/dt noise. Figure 6.37 shows an example of how the primary and secondary sides of the isolating interface can be shielded. VI. High speed optocouplers with high common mode rejection (CMR) should be used for signal input: t PLH,t PHL <.8µs CMR > V CM = 5V Appropriate optocoupler types are HCPL 453, HCPL 454 (Hewlett Packard) and PS4 (NEC). Usually high speed optos require a.µf decoupling capacitor close to the opto. VII. Select the control input pull-up resistor with a low enough value to avoid noise pick-up by the high impedance IPM input and with a high enough value that the high speed optotransistor can still pull the IPM safely below the recommended maximum V CIN(on). A-9

21 Figure 6.37 Interface Circuit Layout Example for Dual IPMs SHIELD GROUND TO V UPC U P F O - U N F O - U SHIELD GROUND TO V UNC SHIELD GROUND TO V VPC V P F O - V N F O - V SHIELD GROUND TO V VNC SHIELD GROUND TO V WPC W P F O - W N F O - W SHIELD GROUND TO V WNC DIGITAL GROUND MID-LAYER SHIELD U P V P W P TO CONTROL POWER SOURCE U N V N W N SHIELDS GROUND TO NEGATIVE SIDE OF EACH CONTROL POWER SUPPLY LEGEND TOP LAYER MIDDLE LAYER BOTTOM LAYER A-9

22 Figure 6.38 Interface Circuit Layout for a V-Series IPMs INTERFACE CIRCUIT IPM B P N U V W IPM PCB VIII.If some IPM switches are not used in actual application their control power supply must still be applied. The related signal input terminals should be pulled up by resistors to the control power supply (V D or V SXR ) to keep the unused switches safely in off-state. IX. Unused fault outputs must be tied high in order to avoid noise pick up and unwanted activation of internal protection circuits. Unused fault outputs should be connected directly to the 5V of local isolated control power supply Example Interface Circuits Intellimod Intelligent Power Modules are designed to use optocoupled transistors for control input and fault output interfaces. In most applications optocouplers will provide a simple and inexpensive isolated interface to the system controller. Figures 6.39 through 6.43 show example interface circuits for the four Intellimod power circuit configurations. These circuits use two types of optocoupled transistors. The control input on/off signals are transferred from the system controller using high speed optocoupled transistors. Usually high speed optos require a.µf film or ceramic decoupling capacitor connected near their V CC and GND pins. The value of the control input pull up resistor is selected low enough to avoid noise pick up by the high impedance input and high enough so that the high speed optotransistor with its relatively low current transfer ratio can still pull the input low enough to assure turn on. The circuits shown use a Hewlett Packard HCPL-454 optotransistor. This opto was chosen mainly for its high common mode transient immunity of 5,V/µs. For reliable operation in IGBT power circuits optocouplers should have a minimum common mode noise immunity of, V/µs. Low speed optocoupled transistors can be used for the fault output and brake input. Slow optos have the added advantages of lower cost and higher current transfer ratios. The example interface circuits use a Sharp PC87 low speed optocoupled transistor for the transfer of brake and fault signals. Like most low speed optos the PC87 does not have internal shielding. Some switching noise will be coupled through the opto. An RC filter with a time constant of about µs can be added to the opto s output to remove this noise. The Intellimod s.5ms long fault output signal will be almost unaffected by the addition of this filter. When designing interface circuits always follow the interface circuit layout guidelines given in Section A-93