L-Series Power Devices

Transcription

1 L-Series Power Devices Application Note

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3 Table of Contents Application Information 1.0 Introduction L-Series Intelligent Power Modules L-Series High Power IPMs L-Series Numbering System Definitions Structure Ceramic Isolation Construction Installing IPMs Application of Thermal Grease Example Thermal Impedance Considerations IPM Self Protection Self Protection Features Control Supply Under-voltage Lockout Over-temperature Protection Short-circuit Protection Controlling the Intelligent Power Module The Control Power Supply Interface Circuit Requirements Other IPM Connection Requirements Speed Shifting Gate Drive Example Interface Circuits Connecting the Interface Circuit Dead Time (t DEAD ) Using the fault signal IPM Inverter Examples Power Loss and Junction Temperature Calculations Development Kits for L-Series IPMs...23 iii

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5 1.0 Introduction to Intellimod Intelligent Power Modules Powerex Intelligent Power Modules (IPMs) are advanced hybrid power devices that combine high speed, low loss IGBTs with optimized gate drive and protection circuitry. Highly effective short-circuit protection is realized through the use of advanced current sense IGBT chips that allow continuous monitoring of power device current. System reliability is further enhanced by the IPM s integrated over-temperature and under-voltage lock out protection. Intelligent Power Modules are designed to reduce system size, cost, and time to market. Powerex in alliance with Mitsubishi Electric introduced the first full line of Intelligent Power Modules in November, Continuous improvements in power chip, packaging, and control circuit technology have lead to the L-Series IPM lineup shown in Table L-Series Intelligent Power Modules The Powerex/Mitsubishi L-Series Intelligent Power Module family shown in Table 1.1 represents the industry s most complete line of IPMs. The L-Series includes 37 types with ratings ranging from 25A to 450A for 1200V modules and 50A to 600A for 600V modules. The power semiconductors used in these 5th generation L-Series IPM modules are based on the field proven CSTBT IGBT and are the first IPMs to use the CSTBT technology. The L-Series has been optimized for minimum switching and conduction losses in order to meet industry demands for acoustically noiseless inverters with carrier frequencies up to 20kHz. The built in gate drive and protection have been carefully designed to minimize the components required for the user supplied interface circuit. 1.2 L-Series High Power IPMs The latest generation of IPM modules was developed in order to address newly emerging industry requirements for higher reliability, lower cost, and reduced EMI. By utilizing the low inductance packaging technology developed for the U-Series IGBT module combined with an advanced super soft freewheel diode and optimized gate drive and protection circuits the L-Series IPM family achieves improved performance and compact size at reduced cost. Table 1.1 L-Series Intelligent Power Modules 1.3 L-Series Numbering System PM 75 R L A 120 (1) (2) (3) (4) (5) (6) (1) Device: PM = INTELLIMOD TM (IPM) (2) Current Rating: I C (Amperes) (3) Power Transistors: C = 6-PAC R = 7-PAC (6-PAC Brake) (4) Device Series: L = L-Series (5) Package: A = Screw Power Terminals B = Pin Power Terminals (6) Voltage: V CES Volts (x10) Part Number Current (A) Voltage (V) Brake Current (A) PM50(#)L(*) PM75(#)L(*) PM100(#)LA PM150(#)LA PM200(#)LA PM300(#)LA PM450CLA NA PM600CLA NA PM25(#)L(*) PM50(#)L(*) PM75(#)L(*) PM100(#)LA PM150(#)LA PM200CLA NA PM300CLA NA PM450CLA NA (*) Package Options: B = Solder Pin, A = Screw Terminal (#) Circuit Options: R = 7-PAC (6-PAC Brake), C = 6-PAC Example: PM75RLA060 is a 75A, 600V, 7-PAC (6-PAC Brake) with Screw Terminals. 1

6 2.0 Definitions The tables in this section describe most of the terms that will be found in this application note and on the IPM datasheets. Table 2.1 gives definitions to the general symbols. Table 2.2 gives the definitions to the symbols that are used on the Absolute Maximum Rating section of the device datasheets while Table 2.3 defines the symbols used in the Electrical Characteristics portion of the datasheets. Table 2.1 General Definitions Symbol Parameter Definition IGBT Insulated Gate Bipolar Transistor FWDi Free-wheeling Diode Anti-parallel to the IGBT IPM Intelligent Power Module t DEAD Dead Time Low side turn-off to high side turn-on and high side turn-off to low side turn-on IPM Motor Interior Permanent Magnet Motor (PC) Photo-coupler PC Programmable Controller CMR Common Mode Noise Rejection Maximum rise ratio to common mode voltage CM H Maximum rise ratio of common mode voltage at the specific high level CM L Maximum rise ratio of common mode voltage at the specific low level CTR Current Transfer Ratio Ratio of the output current to the Input current T a Ambient Temperature Atmosphere temperature without being subject to thermal source T C Case Temperature Case temperature measured at specified point Table 2.2 Absolute Maximum Ratings Definitions Symbol Parameter Definition V CES Collector-Emitter Blocking Voltage Maximum off-state collector-emitter voltage with gate-emitter shorted I C Continuous Collector Current Maximum collector current DC I CM Peak Collector Current Repetitive Peak collector current, T j 150 C I E Continuous Diode Current Maximum diode current DC I EM Peak Diode Current Repetitive Diode peak current, T j 150 C P C Power Dissipation Maximum power dissipation (per device), T C = 25 C T j Junction Temperature Allowable range of IGBT junction temperature during operation T stg Storage Temperature Allowable range of temperature within which the module may be stored or transported without being subject to electric load V iso Isolation Voltage Minimum RMS isolation voltage capability applied electric terminal to baseplate, 1 minute duration Mounting Torque Allowable tightening torque for terminal and mounting screws 2

7 Table 2.3 Electrical Characteristics Definitions Symbol Parameter Definition I CES Collector-Emitter Leakage Current I C at V CE = V CES, V GE = 0V V CE(sat) Collector-Emitter Saturation Voltage V CE at I C = rated I C and V GE = 15V t C(on) Turn-on Delay Time Time from I C = 10% to V CE = 10% of final value t C(off) Turn-off Delay Time Time from V CE = 10% of final value to I C = 10% of final value E on Turn-on Switching Loss Energy dissipated inside the IGBT during the turn-on of a single collector current pulse. Integral time starts from the 10% rise point of the collector current and ends at the 10% of the collector-emitter voltage point. E off Turn-off Switching Loss Energy dissipated inside the IGBT during the turn-off of a single collector current pulse. Integral time starts from the 10% rise point of the collector-emitter voltage and ends at the specified low collector current point, 10% of I C. t rr Diode Reverse Recovery Time Time from I C = 0A to projection of zero I C from I rr and 0.5 x I rr points with I E = rated I C V EC Forward Voltage Drop of Diode V EC at -I C = rated I C R th Thermal Resistance The rise of junction temperature per unit of power applied for a given time period R th(j-c) Thermal Resistance, Junction to Case I C conducting to establish thermal equilibrium R th(c-f) Thermal Resistance, Case to Fin I C conducting to establish thermal equilibrium lubricated 3.0 Structure Powerex Intelligent Power Modules utilize many of the same field proven module packaging technologies used in Powerex IGBT modules. Cost effective implementation of the built in gate drive and protection circuits over a wide range of current ratings has been achieved. This packaging technology is described in more detail in section TYPE C P N U 3.1. L-Series IPMs are available in two power circuit configurations, 6-PAC (C), and 7-PAC (R). Figure 3.1 shows the L-Series power circuit configurations. Figure 3.2 shows the available L-Series package styles; the small package in both screw terminal and pin terminal and the medium and large packages in screw terminal. TYPE R V W B Figure 3.1 L-Series Package Configurations P N U V W 3.1 Ceramic Isolation Construction The L-Series IPMs are constructed using ceramic isolation material. A direct bond copper process in which copper patterns are bonded directly to the ceramic substrate without the use of solder is used in these modules. This substrate provides the improved thermal characteristics and greater current carrying capabilities that are needed in these higher power devices. Gate drive and control circuits are contained on a separate PCB mounted directly above the power devices. The PCB is a multilayer construction with special shield layers for EMI noise immunity. Figure 3.3 shows the cross-section of an L-Series Intelligent Power Module. The structure of the L-Series control pin terminal is shown in Figure

8 BRASS L-Series Small Package with Pin Terminals L-Series Small Package with Screw Terminals NICKEL (Ni) THICKNESS = 1.5um GOLD (Au) THICKNESS = 0.3um Figure 3.4 Control Terminal of L-Series IPM 4.0 Installing IPMs L-Series Medium Package Figure 3.2 L-Series Packages MAIN ELECTRODE CONTROL PCB WIRE INTERNAL CONNECTION TERMINAL GUIDE PIN CONTROL TERMINAL GEL RESIN BASEPLATE CHIP INSULATED SUBSTRATE Part Quality of Material UL Flame Class Main Electrode Copper Plated with Nickel Control Input Terminal Brass Plated with Gold Guide Pin PPS Resin UL 94-V0 Resin Epoxy UL 94-V0 Gel Silicone Case PPS Resin UL 94-V0 Wire Aluminum Chip Silicon Baseplate Copper Control PCB Glass Epoxy UL 94-V0 Insulated Substrate Ceramic Internal Connection Terminal Copper Plated with Nickel Figure 3.3 Cross-section of L-Series IPMs L-Series Large Package CASE As Figure 4.1 shows, when the IPMs internal IGBTs are being switched off, voltage overshoot is introduced by the stray inductance of the power circuit as a result of the main current di/dt. The voltage overshoot can destroy the IPMs when the collector to emitter voltage of the IGBTs goes above the device s V CES rating. In order to avoid damaging an IPM due to an over-voltage the following recommendations should be implemented: 1. Locate the DC-link capacitor as close as possible to the IPM. 2. Use low impedance electrolytic capacitors for the DC-link. 3. Use low inductance parallel plates for the main conduction path from the DC-link capacitor to the IPM. 4. Use a film or ceramic capacitor mounted directly to the IPM s P and N terminals to absorb surge voltage. Uneven mounting stress should be avoided when attaching the modules to a heatsink because it can cause the ceramic isolation material in the modules to crack. It is best to have a large contact 4

9 area between the baseplate and the heatsink as this will provide low thermal impedance. The heatsink should have a surface finish in the range of Rz6~Rz12 and a curvature less than 100µm. A uniform coating of thermal grease between the module and the heatsink must be used and can prevent corrosion of the contact parts. Select a compound which has stable characteristics over the whole operating temperature range and does not change its properties over the life of the equipment. The thickness of the thermal grease should be from 100~200µm (4-8 mils) thick in accordance with the surface finish. Figure 4.2 shows the heatsink flatness. The heatsink should have less than /- 20µm of curvature for every 100mm of length and less than 10µm of roughness. The mounting screws should be tightened with a torque wrench as close as possible to but not exceeding the maximum torque specification given on the datasheet. A temporary tightening torque should be set to 20~30% of the maximum rating. When an electric driver is used, thermal grease with a low viscosity is recommended and any grease that extrudes must be removed before tightening the final screws. The recommended torque order for the mounting screws is shown in Figure Application of Thermal Grease Example This section provides an example thermal grease coating method. In order to follow this example you will need to have the following: an IPM module, thermal grease, a scraper or roller, an electronic scale, and gloves. The thickness of the grease can be calculated by the following equation: C V CE L 1 SMOOTHING L 1 L 2 SMALL SNUBBER L 2 L 1 : Stray inductance between the electrolytic capacitor and the IPM L 2 : Stray inductance between the filter capacitor and the driver L 3 : Stray inductance between the load and the power circuit s output stage L 2 L 2 LARGE Figure 4.1 Voltage Overshoot Caused by Stray Inductance in the Power Circuit GREASE APPLIED AREA Thickness of Grease = Amount of Grease (g) Base Area of Module (cm 2 ) x Density of Grease (g/cm 3 ) POWER MODULE CONVEX CONCAVE SPECIFIED RANGE OF HEATSINK FLATNESS L 3 L 3 EDGE LINE OF BASEPLATE Figure 4.2 Heatsink Flatness LOAD Since the recommended grease thickness is 100~200µm (4-8 mils) we can find the amount of grease needed given the grease density and baseplate area. For our example we have chosen a PM150RLA060 with a 60cm 2 baseplate and Shin-Etsu Chemical Co. (a) Two Point Mounting Type (b) Four Point Mounting Type (c) Eight Point Mounting Type Temporary Tightening: Final Tightening: (Temporary Tightening Torque is 20 ~ 30% of the Maximum Rating.) Figure 4.3 Torque Order for Mounting Screws 5

10 G-746 grease having a density of 2.66g/cm ~200µm = Amount of Grease (g) 60cm 2 x 2.66g/cm 3 The amount needed is 1.6~3.2g Once the amount of required grease has been calculated the grease can be applied uniformly across the baseplate using a scraper or a roller and a mask. 5.0 Thermal Impedance Considerations The junction to case thermal resistance (R th(j-c) ) and the case to heat sink thermal resistance (R th(c-f) ) are given on the individual device datasheets. Table 5.1 shows the thermal resistance values for the L-Series IPMs. The case temperature is measured just below the chip and the chip Table 4.1 Thermal Compounds locations as shown in Tables 5.2, 5.3 and 5.4. The thermal resistance is measured using a uniform 100~200µm coating of thermal grease, with a thermal conductivity of 0.92W/m* C, between the module and the heatsink. A thermocouple is used to measure the case and heatsink temperature along the same vertical line as shown in Figure 5.1. See Table 4.1 for a list of recommended thermal compounds. Manufacturer Shin-Etsu Chemical Co., Ltd. GE Toshiba Silicones Type KS-609, G-747, G-746 YG6260 DOW CORNING DC 340 For more information, please refer to manufacturers. Table 5.1 Thermal Resistance Values for L-Series IPMs Type Name Inverter (Just Under the Chip) Brake (Just Under the Chip) IGBT Chip Rth(j-c) Q FWDi Chip R th(j-c) IGBT Chip R th(j-c) Q FWDi Chip R th(j-c) Contact Thermal Resistance R th(c-f) 600V Type PM50RLA/B060, PM50CLA/B PM75RLA/B060, PM75CLA/B PM100RLA/B060, PM100CLA/B PM150RLA/B060, PM150CLA/B PM200RLA/CLA PM300RLA/CLA PM450CLA PM600CLA V Type PM25RLA/B120, PM25CLA/B PM50RLA/B120, PM50CLA/B PM75RLA/B120, PM75CLA/B PM100RLA/B120, PM100CLA/B PM150RLA/B120, PM150CLA/B PM200CLA PM300CLA PM450CLA

11 6.0 IPM Self Protection 6.1 Self Protection Features Intelligent Power Modules have sophisticated built-in protection circuits that prevent the power devices from being damaged should the system malfunction or be over stressed. Our design and applications engineers have developed fault detection and shut down schemes that allow maximum utilization of power device capability without compromising reliability. Control supply under-voltage, over-temperature, over-current, and short-circuit protection are all provided by the IPM s internal gate control circuits. A fault output signal is provided to alert the system controller if any of the protection circuits are activated. Figure 6.1 is a block diagram showing the IPM s internally integrated functions. This diagram also shows the isolated interface circuits and control power supply that must be provided by the user. The internal gate control circuit requires only a simple 15V DC supply. Specially designed gate drive circuits eliminate the need for a negative supply to off bias the IGBT. The IPM s control input is designed to interface with optocoupled transistors with a minimum of external components. The operation and timing of each protection feature is described in Sections 6.2 through 6.4. Table 5.2 Chip Layout (Small Package) 600V Type Type Name PM50RLA/RLB060, PM50CLA/CLB060 PM75RLA/RLB060, PM75CLA/CLB060 PM100RLA060, PM100CLA060 PM150RLA060, PM150CLA V Type PM25RLA/RLB120, PM25CLA/CLB120 PM50RLA/RLB120, PM50CLA/CLB120 PM75RLA/RLB120, PM75CLA/CLB120 UP VP WP UN VN WN Br IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi X Y X Y X Y X Y X Y X Y X Y Y X SMALL PACKAGE BACK SIDE 7

12 Y X Y X Powerex, Inc., 173 Pavilion Lane, Youngwood, Pennsylvania (724) Table 5.3 Chip Layout (Medium Package) 600V Type Type Name PM200RLA060, PM200CLA060 PM300RLA060, PM300CLA V Type PM100RLA120, PM100CLA120 PM150RLA120, PM150CLA120 UP VP WP UN VN WN Br IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi X Y X Y X Y X Y Table 5.4 Chip Layout (Large Package) Type Name 600V Type PM450CLA060 PM600CLA V Type PM200CLA120 PM300CLA120 PM450CLA120 UP VP WP UN VN WN IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi IGBT FWDi X Y X Y X Y X Y X Y MEDIUM PACKAGE BACK SIDE LARGE PACKAGE BACK SIDE 8

13 6.2 Control Supply Under-voltage Lock Out The Intelligent Power Module s internal control circuits operate from an isolated 15V DC supply. If, for any reason, the voltage of this supply drops below the specified under-voltage trip level (UV t ), the power devices will be turned off and a fault signal will be generated. Small glitches less than the specified t duv in length will not affect the operation of the control circuitry FIN MODULE METALLIC BASEPLATE and will be ignored by the undervoltage protection circuit. In order for normal operation to resume, the supply voltage must exceed the under-voltage reset level (UV r ) for a time greater than the fault output delay (t fo ). Operation of the under-voltage protection circuit will also occur during power up and power down of the control supply. This operation is normal and the system controller s program should take the fault output delay (t fo ) into account. Figure 6.2 is a timing diagram showing the operation of the under-voltage lock-out protection circuit. In this diagram an active low input signal is applied to the input pin of the IPM by the system controller. The effects of control supply power up, power down and failure on the power device gate drive and fault output are shown. Caution: 1. Application of the main bus voltage at a rate greater than 20V/µs before the control power supply is on and stabilized may cause destruction of the power devices. 2. Voltage ripple on the control power supply with dv/dt in excess of 5V/µs may cause a false trip of the UV lock-out. 6.3 Over-temperature Protection T SINK IGBT CHIP NOTE: Figure 5.1 Thermal Measurement Points SIGNAL OUTPUT ISOLATED POWER SUPPLY ISOLATING INTERFACE CIRCUIT ISOLATING INTERFACE CIRCUIT T C GATE CONTROL CIRCUIT GATE DRIVE OVER-TEMP UV LOCK-OUT OVER-CURRENT SHORT-CIRCUIT Figure 6.1 IPM Gate Drive Circuit INTELLIGENT POWER MODULE SENSE CURRENT TEMPERATURE SENSOR CURRENT SENSE IGBT COLLECTOR EMITTER The L-Series Intelligent Power Module has a temperature detector on each chip. If the temperature at any chip junction on the L-Series module exceeds the overtemperature trip level (OT) the IPM s internal control circuit will protect the power devices by disabling the gate drive and ignoring the control input signal until the over-temperature condition has subsided. In 6-PAC and 7-PAC modules all three low side devices will be turned off and a low side fault signal will be generated. High side switches are unaffected and can still be turned on and off by the system controller. The fault output will remain as long as the over-temperature condition exists. When the temperature falls below the overtemperature reset level (OT r ), and the control input is high (off-state) the power device will be enabled and normal operation will resume at the next low (on) input signal. 9

14 Figure 6.3 is a timing diagram showing the operation of the overtemperature protection circuit. The over-temperature function provides effective protection against overloads and cooling system failures in most applications. In cases of abnormally high losses such as failure of the system controller to properly regulate current or excessively high switching frequency, it is possible for the center of the IGBT chip to exceed T j(max) before the on-chip temperature sensor reaches the OT trip level. Caution: Tripping of the overtemperature protection is an indication of stressful operation. Repetitive tripping should be avoided. 6.4 Short-circuit Protection In the two step shutdown, the gate voltage is reduced to an intermediate voltage causing the current through the device to drop slowly to a low level. Then, about 5µs later, the gate voltage is reduced to zero completing the shut down. The Intellimod uses actual device SIGNAL CONTROL SUPPLY VOLTAGE OUTPUT CURRENT (I FO ) INTERNAL GATE VOLTAGE (V GE ) UV r UV t t FO t duv current measurements to detect all short-circuit current conditions. Even resistive and inductive shorts to ground that are often missed by conventional desaturation and bus current sensing protection schemes will be detected by the Intellimod s current sense IGBTs. t FO t duv 10 The IPM uses current sense IGBT chips to continuously monitor power device current. If the current though the Intelligent Power Module exceeds the specified short-circuit trip level (SC) for a period longer than t off (SC), the IPMs internal control circuit will protect the power device by disabling the gate drive and generating a fault output signal. The timing of the short-circuit protection is shown in Figure 6.4. The t off (SC) delay is implemented in order to avoid tripping of the SC protection on short pulses of current above the SC level that are not dangerous for the power device. When a short-circuit is detected a controlled shutdown is initiated and a fault output is generated. The controlled shutdown lowers the turn-off di/dt which helps to control transient voltages that can occur during shut down from high fault currents. Most Intelligent Modules use the two step shutdown depicted in Figure 6.4. SIGNAL CHIP TEMPERATURE (T C ) OUTPUT CURRENT (I FO ) INTERNAL GATE VOLTAGE (V GE ) CONTROL SUPPLY ON OT OT r SHORT GLITCH IGNORED POWER SUPPLY AND RECOVERY Figure 6.2 Operation of Under-voltage Lockout Figure 6.3 Operation of Over-temperature CONTROL SUPPLY OFF

15 Caution: 1. Tripping of the short-circuit protection indicates stressful operation of the IGBT. Repetitive tripping must be avoided. 2. High surge voltages can occur during emergency shutdown. Low inductance buswork and snubbers are recommended. 7.0 Controlling the Intelligent Power Module Intelligent Power Modules are easy to operate. The integrated gate drive and protection circuits require only an isolated power supply and an active low control signal. A fault output is provided for monitoring the operation of the modules internal protection circuits. SIGNAL 7.1 The Control Power Supply Depending on the power circuit configuration of the module two, four or six isolated power supplies are required by the IPM s internal drive and protection circuits. In high power 3-phase inverters using the larger 6-PAC type IPMs six isolated power supplies must be used. In these high current applications each low side device must have its own isolated control power supply in order to avoid ground loop noise problems. The control supplies should be regulated to 15V /-10% in order to avoid over-voltage damage or false tripping of the undervoltage protection. The supplies should have an isolation voltage rating of at least two times the IPM s V CES rating (i.e. V iso = 2400V for 1200V module). The current that must be supplied by the control power supply is the sum of the quiescent current needed to power the internal control circuits and the current required to drive the IGBT gate. Table 7.1 summarizes control supply requirements for L-Series IPMs. This table gives control circuit currents for the quiescent (non-switching) state and for 20kHz switching. This data is provided in order to help the user design appropriately sized control power supplies. Power requirements for operating frequencies other than 20kHz can be determined by scaling the frequency dependent portion of the control circuit current. For example, to determine the maximum control circuit current required for the low side (N) of a PM75RLA120 operating at 7kHz the maximum quiescent control circuit current is subtracted from the maximum 20kHz control circuit current: INTERNAL GATE VOLTAGE (V GE ) SHORT-CIRCUIT TRIP LEVEL t off (SC) t hold 42mA 19mA = 23mA 23mA is the frequency dependent portion of the control circuit current for 20kHz operation. For 7kHz operation the frequency dependent portion is: COLLECTOR CURRENT 23mA x (7kHz / 20kHz) = 8.05mA OUTPUT CURRENT (I FO ) To get the total control power supply current required, the quiescent current must be added back: t FO 19mA 8.05mA = 27.05mA NORMAL OPERATION FWD RECOVERY CURRENT OVER-CURRENT AND RECOVERY Figure 6.4 Operation of Short-circuit Protection NORMAL OPERATION 27.05mA is the maximum control circuit current required for the low side (N) of a PM75RLA120 operating at 7kHz. 11

16 Table 7.1 L-Series IPM Control Power Supply Current N Side (Each Supply) P Side (Each Supply) Part Number DC 20kHz DC 20kHz 600V Series PM50CLA PM50CLB PM50RLA PM50RLB PM75CLA PM75CLB PM75RLA PM75RLB PM100CLA PM100RLA PM150CLA PM150RLA PM200CLA PM200RLA PM300CLA PM300RLA PM450CLA PM600CLA V Series PM25CLA PM25CLB PM25RLA PM25RLB PM50CLA PM50CLB PM50RLA PM50RLB PM75CLA PM75CLB PM75RLA PM75RLB PM100CLA PM100RLA PM150CLA PM150RLA PM200CLA PM450CLA We can use the same technique described here to determine the control supply current required by each of the high side (P) IGBTs of the IPM. Capacitive coupling between primary and secondary sides of isolated control supplies must be minimized as parasitic capacitances in excess of 100pF can cause noise that may trigger the control circuits. An electrolytic or tantalum decoupling capacitor should be connected across the control power supply at the IPM s terminals. This capacitor will help to filter common noise on the control power supply and provide the high pulse currents required by the IPM s internal gate drive circuits. Isolated control power supplies can be created using a variety of techniques. Control power can be derived from the main input line using either a switching power supply with multiple outputs or a line frequency transformer with multiple secondaries. Control power supplies can also be derived from the main logic power supply using DC-to-DC converters. Using a compact DC-to-DC converter for each isolated supply can help to simplify the interface circuit layout. A distributed DC-to-DC converter in which a single oscillator is used to drive several small isolation transformers can provide the layout advantages of separate DC-to-DC converters at a lower cost. In order to simplify the design of the required isolated power supplies, Powerex has developed DC-to-DC converter modules to work with the IPMs. 20V DC can be connected to the M to produce four isolated 15V DC outputs to power the IPM s control circuits. The M can also be used as a stand alone unit if

17 20V DC is available from another source such as the main logic power supply. 24V DC can be connected to the VLA and VLA to produce a single isolated 15V DC to power the IPM control circuits. The VLA has an output capability of 100mA, while the VLA has an output capability of 300mA which may be needed with the larger size IPMs. Figure 7.2 shows an isolated interface circuit for a seven pack IPM using Powerex DC-to-DC converters. Section 9 gives details of Powerex development kits that employ this interface circuit. Caution: Using bootstrap techniques is not recommended because the voltage ripple on V D may cause a false trip of the under-voltage protection in certain inverter PWM modes. 7.2 Interface Circuit Requirements The IGBT power switches in the Powerex IPM modules are controlled by a low level input signal. The active low control input will keep the power devices off when it is held high. Typically the input pin of the IPM is pulled high with a resistor connected to the positive side of the control power supply. An ON signal is then generated by pulling the control input low. The fault output is an open collector with its maximum sink current internally limited. When a fault condition occurs the open collector device turns on allowing the fault output to sink current from the positive side of the control supply. Fault and on/off control signals are usually transferred to and from the system controller using isolating interface circuits. Isolating interfaces allow high and low side control signals to be referenced to a common logic level. The isolation is usually provided by opto-couplers. However, fiber optics, pulse transformers, or level shifting circuits could be used. The most important consideration in interface circuit design is layout. Shielding and careful routing of printed circuit wiring is necessary in order to avoid coupling of dv/dt noise into control circuits. Parasitic capacitance between high side interface circuits, high and low side interface circuits or primary and secondary sides of the isolating devices can cause noise problems. Careful layout of control power supply and isolating circuit wiring is necessary. The L-Series design kits are discussed in more detail in Section 9.0. Figure 7.1 shows the interface circuit layout used in the L- Series BP7A design kit and Figure 7.2 shows the board layout. The shielding and printed circuit routing techniques used in this example are intended to illustrate a typical application of the layout guidelines. The following is a list of guidelines that should be followed when designing interface circuits. INTERFACE CIRCUIT LAYOUT GUIDELINES 1. Maintain maximum interface isolation. Avoid routing printed circuit board traces from primary and secondary sides of the isolation device near to or above and below each other. Any layout that increases the primary to secondary capacitance of the isolating interface can cause noise problems. 2. Maintain maximum control power supply isolation. Avoid routing printed circuit board traces from UP, VP, WP, and N side supplies near to each other. High dv/dts exist between these supplies and noise will be coupled through parasitic capacitances. If isolated power supplies are derived from a common transformer interwinding capacitance should be minimized. 3. Keep printed circuit board traces between the interface circuit and Intellimod short. Long traces have a tendency to pick up noise from other parts of the circuit. 4. Use recommended decoupling capacitors for power supplies and opto-couplers. Fast switching IGBT power circuits generate dv/dt and di/dt noise. Every precaution should be taken to protect the control circuits from coupled noise. 5. Use shielding. Printed circuit board shield layers are helpful for controlling coupled dv/dt noise. Figure 7.2 shows an example (copied from a Powerex development kit) of how the primary and secondary sides of the isolating interface can be shielded. 6. High speed opto-couplers with high common mode rejection (CMR) should be used for signal input: t PLH, t PHL < 0.8µs CMR > V CM = 1500V Appropriate opto-coupler types are HCPL 4504, HCPL 4506 (Hewlett Packard), PS9613 (NEC) and TLP559 (Toshiba). Usually high speed optos require a 0.1µF decoupling capacitor close to the opto. 13

18 IC 7 VLA D R 15 IC 1 IC 12 C 1 R 1 V L W N V N U N BR W P V P U P FO GND R 12 R 11 CN 1 R 8 R 10 R 9 R 13 R 14 IC 2 IC 3 IC 8 IC 4 IC 9 IC 5 IC 10 IC 6 IC 11 C 2 R 2 C 3 R 3 C 4 R 4 D 2 C 5 R 5 D 3 C 6 R 6 D 4 L-SERIES IPM CONNECTOR R 7 CN 2 F O W N V N U N B R V N1 V NC V WPI W P WF O V WPC V VPI V P VF O V VPC V UPI U P UF O V UPC C 10 C 9 C 8 C 7 C VLA VLA VLA R 16 D 5 IC 13 IC 14 IC 15 CN 3 V COM Figure 7.1 L-Series IPM Interface Circuit 14

19 IC11 1 LED D4 R14 HCPL4504 C6 R6 IC6 IC10 1 LED D3 R13 HCPL4504 C5 IC5 R5 GND IC9 1 LED D2 CN1 R9 C4 C3 C2 C1 R3 R2 R1 R4 HCPL4504 IC4 R10 C10 V L 1 IC CN2 C7 C C9 R10 R8 HCPL4504 IC3 R11 HCPL4504 IC2 R12 HCPL4504 IC1 R15 IC7 1 D1 LED 7. Select the control input pull-up resistor with a low enough value to avoid noise pick-up by the high impedance IPM input and with a high enough value that the high speed opto-transistor can still pull the IPM safely below the recommended maximum V CIN(on). COMPONENT LEGEND LED D5 R16 CN3 C11 8. If some IPM switches are not used in actual application their control power supply must still be applied. The related signal input terminals should be pulled up by resistors to the control power supply (V D ) to keep the unused switches safely in offstate. The small and medium 6-PAC L-Series IPMs have a B terminal that should be left unconnected to minimize noise feedback to the IPM. COMPONENT SIDE 9. Unused fault outputs must be tied high in order to avoid noise pick up and unwanted activation of internal protection circuits. Unused fault outputs should be connected directly to the 15V of local isolated control power supply. Figure 7.2 Interface Circuit PCB SOLDER SIDE Other IPM Connection Requirements 1. The CLA and CLB type IPMs have a B terminal, however internally there is no brake circuit and so internally the terminal is not connected to the circuit. If a connection is made to these terminals it can degrade the noise immunity of the circuit. It is recommended to leave this terminal open. If any of the IGBTs in the IPM are not used pull the corresponding control inputs to the logic high voltage to prevent erroneous turn on of the IGBT by circuit noise. 15

20 16 2. Do not make a connection between the control side ground and the output emitter ground as it can cause the control to malfunction due to noise. The V NC and N terminals are connected internally. Do not make an external connection between these terminals as parasitic inductance in the device can create a high potential on the gate drive IC causing it to either be damaged or malfunction. Refer to Figure 7.3 where the main power circuit current is shown by the thick gray arrow. Figure 7.3 (B) represents the proper flow of gate drive circuit current and main power circuit current that occur with proper layout. 3. The IPM is not suitable for parallel operation. There is a degree of variance in switching times between different IPMs and one IPM may incur higher losses damaging the IPM due to thermal issues. It is not possible to coordinate switching times of two IPMs. 7.3 Speed Shifting Gate Drive The L-Series IPMs use the current sense of the IGBT chip to control gate drive speed. The speed shifting gate drive scheme is shown in Figure 7.4. During low current turn-on the IGBTs use slower gate drive and during higher current turn-on high speed gate drive is used. The speed shifting gate drive allows the IPMs to radiate less noise by softening the free-wheel diode recovery at low collector current, as shown in Figure 7.5, which improves the overall reliability of the system. Another advantage to the speed shifting gate drive is the reduction in turn-on switching losses with high speed gate drive at high collector current 7.4 Example Interface Circuits Intelligent Power Modules are designed to use opto-coupled transistors for control input and fault output interfaces. In most applications opto-couplers will provide a simple and inexpensive isolated interface to the system controller. Figures 7.6 and 7.7 show example interface circuits for the small and medium L-Series power circuit V DO IN V PC V DO IN V NC IPM (A) STRAY CURRENT configurations and Figure 7.8 shows the interface circuit for the large 6-PAC L-Series IPMs. These circuits use two types of optocoupled transistors. The control input s on/off signals are transferred from the system controller using high speed opto-coupled transistors. Usually high speed optos require a 0.1µF film or ceramic decoupling capacitor connected near their V CC and GND pins. The V DO IN V PC V DO IN V NC IPM PROPER LAYOUT Figure 7.3 Proper Connection of Control Side Ground and Output Emitter Ground CONTROL (ACTIVE LOW) i ON2 (SLOW) i OFF V D Q D ^ Figure 7.4 Speed Shifting Gate Drive i ON1 (FAST) V REF (B)

21 value of the control input pull up resistor is selected low enough to avoid noise pick up by the high impedance input and high enough so that the high speed optotransistor with its relatively low current transfer ratio can still pull the input low enough to assure turn on. The circuits shown use an Avago HCPL-4504 opto-transistor. This opto was chosen mainly for its high common mode transient immunity of 15,000V/µs. For reliable operation in IGBT power circuits opto-couplers should have a minimum common mode noise immunity of 10,000 V/µs. The HCPL- 4506, PS9613 (NEC) and TLP559 (Toshiba) are other recommended high speed opto-coupler types. Low th GEN. PM50RLA060 speed opto-coupled transistors can be used for the fault output and brake input. Slow optos have the added advantages of lower cost and higher current transfer ratios. The example interface circuits use an NEC PS2501 low speed optocoupled transistor for the transfer of brake and fault signals. Like most low speed opto-couplers the PS2501 does not have internal shielding. Some switching noise will be coupled through the optocoupler. Other recommended low speed opto-coupler types are the PS2502 (NEC) and the TLP- 521 (Toshiba). An RC filter with a time constant of about 10µs can be added to the opto s output to remove this noise. The IPM s VER:10dB/DIV. (RELATIVE VALUE) HOR:10MHz/DIV. 1.5ms long fault output signal will be almost unaffected by the addition of this filter. Always follow the interface circuit layout guidelines given in Section 7.2 when designing interface circuits. 7.5 Connecting the Interface Circuit The input pins of Powerex Intelligent Power Modules are designed to be connected directly to a printed circuit board. Noise pick up can be minimized by building the interface circuit on the PCB near the input pins of the module. The control pins are designed to be connected to the PCB using an inverse mounted header receptacle. This connection technique, as shown in Figure 7.9, can also be adapted to large 6-PAC and 7-PAC modules. Table 7.2 shows the suggested connection method and connector for L-Series IPMs. Figures 7.10 and 7.11 show the PCB layout for L-Series and the connectors listed on the table. 7.6 Dead Time (t DEAD ) START 30 MHz 10 MHz/ STOP 130 MHz th GEN. PM50RSD START 30 MHz 10 MHz/ STOP 130 MHz Figure 7.5 Noise Reduction Ver:10dB/div. In order to prevent arm shoot through a dead time between high and low side input on signals is required in the system control logic. It is important to consider optocoupler delay times when setting the controller s dead time. 7.7 Using the Fault Signal In order to keep the interface circuits simple the Intellimod uses a single on/off output to alert the system controller of all fault conditions. The system controller can easily determine whether the fault signal 17

22 V UPC LINE UF O U P 10µF U P INTERFACE C S N P V UP1 20k 0.1µF 15V B V VPC VF O V P SAME AS U P INTERFACE CIRCUIT OUTPUT 15V V P INTERFACE V VP1 Applicable Types 600V Series Rated Current (Amperes) Decoupling Capacitor (C S ) 7-PAC L-SERIES IPM V WPC WF O W P V WP1 SAME AS U P INTERFACE CIRCUIT OUTPUT 15V W P INTERFACE PM50RLA µF V NC PM50RLB µF U 33µF 15V PM75RLA µF V N1 PM75RLB µF PM100RLA µF PM150RLA µF D N BRAKE PM200RLA µF PM300RLA µF 1200V Series PM25RLA µF PM25RLB µF PM50RLA µF MOTOR V U N V N 20k 0.1µF 0.1µF U N V N N SIDE INTERFACE PM50RLB µF W 20k PM75RLA µF W N 0.1µF W N PM75RLB µF PM100RLA µF 20k PM150RLA µF F O NOTE: Unused fault outputs must be connected to the 15V of the local control supply. Figure 7.6 Interface Circuit for 7-PAC IPMs 18

23 V UPC LINE UF O U P 10µF U P INTERFACE C S N P V UP1 0.1µF 20k 15V V VPC VF O V P SAME AS U P INTERFACE CIRCUIT OUTPUT 15V V P INTERFACE V VP1 Applicable Types Rated Current (Amperes) Decoupling Capacitor (C S ) 600V Series PM50CLA µF PM50CLB µF 6-PAC L-SERIES IPM V WPC WF O W P V WP1 SAME AS U P INTERFACE CIRCUIT OUTPUT 15V W P INTERFACE PM75CLA µF PM75CLB µF PM100CLA µF PM150CLA µF U V NC V N1 33µF 15V PM200CLA µF PM300CLA µF U N 0.1µF U N 1200V Series PM25CLA µF PM25CLB µF PM50CLA µF PM50CLB µF PM75CLA µF MOTOR V V N W N 20k 20k 0.1µF 0.1µF V N W N N SIDE INTERFACE PM75CLB µF PM100CLA µF PM150CLA µF W F O 20k NOTE: If high side fault outputs are not used, they must be connected to the 15V of the local power supply. Figure 7.7 Interface Circuit for 6-PAC IPMs 19

24 V UPC LINE U PFO U P 10µF U P INTERFACE C S N P V UP1 20k 0.1µF 15V V VPC V PFO V P SAME AS U P INTERFACE CIRCUIT OUTPUT 15V V P INTERFACE V VP1 6-PAC L-SERIES IPM V WPC W PFO W P V WP1 SAME AS U P INTERFACE CIRCUIT OUTPUT 15V W P INTERFACE U V UNC U NFO SAME AS U P INTERFACE CIRCUIT OUTPUT 15V U N INTERFACE V UN1 Applicable Types Rated Current (Amperes) Decoupling Capacitor (C S ) 600V Series PM450CLA µf PM600CLB µf 1200V Series PM200CLA µf PM300CLA µf PM450CLA µf PM600CLA µf NOTE: If high side fault outputs are not used, they must be connected to the 15V of the local power supply. MOTOR V W V VNC V NFO V N V VN1 V WNC W NFO W N V WN1 SAME AS U P INTERFACE CIRCUIT SAME AS U P INTERFACE CIRCUIT OUTPUT 15V OUTPUT 15V V N INTERFACE W N INTERFACE Figure 7.8 Interface Circuit for 6-PAC IPMs 20

25 GUIDE PIN CONTROL PINS INVERSE HEADER RECEPTACLE PRINTED CIRCUIT BOARD L-SERIES IPM Figure 7.9 Connecting the Interface Circuit to the IPM D G B C F E H A Part Dia. A Distance from First Center of Guide Pin to Center of Last Guide Pin 2.75" B Hole for Header Receptacle Pin 0.032" C Clearance Hole for Intellimod Pin 0.032" D Clearance Hole for Intellimod Guide Pin 0.110" E Intellimod Pin Spacing 0.100" F Intellimod IGBT Ground Pin Spacing 0.630" G Guide Pin to First Intellimod P.S. Pin Spacing 0.130" H Spacing Between Header Receptacle Pin and Intellimod Pin 0.100" Figure 7.10 L-Series Intelligent Power Module Type Connection Method Using DF10-31S-2DSA (59) C D E H E J E F G B A C Part Dia. A Distance from Center of First Guide Pin to Center of Last Guide Pin 5.19" B Distance from Center of Intellimod Pin to Center of Intellimod Pin 4.94" C Distance between Guide Pin Centers Enclosing a Connector 1.25" D Distance between Proximate Guide Pin Centers Enclosing Adjacent Connectors 0.72" E Intellimod Pin Spacing 0.1" F Distance from First Pin Column to Fifth Pin Column 0.7" G Distance from First Pin of One Connector to first Pin of Next Connector 1.974" H Clearance Hole for Intellimod Guide Pin 0.11" J Clearance Hole for Intellimod Pin 0.04" K Hole for Header Receptacle Pin 0.04" Figure 7.11 L-Series Intelligent Power Module Type Connection Method Using MDF7-11S-2.54DSA (22) D C K E G tem controller of all fault conditions. The system controller can easily determine whether the fault signal was caused by an over temperature or over-current/short-circuit by examining its duration. Short-circuit and over-current condition fault signals will be t FO (nominal 1.5ms) in duration. An over-temperature fault signal will be much longer. The over-temperature fault starts when the baseplate temperature exceeds the OT level and does not reset until the baseplate cools below the OT R level. Typically this takes tens of seconds. NOTE: Unused fault outputs must be properly terminated by connecting them to the 15V on the local control power supply. Failure to properly terminate unused fault outputs may result in unexpected tripping of the modules internal protection. 7.8 IPM Inverter Examples The IPM s integrated intelligence greatly simplifies inverter design. The built in protection circuits allow maximum utilization of power device capability without compromising reliability. Input common mode noise filtering and MOV surge suppression helps to protect the input rectifier and IPMs from line transients. The main power bus is constructed using parallel plates separated by a thin layer of electrical insulation material in order to minimize parasitic inductance. Low inductance bus designs are covered in more detail in the General Application notes for IGBTs. The IPMs must be mounted on a heatsink with suitable cooling capabilities. Thermal design and power loss equations are covered in of the General Application notes for IGBTs. The following section of this application note gives an overview 21

26 of our on-line simulator that greatly simplifies power loss and junction temperature calculations. Powerex offers a complete line-up of diode modules that are ideal for use as the input bridge in inverter applications. 8.0 Power Loss and Junction Temperature Calculations The Mitsubishi Average Loss Simulation Software is a very powerful tool for estimating power loss and can be used with all of the L-Series IPM modules. The Powerex home page contains a link to the software. The following steps take you through an example calculation Table 7.2 L-Series Connection Methods Part Number Current (A) Voltage (V) estimating losses with a PM75CLA060 using the simulator: 1. Start the simulation software, 2. Click on the IGBT icon in the tool bar. 3. Select IPM from the division pull down menu. 4. Select IPM L-Series from the series pull down menu. 5. Select PM75CLA060 from the module pull down menu. 6. Click the OK button 7. Enter the application conditions. (Typical application conditions for the device will be entered as a default.) Brake Current (A) Connector (Hirose Part Number) PM50(#)L(*) DF10-31S-2DSA (59) PM75(#)L(*) DF10-31S-2DSA (59) PM100(#)LA DF10-31S-2DSA (59) PM150(#)LA DF10-31S-2DSA (59) PM200(#)LA DF10-31S-2DSA (59) PM300(#)LA DF10-31S-2DSA (59) PM450CLA NA MDF7-11S-2.54DSA (22) PM600CLA NA MDF7-11S-2.54DSA (22) PM25(#)L(*) DF10-31S-2DSA (59) PM50(#)L(*) DF10-31S-2DSA (59) PM75(#)L(*) DF10-31S-2DSA (59) PM100(#)LA DF10-31S-2DSA (59) PM150(#)LA DF10-31S-2DSA (59) PM200CLA NA MDF7-11S-2.54DSA (22) PM300CLA NA MDF7-11S-2.54DSA (22) PM450CLA NA MDF7-11S-2.54DSA (22) (*) Package Options: B = Solder Pin, A = Screw Terminal (#) Circuit Options: R = 7-PAC (6-PAC Brake), C = 6-PAC EXAMPLE: PM75RLB120 is a 75A, 1200V, 7-PAC (6-PAC Brake) in a Solder Pin Package Application conditions are as follows: I cp : Peak Collector Current V CC : Bus Voltage F sw : Switching Frequency T f : Heatsink Temperature R g : Resistivity of Gate Resistor PF: Power Factor 8. Hit the equal icon in the tool bar. Simulator results for the PM75CLA060 are shown in Figure 8.1. The initial results displayed by the simulator are a steady state approximation and are as follows: T j (IGBT): Chip junction temperature for the IGBT T j (Diode): Chip junction temperature for the free-wheeling diode P(IGBT): Power loss by each IGBT P(Diode): Power loss by each diode P(Total): Sum of power loss from all diode and IGBTs in the module Once the simulator has made power loss calculations, you can choose a variety of power loss curves from the Graph menu in the tool bar as shown in Figure 8.2. Figure 8.3 shows total power dissipation versus switching frequency while Figure 8.4 shows total power dissipation versus collector current for the PM75CLA060. Both graphs have separate curves for IGBT and diode losses. 22

27 9.0 Development Kits for L-Series IPMs Figure 8.1 PM75CLA060 Power Loss Simulation Powerex application engineers have devised development kits for use with L-Series IPMs. These kits are intended to quickly get the users to test their design as well as give an example of proper PCB layout. The BP7A series is intended for use with IPMs with rating from 50A to 300A in the 600V class and from 25A to 150A in the 1200V class. The BP6A is intended for use with the higher power rated 6-PAC L-Series IPMs rated from 450A to 600A in the 600V class and from 200A to 450A in the 600V class. The design kits contain a PC along with four or six isolated DC-to-DC converters. The complete bill of materials required for populating the rest of the board is given with the specific design kit datasheet. Our design kits follow the circuit interface design and layout recommendations that can be found throughout this application note. Application and technical information specific to both the BP6A and BP7A are available on the Powerex web site. Figure 8.2 Graph Menu Options 23

28 Figure 8.3 PM75CLA060 Total Power Loss Versus Switching Frequency Figure 8.4 PM75CLA060 Total Power Loss Versus I C 24