MG200Q2YS60A(1200V/200A 2in1)

Transcription

1 TOSHIBA IGBT Module Silicon N Channel IGBT (V/A in) High Power Switching Applications Motor Control Applications Integrates a complete half bridge power circuit and fault-signal output circuit in one package. (short circuit and over temperature) The electrodes are isolated from case. Low thermal resistance VCE (sat) =. V (typ.) Equivalent Circuit C 5 F O 7 E/C OT F O 3 E Signal terminal. G (L). F O (L) 3. E (L). V D 5. G (H). F O (H) 7. E (H). Open -9-9

2 Package Dimensions: -3CB. G (L). F O (L) 3. E (L). V D 5. G (H). F O (H) 7. E (H). Open Signal Terminal Layout G (L). F O (L) 3. E (L). V D 5. G (H). F O (H) 7. E (H). Open.5.5 Weight: 375 g -9-9

3 Maximum Ratings (Ta 5 C) Stage Characteristics Symbol Rating Unit Collector-emitter voltage V CES V Gate-emitter voltage V GES V Inverter Control Module Collector current DC I C A ms I CP Forward current DC I F A ms I FM Collector power dissipation (Tc 5 C) P C W Control voltage (OT) V D V Fault input voltage VF O V Fault input current IF O ma Junction temperature T j 5 C Storage temperature range T stg ~5 C Operation temperature range T ope ~ C Isolation voltage V isol 5 (AC min) V Screw torque 3 (M5) N m Electrical Characteristics (T j 5 C). Inverter Stage Gate leakage current Characteristics Symbol Test Condition Min Typ. Max Unit I GES V GE V, V CE 3/ ma V GE V, V CE na Collector cut-off current I CES V CE V, V GE. ma Gate-emitter cut-off voltage V GE (off) V CE 5 V, I C ma. 7.. V Collector-emitter saturation voltage V CE (sat) V GE 5 V, I C A Tj 5 C.. Tj 5 C 3. Input capacitance C ies V CE V, V GE, f MHz 5 pf Turn-on delay time t d (on).. Switching time Turn-off time t off V CC V, I C A V GE 5 V, R G 9. Fall time t f (Note ).5 Reverse recovery time t rr.5 Forward voltage V F I F A.. V Note : Switching time test circuit & timing chart. Control (Tc 5 C) Characteristics Symbol Test Condition Min Typ. Max Unit Fault output current OC V GE 5 V A Over temperature OT 5 C Fault output delay time t d (Fo) V CC V, V GE 5 V s V s 3-9-9

4 3. Module (Tc 5 C) Characteristics Symbol Test Condition Min Typ. Max Unit Junction to case thermal resistance R th (j-c) Inverter IGBT stage. C/W Inverter FRD stage.3 Case to fin thermal resistance R th (c-f) With silicon compound.3 C/W Switching Time Test Circuit R G I F V GE I C L V CC R G Timing Chart V GE 9% % 9% I rr I C I rr t rr % I rr 9% % % t d (on) t d (off) t f -9-9

5 Remark <Short circuit capability condition> Short circuit capability is s after fault output signal. Please keep following condition to use fault output signal. VCC 75 V. V VGE 7. V RG 9 Tj 5 C <Gate voltage> To use this product, VGE must be provided higher than. V. In case VGE is less than. V, fault signal FO may not be output even under error conditions

6 Tj 5 C 3 I C V CE VGE V 5 V V V 9 V Tj 5 C 3 I C V CE VGE V 5 V V V 9 V V V Collector-emitter voltage VCE (V) Tj 5 C V CE V GE A A IC A Collector-emitter voltage VCE (V) Tj 5 C V CE V GE IC A A A Gate-emitter voltage V GE (V) Gate-emitter voltage V GE (V) Collector-emitter voltage VCE (V) Tj C V CE V GE A IC A A 3 VCE 5 V I C V GE Tj 5 C 5 C C 5 5 Gate-emitter voltage V GE (V) Gate-emitter voltage V GE (V) -9-9

7 Forward current IF (A) 3 Common cathode VGE V 5 C I F V F Tj 5 C Collector-emitter voltage VCE (V) RL 3 9 Tj 5 C V V V V CE, V GE Q G VCE V Gate-emitter voltage VGE (V) C 3 5 Forward voltage V F (V) 5 5 Charge Q G (nc) SW time (ns) VCC V IC A VGE 5 V toff SW time R G td (off) ton tf td (on) tr SW loss Eon, Eoff (mj) E on, E off R G Eoff Eon VCC V IC A Tj 5 C VGE 5 V Tj 5 C Gate resistance R G (9) Gate resistance R G (9) SW time I C E on, E off I C toff SW time (ns) ton td (on) tr td (off) tf VCC V RG 9 Tj 5 C VGE 5 V Tj 5 C SW loss Eon, Eoff (mj) Eoff Eon VCC V RG 9 Tj 5 C VGE 5 V Tj 5 C Collector current I C (A) Collector current I C (A) 7-9-9

8 I rr, t rr I F E dsw I F Reverse recovery time trr (ns) Reverse recovery current Irr (A) trr Irr VCC V RG 9 Tj 5 C VGE 5 V Tj 5 C Reverse recovery loss Edsw (mj) Common cathode VCC V RG 9 Tj 5 C VGE 5 V Tj 5 C Forward current I F (A) Forward current I F (A) C V CE Safe-operating area IC max (pulsed)* Capacitance C (pf) VGE V f MHz Tj 5 C.. Cres Cies Coes IC max (continuous) *: Single nonrepetitive pulse Tc 5 C Curves must be derated linearly with increase in temperature. ms s 5 s Reverse bias SOA Tj 5 C RG 9 VGE 5 V Rth (j-c) ( C/W).. TC 5 C R th t w Diode stage Transistor stage.... Pulse width t w (s) -9-9