Selecting the Optimum MOSFET for Your Off-line Switching Power Supply

Transcription

1 Selecting the Optimum MOSFET for Your Off-line Switching Power Supply Marty Brown, Sr. Applications Engineer July-2017 Introduction: There are many subtle aspects when considering the best MOSFET for a switching power supply design. Conventional wisdom wants the designer to believe that the lowest RDS(on) yields the most efficient supply. Although that certainly has a bearing upon the efficiency, the RDS(on) is not the only consideration. A little elementary understanding of the construction of the MOSFET and how its interdependent parameters affect the power supply s performance, will allow a designer to make the best choice. As the power system designer, you already are familiar about how the power supply is going to be used and the limits to its operation (input line, load, temperature, etc). In an ideal world, knowing where the system spends 90+% of its operational life would be nice. In the same ideal world, the requirement that the supply should be 100% efficient, occupy zero space and cost nothing is always being discussed. After spending some time in the real-world, one then realizes that the design should be the best design at the lowest reasonable cost. A Standard MOSFET vs. a Superjunction MOSFET: Today, the basic choice of silicon MOSFETs fall into two major divisions, the Planar and/or Trench MOSFET, and the superjunction MOSFET. Planar MOSFETs have their active region close to the surface of the die. This can be seen in figure 1. Figure 1. Standard Planar MOSFET Construction. To decrease the RDS(on), additional die area is required, and to increase the voltage of the MOSFET, the die must be made thicker. The superjunction MOSFET uses its die depth to increase the channel area and thus significantly reducing its RDS(on) for a given die area. The superjunction s channel is constructed into the die instead

2 of just being on or near the surface of the die. This greatly increases the conduction area within a much smaller surface area. The superjunction MOSFET can be seen in figure 2. Source Gate Source ʃʃ SiO 2 ʃʃ N+ P P Channel N+ Channel N+ P ID N Drain Figure 2. The Construction of a Generalized Superjunction MOSFET This results in much lower on-resistance, allowing a smaller die size for each current rating as compared to the planar MOSFET. As an added benefit, much lower parasitic capacitances with much faster switching speeds are obtained. Let s compare the important parameters between a standard planar MOSFET and a high performance D3 superjunction MOSFET. The parts presented in Table 1 are real and have nearly identical drain voltage and current ratings. Part Number PKG VDSS ID at +100 C ID at +25 C Qg trise tfall XXX10N60 TO220FP 600V 6A 10.5A 47nJ 31 ns 23 ns D3S340N65 TO V 7.3A 11.4A <25 nj 9.0 ns 6.4 ns Part Number Ciss Crss RDS(on) Eas PD Өjc XXX10N pf 35pF 650 mω 300mJ 39W 3.2 C/W D3S340N65 940pF 1.3pF <340 mω 200mJ 160W 5.3 C/W Table 1. Comparison of a Representative Standard vs. a D3 Superjunction MOSFET with nearly Identical Drain Ratings. As one can see, the RDS(on) and the MOSFET s annoying parasitic capacitances are much lower, and the switching speed is more than 3 times faster. The truly amazing factor is the uncapped die area of the superjunction MOSFET is one-third that of the Planar MOSFET.

3 How Does the MOSFET Affect the Performance of the Power Supply? Figure 3 illustrates a very common plot when testing switching power supplies. The test is the supply s efficiency over its expected load range. The efficiency exhibits a peak at some load between the maximum and minimum loads. If you have done a good design, that peak will be at or near where the supply operates 90+ percent of its operating life. Its location and its peak value is totally determined by trading-off the various MOSFET parameters during the design process. Figure 3. Efficiency vs. Load The Influences. At light loads, the on-time (duty cycle) is small. This makes the MOSFET conduction losses much less significant. Here, the switching and gate drive losses dominate its efficiency. Within the typical power supply, the switching frequency is relatively constant, so the switching and drive losses are also relatively constant. At higher loads, the MOSFET (and output rectifier) conduction losses become more significant than the drive and switching losses. Here, the value of RDS(on) becomes important. As with all resistive switches, the supply s efficiency deteriorates as the output load increases. This non-linear effect is the ID 2 (RDS(on)) loss. The Definition of Major MOSFET-Related Losses: The losses within the power switching stage (MOSFET, BJT, IGBT, etc.) can be separated into three different categories: conduction loss, switching loss, and drive loss. These losses can be narrowly viewed and measured in the physical circuit, and can also be estimated from the datasheet parameters. The Power Switch circuit under examination is shown in Figure 4.

4 A,) The Physical Circuit b.) The Loss Model. Figure 4. The MOSFET Power Switch Circuit Stage. From the model shown in Figure 4b, one can construct the loss circuit model for each of the three loss periods experienced during each switching cycle. Each of the voltages and current signals should and could be easily measured from the physical circuit. The Conduction Loss: The period for this loss is only during the on-time of the MOSFET and the waveforms of interest are the absolute values of the drain voltage and drain current. In hard-switched PWM supplies, the drain current is simply a trapezoid whose amplitude is I(min) at its start and Ipk at its end, as seen in Figure 5a. Within resonant supplies, the wave shapes are more complicated. Typically, the drain current is a portion of a sinusoid described by a beginning and an ending phase angle, or how close to resonance it operates. Its amplitude value can be a positive and/or a negative value, depending upon its phase. During positive drain current flow, the VDS is a result of the drain current flowing through the active RDS(on) of the MOSFET. When the drain current is negative, the drain-to-source voltage is the forward voltage drop of the antiparallel diode of the MOSFET. A representative LLC converter conduction period can be seen in Figure 5b.

5 Drain Current Fwd Drain VDS Diode Vfwd Time a). PWM Conduction Period b.). Resonant Supply Conduction Period. (ex. LLC Converter) Figure 5. The Conduction Periods of Common Switching Power Supplies t0 t1 t2 The conduction loss is completely determined by the on-time duty cycle of the power switching circuit. That is, it has no dependence upon the switching frequency. The major determining parameter for the conduction loss IS the RDS(on) of the MOSFET. The Switching Loss: The simplistic definition of a MOSFET switching loss is the product of VDS and ID over the switching period which occurs when either the ID and VDS are non-zero. The definition of the MOSFET switching parameters (tdly(on, tdly(off), tr, and tf) surprisingly vary between MOSFET suppliers. So when you are using the data sheet parameters from MOSFET suppliers, please check to see if their parameter definitions adhere to JEDEC JESD77-B! Figure 6 illustrates the exact definitions of the MOSFET switching parameters per JESD77-B. The parameters in bold are the parameters referenced (supposedly) on data sheets. It is very useful, in the early part of the design phase, to estimate the turn-on and turn-off switching losses from the data sheet parameters, instead of having to build the prototype and actually view the MOSFET switching behavior. The inductive hard-switched PWM switching period can be seen in Figure 6. Resonant transition switched power supplies will have a different set of wave forms.

6 Figure 6. Definition of the MOSFET Parameters per JESD77-B. The switching losses are dependent upon the parasitic capacitances of the MOSFET and the external circuit and its parasitics. These will change with drive, and operating conditions. Here, both the voltage and current are simultaneously transitioning (rising or falling) across the MOSFET s drain and source terminals during this period. One can graphically estimate these by summing the areas of triangles and rectangles. The switching loss is directly proportional to the supply s switching frequency. So for a fixed frequency design, the switching loss is only dependent upon Vin, Pout, and Ig. In other words, the 2- dimensional graph shown in Figure 3 is actually a 3 dimensional graph with X being the Output Load, Y being the Efficiency, and Z being the input voltage, as seen in Figure 7. Efficiency (%) Input Voltage (%) Figure 7. Representative Three-Dimensional Plot of System Efficiency. The drive Loss: The drive loss is dissipated within the MOSFET driver IC and the series gate resistance. It is totally defined by: Rg, the Ciss (Cgs), Crss (Cdg), the RDS(on)s of each of the driver totem-pole output MOSFETs, the gate drive voltage and the switching frequency. The associated waveforms can be seen in Figure 8.

7 Figure 8. The Gate Drive Waveforms. The sloped portion of the gate voltage (Red) is simply the gate driver charging or discharging only the input gate capacitance (Ciss). The flat periods of the gate voltage ( Vg(th)) is the Miller capacitance (Crss) injecting its stored energy during the drain voltage s transitions, into Ciss. During these period, the gate driver must not only charge or discharge the input capacitance (Ciss), but also provide additional current to overcome the energy inserted by the Miller capacitor (Crss). Both the slopes, the current peak and its duration are dependent upon the value of the gate resistor and the RDS(on) s of the driver s output devices. So, the higher the total series gate resistance, the lower the rise and fall times of the drain voltage and current, and the longer the switching periods. The drive loss is determined by the switching frequency, the total gate drive resistance, gate drive voltage, and the MOSFET s input capacitance. It is immune to changes in the output power. The Estimation of the MOSFET Losses: One must first estimate the energy lost (expressed in Joules (J)) during each loss period within each switching cycle. To calculate the switching/drive power loss (Watts), multiply the calculated energy loss during each loss period times the switching frequency. The energy loss during each loss period can be written as: Conduction Loss: (on-time) Econd = fsw[ T on ʃv RDS(on) I D(on) dt on] Watts or Econd = fsw[rds(on)ʃ ID 2 (on) dt on] Watts MOSFET Switching Loss: Turn-Off: E SW(toff) = fsw[ ʃv DI D dt(t d(off)) + ʃv DI D dt(t f) Watts Turn-on: E SW(ton) = f SW[V D ʃi Ddt(t f) + I DʃV D dt(t r(v))] Watts The Drive Loss:

8 Turn-on: Turn-off: E DR(on) = f SW[ʃIgdtf)] 2 x (R DS(on)UPPER + Rg)] Watts E DR(off) = f SW[ʃIgdtr)] 2 x (R DS(on)UPPER + Rg)] Watts The wave shapes are expressed as integrals since the voltage and current waveforms are complex, and non-rectangular. Graphically, from the scope plots, one can piecewise sum areas under the curve of each waveform by using the areas of a triangle, rectangle, or trapezoid. Overall Efficiency Considerations: If one were to only look at a power supply s efficiency at one operating condition, it would be very misleading. If you were to consider the variation in efficiency over the expected range of output load (W) and input voltage (V), one gets a very clear understanding of the performance of the power supply of its complete operating range. That peak of the efficiency, as seen in Figure 3, may make you consider selecting an optimum MOSFET for your design and operating range. That is where the peak efficiency occurs where your supply spends 90%+ or its operating life. Figure 9 is a qualitative representation of the behaviors of the three losses over the load range.... Change (%) Figure 9. The Behavior of the Three Losses over the Load Range. Figure 9 only describes the losses individually and not collectively. When these losses are combined (summed) the result is much more informative. Figure 9 is an example of an undesirable result of choosing wrongly.

9 Higher RDS(on) Peak Low Peak Hi Lower RDS(on) Output Power (%) Figure 10. An Example of Choosing the Lowest RDS(on) MOSFET within a Supply. In this example, the designer chose the lowest RDS(on) MOSFET within a family of high voltage MOSFET offerings. The result was an overall lower supply efficiency as compared to if the designer had chosen a higher RDS(on) (smaller die area) device. Of course, there is a whole set of variations in the results given the range of MOSFET parameters and operating conditions. Figure 7 represents a worst possible case outcome of a poor design decision. In this case, by choosing the lowest available RDS(on) MOSFET, increases the Ciss and Crss. This required a higher peak gate drive current. If the gate driver could not supply that peak current in the short period, the MOSFET would switch slower (longer tsw and lower dvd/dt). This drastically increases the significant drain-source switching loss and the gate driver loss. The gate driver experiences a larger loss related to the amplitude of the peak gate current and the lengthened time required to switch the MOSFET. The resulting drive and drain-source switching loss would then make the efficiency noticeably worse at the lighter loads and also arithmetically lowers the combined efficiency curve by the amount of these losses. This degrades the overall efficiency, especially at the lighter loads, and pushes the peak efficiency point towards the higher loads. The perceived benefit of a reduced RDS(on) do indeed decrease the conduction loss, but its overall effect is somewhat marginal. The conduction loss is mainly responsible for the curviness of the efficiency curve. The degree of curvature becomes lesser for lower RDS(on)s. The increase in the efficiency due to the reduced RDS(on) is only arithmetic. The conduction loss is still overwhelmingly dominated by the square of the drain current. This helps at the higher loads where the efficiency is dominated by the conduction loss. In the case of Figure 9, the increase in the switching and drive losses were larger than the improvement in the raised efficiency level and the curvature. This IS a very possible outcome.

10 Efficiency (%) Input Voltage (%) Figure 10. Representative Three-Dimensional Plot of System Efficiency. Figure 10 represents how the variation of a supply s efficiency changes with changes in the input voltage with a low impedance input source. With an input source that exhibits a higher impedance, such as with a PFC pre-regulator, the efficiency curve would differ. For the average engineer, not really understanding the physical influences of MOSFETs, the choice of MOSFET is made once and the results are accepted. To the informed designer, this is only acceptable when the MOSFET behavior is more thoroughly examined. Summary: The MOSFET represents the largest percentage of losses within the typical switching power supply. The rectifiers are a lesser second. By examining the behavior and performance of the MOSFET, one can significantly improve the efficiency of the supply over its expected operating conditions. Optimizing the MOSFET s efficiency in the operating region where the supply will be operating most of the time, saves energy in the long term. Migrating to a super junction MOSFET from a standard planar MOSFET is compelling. Just comparing the major parameters between the planar and super junction MOSFETs of close drain ratings, as seen in Table 1, speaks volumes about how a designer can improve the performance of a typical offline switching power supply. As an example, the super junction MOSFET exhibits a >73% reduction in its die area, a >50% reduction in Ciss, and a >69% reduction of the value of the miller capacitance (Crss). Both parameters are important to cost and switching performance. D3, with its optimum MOSFET design, offers a best-in-class performance in all off-line switching power supply applications.

11 References: 1.) JEDEC Standard: Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices, JESD77-B, pgs: 4-28 thru 4-44, URL: