IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY Impact Ionization MOS (I-MOS) Part II: Experimental Results

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY Impact Ionization MOS (I-MOS) Part II: Experimental Results Kailash Gopalakrishnan, Raymond Woo, Christoph Jungemann, Member, IEEE, Peter B. Griffin, and James D. Plummer, Fellow, IEEE Abstract Part I of this paper dealt with the fundamental understanding of device physics and circuit design in a novel transistor, based on the field-effect control of impact-ionization (I-MOS). This paper focuses on experimental results obtained on various silicon-based prototypes of the I-MOS. The fabricated p-channel I-MOS devices showed extremely abrupt transitions from the OFF state to the ON state with a subthreshold slope of less than 10 mv/dec at 300 K. These first experimental prototypes of the I-MOS also showed significant hot carrier effects resulting in threshold voltage shifts and degradation of subthreshold slope with repeated measurements. Hot carrier damage was seen to be much worse in nmos devices than in pmos devices. Monte Carlo simulations revealed that the hot carrier damage was caused by holes (electrons) underneath the gate in pmos (nmos) devices and, thus, consequently explained the difference in hot carrier effects in p-channel versus n-channel I-MOS transistors. Recessed channel devices were also explored to understand the effects of surfaces on the enhancement in the breakdown voltage in I-MOS devices. In order to reduce the breakdown voltage needed for device operation, simple p-i-n devices were fabricated in germanium. These devices showed much lower values of breakdown voltage and excellent matches to MEDICI simulations. Index Terms Avalanche photodiodes (APDs), gate control of impact ionization, Germanium (Ge), hot carriers, impact ionization (I-MOS), kt/q, low static power, modulated breakdown, MOSFET, p-i-n, recessed channel devices, silicon, subthreshold slope, surface breakdown, surface impact-ionization, 10 mv/dec. I. INTRODUCTION IN PART I of this paper, device simulations were used to understand the operational principles of a novel transistor I-MOS that is based on the gated control of impact ionization in a narrow p-i-n junction. In addition, circuit design simulations and analysis were also used to evaluate how the devices behaved in a circuit framework. In this paper, we describe experimental results obtained with various prototypes of I-MOS transistors with the objective of verifying the basic concept and further understanding the device physics. Hot carrier reliability is a concern in silicon (Si)-based I-MOS devices because they operate at higher voltages than typical CMOS devices and are based on impact ionization that generates many secondary hot carriers. A detailed study of these Manuscript received August 2, 2004; revised November 1, This work was supported in part by the Stanford Graduate Fellowship Program, in part by DARPA, and in part by the MARCO MSD Focus Center. The review of this paper was arranged by Editor T. Skotnicki. K. Gopalakrishnan was with Stanford University, Stanford, CA USA. He is now with IBM Almaden Research Center, San Jose, CA USA. R. Woo, C. Jungemann, P.B. Griffin, and J.D. Plummer are with Stanford University, Stanford, CA USA. Digital Object Identifier /TED hot carrier effects is necessary not only from the reliability perspective but also because a fundamental understanding of hot carrier injection mechanisms could lead to the creation of low power Flash memory devices. In addition, possible techniques to reduce hot carrier degradation in I-MOS devices are also of interest in logic circuits that employ these transistors. The experimental values of the breakdown voltage in the initial I-MOS transistors were much higher than the breakdown voltages reported in the literature for simple p-i-n diodes. Since scalability of the breakdown voltage might determine the eventual acceptance of this technology, we clarify the mechanisms behind the higher breakdown voltage in I-MOS transistors. It is believed that the values of the impact ionization coefficient may be much lower near interfaces than in the bulk of the material. Comparison of recessed gate devices (with impact ionization occurring in the bulk of the Si) with corresponding Si surface I-MOS prototypes clarifies the role of interfaces on the avalanche coefficients and breakdown voltage. In part I of this paper, we described how Ge p-i-n diodes showed much lower values of breakdown voltage than their Si counterparts. Experimental prototypes of germanium (Ge)-based p-i-n diodes were fabricated and the values of the breakdown voltage obtained were compared with simulations. II. I-MOS DEVICE FABRICATION AND EXPERIMENTAL DATA In order to verify that the I-MOS has a subthreshold slope that is steeper than kt/q, Si-based n-channel and p-channel devices were fabricated in the Stanford Nanofabrication Facility (SNF) [1]. Conventional g-line lithography was used to make simple prototypes in a 0.2- m-thick Si film in SOI wafers using a ten-mask process that was very similar to conventional Si CMOS processing. The basic process flow that was used (after conventional active-area definition and n-well and p-well implantations) for p-channel devices is shown in Fig. 1. Fig. 2 shows the dc versus characteristics of the p-channel I-MOS transistor for a device with an offset of 0.3 m in Mode 1. Experimental results on Mode 2 are not discussed as they involve band-to-band tunneling (BTBT) and not impact-ionization in Si. Results on Mode 2 and its application for low-voltage Flash memories are discussed elsewhere [21]. When the device is measured for the first time, the device characteristics show extremely abrupt subthreshold slopes mv dec with OFF currents of the order of a few nanoamperes/microns [1]. This shows that devices based on the field-effect control of impact ionization show extremely abrupt transitions from the OFF state to the ON state. However, as the device is measured repeatedly, the threshold voltage of the /$ IEEE

2 78 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 Fig. 1. Process flow for a p-channel SOI I-MOS device. Most of the fabrication steps resemble those of a normal CMOS process. After gate patterning (b), a mask that exposed half of the active area on one side of the gate is used for p+ drain implantation (c). For the next lithography step, the n+ mask had precisely controlled offsets that were used to offset the source region from the edge of the gate (d). Rapid thermal annealing (RTA) at 1000 C for 30 s was then used to activate the dopants while minimizing dopant diffusion followed by the traditional contact and metal steps. Fig. 2. Experimental I versus V characteristics for a p-channel SOI I-MOS transistor with L (drawn) = 0:3 m. The subthreshold slope is very abrupt and is of the order of mv/dec when the device is measured for the first time. As the device is measured repeatedly, the threshold voltage of the device shifts significantly. In addition, the subthreshold slope degrades with further measurement. I is self-limited by hot carrier programming. device increases monotonically (i.e., becomes more negative for the p-channel device) and the subthreshold slope degrades considerably. Simple two terminal p-i-n devices fabricated on the same wafer did not show any shift in the breakdown voltage and maintained abrupt switching from the OFF state to the ON state for at least 1000 cycles. There were three possible explanations for instability in the p-channel I-MOS devices: irreversibility of the breakdown process, thermal runaway, or hot-carrier effects. Previous experimental data in trapped-plasma avalanche-triggered transit (TRAPATT) diode and impact-ionization avalanche transit-time (IMPATT) diode oscillators [2] and p-i-n diodes indicated that the avalanche breakdown process was completely reversible. In addition, p-i-n devices fabricated on the same wafer did not show any degradation at similar values of currents and voltages and the stressed I-MOS devices retained their shifts for many hours after the measurements indicating that thermal runaway [3] was not responsible for the shifts. However, higher values of the applied voltage necessary to induce breakdown in these large i-length Si I-MOS devices can cause substantial carrier heating. This carrier heating can result in significant hot carrier injection into the gate dielectric or in the offset region, which can possibly affect. In addition, hot carrier injection can cause considerable interface damage that can degrade the subthreshold slope. shifts were confirmed to be caused by hot carrier injection and trapping by baking the wafers at 200 C for 30 min which caused shifts to disappear by detrapping the injected carriers. However, baking did not completely restore the subthreshold slopes of these devices since the current in the OFF state increased slightly possibly due to interface states created by hot carrier injection. The nature of carrier injection (electron versus holes) and its position in the dielectric will be analyzed in greater detail in Section III. N-channel I-MOS devices did not show abrupt transitions from the OFF state to the ON state but instead showed significant values of gate current. The differences in the characteristics between the n-channel and the p-channel devices will also be explained in the next section. Fig. 3 shows the dependency of the breakdown voltage of p-channel I-MOS devices with varying i-lengths and compares it to the experimental breakdown voltage data with MBE fabricated p-i-n diodes [4]. The I-MOS breakdown voltage was defined as the drain voltage at which the current switched abruptly to the ON state at V. For the p-channel I-MOS, the effective i-length was arbitrarily defined from the point at which the n-type doping dropped to to account for the finite roll-off in the source doping profile. As expected, the breakdown voltages scale with the scaling of the i-length although it is clear that I-MOS devices have higher values of breakdown voltage than corresponding two terminal p-i-n devices. One possible reason can be attributed to the lower carrier concentration

3 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS) Part II EXPERIMENTAL RESULTS 79 Fig. 3. Comparison between the experimental breakdown voltages in lateral p-i-n diodes, I-MOS transistors V = 01 V) and recessed channel I-MOS devices. Device structure for recessed channel I-MOS devices is shown in Fig. 6. Experimental results for p-i-n diodes were taken from [4]. For p-channel I-MOS transistors, the length of the i-region has been defined as the drawn i-length minus the point at which the n-type doping falls below 10 =cm in simulations. P-i-n diodes have a much lower breakdown voltage than I-MOS transistors for similar i-lengths. These breakdown voltages for recessed channel devices are lower than those for conventional I-MOS transistors and closer to the silicon p-i-n breakdown voltage values possibly because of lesser influence of the surface. holes) in the region underneath the gate as compared to the heavily doped region in the two terminal case which could cause a finite voltage drop to happen in the MOS part of the I-MOS device. The other reason can be attributed to the differences in the values of the surface and bulk impact ionization coefficients and will be treated in some detail in Section IV. III. HOT CARRIER ANALYSIS IN THE I-MOS Baking experiments that restored I-MOS threshold voltages confirmed that hot carriers injected into the dielectric were responsible for shifts but did not indicate what carriers (electrons versus holes) caused these shifts and even more importantly did not indicate the point of maximum carrier injection and trapping. MEDICI simulations coupled with nonlocal selfconsistent Monte Carlo simulations in Galene [5] were used to reveal the nature of the trapped charge and its position in the gate dielectric. Monte Carlo simulations showing electron and hole carrier energy with position for a p-channel I-MOS device (with m and m) at V and V are shown in Fig. 4. From the figure, it is clear that the I-MOS has both hot electrons and hot holes at various positions between the source and the drain regions. The hot holes exist primarily in the region underneath the gate and peak in energy near the edge of the gate. In the i-region outside the gate, the hole energy is substantially lower than the electron energy and the electron energy increases with position till it reaches the edge of the source region. This means that hot carrier injection can occur due to both hot holes near the edge of the gate (or underneath the gate) and/or due to hot electrons in the offset region. MEDICI local simulations were done with point charges of m at various points in the dielectric (both under the Fig. 4. Monte Carlo simulations in GALENE [5] showing the position and energy dependency of the electron and hole concentration along the interface in a p-channel I-MOS device (L = 0:2 m: L = 0:1 m). I-MOS has both hot electrons and hot holes at various positions between the source and the drain regions. The hot holes exist primarily under the gate while electrons peak in energy in the offset region. gate and in the offset region) and the versus characteristics were simulated. These simulations indicated that electron point charges at all points in the dielectric above the i-region only caused a reduction in due to either a reduction in the MOS (if the charge was placed underneath the gate) or a reduction in the breakdown voltage due to a reduction in the effective i-length (if the charge was placed in the offset region). This trend was opposite to the trend observed experimentally where was seen to increase with stress. These simulations also indicated that only hole injection underneath the gate caused to increase as was observed experimentally. This indicated that only hot holes injected underneath the gate for pmos and hot electrons injected underneath the gate for nmos transistors were responsible for shifts observed experimentally. The above simulations also explained why it was a lot more difficult to get stable nmos devices. The hole barrier height for thermionic injection is 4.8 ev and the electron barrier height is 3.1 ev and thus hot electron injection is a lot more efficient at comparable biases than hot hole injection. This is especially true because the ionization threshold energy [6] for both electrons and holes in Si is definitely lower than 4.8 ev, which causes a good fraction of holes to undergo an energy loss due to impact ionization before they can get hot enough to be injected by thermionic emission into the gate dielectric. nmos device data, shown in Fig. 5 for a m device, also showed

4 80 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 Fig. 5. N-channel I-MOS quasi-static device data for L =0:3 m. There is substantial gate current for jv j > 9 V (below 9 V, I is below the detectable noise floor of the parameter analyzer). Device characteristics do not show abrupt transitions from the OFF to the ON state because of dynamic hot carrier programming. For jv j > 10 V, injection efficiencies (= I =I ) as high as 10 were obtained. a substantial gate current while no such gate current was detectable in pmos devices. Injection efficiency (defined as the ratio of the ) was as high as for Vin nmos devices. Since only a few thousand electrons can cause a considerable shift in, it is believed that the nmos devices had substantial programming in time scales of the order of nanoseconds after the device turned on. Since measurements in Fig. 5 corresponded to quasi-static dc measurements (with the time step at each bias point being around a millisecond or more), stable nmos devices were not obtained due to the large number of injected hot electrons. Such high injection efficiency could however be harnessed in a useful fashion in Flash devices for low power programming [7], [8]. At this point, it is worth examining the reasons for the high hot carrier damage and injection efficiency in n-channel I-MOS devices when compared to similar n-channel MOS devices [9]. There are three primary reasons why the I-MOS has a higher injection efficiency: 1) The operating voltages needed for Si I-MOS devices are higher than the operating voltages needed for comparable Si nmos devices and, thus, carrier heating is subsequently higher; 2) In an n-channel MOS device, electron heating and its subsequent injection into the gate dielectric occurs near the drain edge of the gate. The conditions needed to cause efficient electron heating (high lateral electric fields) contrast with the conditions needed to attract the electrons to the gate (high vertical electric fields). When the gate voltage is increased, the vertical electric fields increase but the lateral electric fields decrease and these conflicting requirements cause n-channel MOS devices to have a low injection efficiency ( or lower). In an n-channel I-MOS device, due to the polarity of the voltages ( and ), the conditions needed for both efficient carrier heating and for attracting the electrons to the gate can be met simultaneously. In addition, electron injection in the I-MOS occurs at the source-side and source-side injection techniques have been known to improve injection efficiency in Flash memories [10], and; 3) Finally, simulations of the electron current flow patterns in the n-channel I-MOS (Fig. 3 in [11]) showed that a considerable fraction of the electrons have a vertical component to their momentum due to the nature of the breakdown process in the offset region. This alleviates the need for an intravalley acoustic-phonon scattering event for momentum redirection [12], [13] and therefore electron injection into the gate can occur with higher efficiency than in a normal n-channel MOS transistor. Hot carrier injection in the I-MOS, and the resultant shifts, impose serious questions about the practical use of I-MOS in circuits. However, as the i-lengths are scaled further or if Ge is used, hot carrier effects are expected to have a lesser impact because of reductions in the supply voltage (and a corresponding reduction in the carrier energy). Buried channel devices, where the avalanche breakdown can be engineered to happen away from the critical gate oxide interface, are also expected to show much higher resistance to hot carrier effects albeit, at the expense of short-channel control. IV. RECESSED CHANNEL I-MOS DEVICES In Section II, it was pointed out that I-MOS devices have higher breakdown voltages than laterally fabricated p-i-n diodes with similar i-lengths. This was attributed to two main factors: 1) Finite voltage drop in the MOS part of the I-MOS transistor due to a comparatively low concentration of carriers. 2) Lower values of impact ionization coefficients in the surface versus the bulk of any semiconductor material. Previous studies about this difference in avalanche generation

5 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS) Part II EXPERIMENTAL RESULTS 81 Fig. 6. Basic device structure for the recessed channel p-type SOI version of the I-MOS fabricated in SNF. Recessed channel devices were used to explore the differences between surface and bulk breakdown coefficients in silicon devices. The fabrication process for recessed channel devices is shown in Fig. 7. Position of the avalanche breakdown region is indicated by the dotted black circle. coefficients have been inconclusive [16] and some have attributed this difference to a host of factors including surface scattering mechanisms [17], quantization [18] etc. Since scalability of the breakdown voltage might determine eventual acceptance of this technology, there was interest in determining whether surface scattering/quantization played any role in enhancing the breakdown voltage. In order to cause breakdown to happen in a region away from any interface, a recessed channel p-type I-MOS device (device structure shown in Fig. 6) was fabricated. Since avalanche breakdown occurred in the offset region (which was away from the interface), it was expected that the recessed channel devices would have avalanche coefficients similar to those in bulk Si. A brief processing sequence for the recessed channel structure is illustrated in Fig. 7. The remaining process followed the same sequence as the conventional I-MOS (described in Fig. 1) with the exception that an oxide wet etch was done to remove the LTO before the source implantation step. The fabricated recessed p-channel I-MOS devices showed similar abrupt transitions from the OFF state to the ON state with subthreshold slopes of less than 10 mv/dec. Fig. 3 compares the breakdown voltages in the recessed channel structure, the conventional I-MOS structure and simple two terminal p-i-n diodes as a function of the i-length. It is clear that the recessed channel structure has a much lower breakdown voltage than the corresponding I-MOS device and matches the p-i-n breakdown voltage more closely. This indicates that in order to get to the lowest possible breakdown voltages in the I-MOS, recessed channel devices may have to be used. Recessed channel devices were also observed to have lower hot carrier shifts than corresponding I-MOS devices. The reason for this is not completely clear at this time but it is speculated that this might be because of a reduction in the impact-ionization threshold energy. This causes carriers to lose energy to impact ionization more efficiently thereby decreasing the injection efficiency. V. GERMANIUM P-I-N RESULTS As explained in Part I of this work, Ge (or an even lower bandgap material) would be the material of choice for the I-MOS because of much higher impact ionization generation rates. However, there has been no previous experimental data for breakdown voltages in narrow Ge p-i-n diodes. This lack of data can be primarily attributed to the lack of detailed processing knowledge (such as dopant activation, contacts and isolation) in Ge. A study was undertaken to understand the dependency of the breakdown voltage on the i-length in bulk Ge p-i-n diodes. Isolation of the adjacent lateral p-i-n diodes in Ge was achieved by growing a thin oxynitride layer [19] for surface passivation followed by the deposition of a 0.4 m thick LTO layer and patterning of the oxide to expose the active area. Dopant activation studies were carried out in Ge [20] to get high active concentrations of n and p-type dopants. Rapid thermal annealing (RTA) of implanted dopants (boron and arsenic) in Ge resulted in active concentrations exceeding 5. The boron profiles showed no significant diffusion and closely match the as-implanted profile but significant diffusion was observed for the arsenic profile (spreading resistance probe profiles are shown in [20]). Active area patterning was followed by a lithography step for the n implant (4 dose of arsenic). Lithography for the p implant then followed. In the next step, after the corresponding lithography steps and rapid thermal annealing, LTO was deposited as the inter-layer dielectric followed by contact lithography and etch. Ti (0.1 m)/al (0.4 m) was sputtered for the contact and metal pads followed by metal lithography and etch. The process was followed by an FGA anneal at 400 C for 1h. The fabricated Ge p-i-n diodes showed a lot of excess perimeter dependent leakage, which indicated that the surface was not passivated well. This leakage component can be eliminated by using a Ge on insulator (GOI) substrate. High leakage precluded extracting accurate breakdown voltages at room temperature. Low temperature measurements (done at 100 K) were used to reduce this leakage and extract accurate breakdown voltages for the different p-i-n diodes. Fig. 8 shows the experimental avalanche breakdown voltage as a function of the i-length in bulk Ge and other materials and compares it to MEDICI simulations (i-length as being defined as the length of i-region between the points at which the n and p type doping fall below ). It should be noted that the MEDICI simulations correspond to room temperature breakdown voltages while the experimental data in Ge corresponds to 100K values. At lower temperatures, due to reduction in optical-phonon scattering events, the breakdown voltages are lower but this reduction is expected to be less than 30% for i-lengths less than 1 m [3]. These results show that the experimental breakdown voltages in Ge at least a factor of 2 lower than those in Si and match the simulated values accurately down to m. In order to extract the breakdown voltages at smaller i-lengths, it might be necessary to develop a shallow junction technology for Ge or employ MBE or other techniques to grow abrupt p-i-n diodes. At this point, it should be pointed out that it is remarkable that local models are so accurate in estimating the breakdown voltage in Si, GaAs and Ge (Fig. 8) in spite of significant nonlocal dead-space effects [18] that have been shown to play an important role at these small dimensions. The dead-space effect (caused by the finite distance that the carriers have to travel in the high field region before they can cause impact ionization) can reduce the value of the impact-ionization generation

6 82 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 Fig. 7. (a) Processing sequence for the recessed channel device. A patterned oxide was used as a hard mask to etch the silicon. (b) This was followed by sacrificial and gate oxidations and then by LPCVD polysilicon deposition. Care was taken to ensure that the poly overlaps the oxide by at least 0.1 m. (c) The remaining processing steps follow that of a conventional I-MOS device (d), shown in Fig. 1. Fig. 8. Experimental breakdown voltages for bulk germanium p-i-n diodes and comparison to silicon and GaAs data. Germanium diodes were measured at 100K in order to reduce the dark current and clearly observe breakdown. Also shown are MEDICI simulations at room temperature. Experimental values match simulations very well for all materials. The breakdown voltages in germanium are approximately a factor of 2 3 lower than those in silicon. rates below the value predicted by the local theory. Thus the local field model overestimates multiplication, especially at low biases. This effect is more dominant in p-n junctions than in p-i-n junctions. However, in ultra small p-n (and p-i-n) junctions, carriers also have a higher probability of not suffering optical phonon collisions and consequently it is easier to get to the ionization threshold energy. This velocity (and the resulting impact-ionization) overshoot effect tends to cancel the nonlocal dead space effect so that the breakdown voltages are reasonably predicted by the local field model [19], [20]. VI. DISCUSSIONS AND CONCLUSION In conclusion, p-channel Si I-MOS devices were fabricated and showed extremely abrupt transitions from the OFF state to the ON state with a subthreshold slope of less than 10 mv/dec. These devices also showed significant hot carrier effects resulting in shifts and degradation of the subthreshold slope with repeated measurements. The initial nmos devices fabricated were not stable because the hot carrier damage in these large geometry high voltage devices was much worse in nmos than in pmos devices. Monte Carlo simulations revealed that the hot carrier effects were caused by holes (electrons) underneath the gate in pmos (nmos) devices and thereby explained the relative significance of the hot carrier effects in pmos versus nmos transistors. The p-channel I-MOS devices showed much higher values of the breakdown voltage than those obtained from simple two terminal p-i-n diodes with equivalent i-lengths. This was attributed to surface effects on impact ionization coefficients and breakdown voltage. Experimentally fabricated recessed channel devices with breakdown occurring in the bulk showed lower breakdown voltages than the corresponding surface channel devices. In order to reduce the breakdown voltage needed for device operation, lateral p-i-n devices were fabricated in Ge. These devices showed much lower values of breakdown voltage than corresponding Si devices and provided good fits to MEDICI simulations. It should be noted that the experimental results that were discussed do not negate any of the advantages of the I-MOS transistor. The hot carrier problem in the p-channel and the lack of stability in the n-channel I-MOS are simply a consequence of the larger dimensions of I-MOS transistors fabricated in our laboratory (and consequently higher operating voltages). When the device dimensions are scaled and if Ge is used in the I-MOS, hot carrier effects are expected to be significantly lower. This is because the barrier heights can be made significantly higher than the ionization threshold energies (0.8 ev) [14] and consequently it becomes easier for the carriers to lose energy to impact ionization before thermionic emission events. Thus, as in CMOS, hot carrier effects are expected to reduce significantly in the I-MOS as operating voltages are reduced below energy barrier heights for thermionic emission into the gate dielectric. In addition, as gate oxides are scaled into the direct tunneling regime, hot carrier degradation becomes less of a problem be-

7 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS) Part II EXPERIMENTAL RESULTS 83 cause the carriers can simply escape through direct tunneling without spending any time in the oxide [15]. However, introduction of high-k gate dielectrics may push operation into the Fowler-Nordheim regime and can make reliability issues worse since the carrier energy loss at the polysilicon/metal gate becomes higher than in the direct tunneling regime. Higher hot carrier injection efficiency in the I-MOS at higher operating voltages could be exploited for potential use in low power Flash memories. Also, even though Ge is the desired material of choice for lower breakdown voltages, strained-si could also be used as the substrate material for the I-MOS. Lower bandgaps and higher impact ionization rates in strained-si could potentially lead to comparable voltages in strained- Si and Ge. ACKNOWLEDGMENT The authors gratefully acknowledge Prof. K. Saraswat, Prof. R. Dutton, S. Jain, Y. Jono, R. Shenoy, Y. Liu, and P. Kalavade for useful discussions and directions. They would also like to thank the SNF staff for assistance during device fabrication. REFERENCES [1] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, I-MOS: A novel semiconductor device with a subthreshold slope lower than kt/q, in IEDM Tech. Dig., 2002, pp [2] B. C. DeLoach Jr, The IMPATT story, IEEE Trans. Electron Devices, vol. 23, no. 7, pp , Jul [3] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, [4] S. Millidge, D. C. Herbert, M. Kane, G. W. Smith, and D. R. Wright, Non-local aspects of breakdown in p-i-n diodes, Semicond. Sci. Technol., vol. 10, no. 3, pp , [5] Galene III User Guide, Version 3.2. [6] Y. Keesom, J. M. Hinckley, and J. Singh, Theoretical study of the threshold energy and impact ionization coefficient for electrons in Si Ge, Appl. Phys. Lett., vol. 64, no. 22, pp , May [7] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell, in IEDM Tech. Dig., Dec. 1995, pp [8] S. Mahapatra, S. Shukuri, and J. Bude, CHISEL flash EEPROM. I. performance and scaling, IEEE Trans. Electron Devices, vol. 49, no. 7, pp , Jul [9] D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, The scaling properties of CHISEL and CHE injection efficiency in MOSFET s and flash memory cells, in IEDM Tech. Dig., Dec. 1999, pp [10] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Flash memory cells-an overview, Proc. IEEE, vol. 85, no. 8, pp , Aug [11] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, Impact ionization MOS (I-MOS) Part I: Device and circuit simulations, IEEE Trans. Electron Devices, vol. 52, no. 1, pp , Jan [12] C. Hu et al., Lucky-electron model of channel hot-electron injection in MOSFETs, IEEE Trans. Electron Devices, vol. 31, no. 9, pp , Oct [13] S. Ogura, A. Hori, J. Kato, S. Odanaka, K. Akamatsu, M. Yamanaka, M. Kojima, and H. Kotani, A novel step stack NOR cell for low voltage flash, in VLSI Symp. Tech. Dig., 1998, pp [14] W. T. Tsang, Lightwave Communications Technology. New York: Academic, [15] K. F. Schuegraf, D. Park, and C. Hu, Reliability of thin SiO at directtunneling voltages, in IEDM Tech. Dig., 1994, pp [16] C. Jungemann, S. Yamaguchi, and H. Goto, Is there experimental evidence for a difference between surface and bulk impact ionization in silicon?, in IEDM Tech. Dig., 1996, pp [17] J. W. Slotboom, G. Streutker, G. J. T. Davis, and P. B. Hartog, Surface impact ionization in silicon devices, in IEDM Tech. Dig., 1987, pp [18] M. V. Fischetti, S. E. Laux, and E. Crabbe, Understanding hot-electron transport in silicon devices: Is there a shortcut?, J. Appl. Phys., vol. 78, no. 2, pp , [19] D. J. Hymes and J. J. Rosenberg, Growth and materials characterization of native germanium oxynitride thin films on germanium, J. Electrochem. Soc., vol. 135, no. 4, pp , Apr [20] C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, Activation and diffusion studies of ion-implanted p and n dopants in germanium, Appl. Phys. Lett., vol. 83, no. 16, pp , Oct [21] K. Gopalakrishnan, R. Woo, R. S. Shenoy, Y. Jono, P. B. Griffin, and J. D. Plummer, Novel very high injection efficiency structures based on the directed BBHE mechanism for ultra low power flash memories, IEEE Electron Device Lett., submitted for publication. [22] B. E. A. Saleh, M. M. Hayat, and M. C. Teich, Effect of dead space on the excess noise factor and time response of avalanche photodiodes, IEEE Trans. Electron Devices, vol. 37, no. 11, pp , Nov Kailash Gopalakrishnan was born in Bombay, India. He received the B.S. degree from the Indian Institute of Technology, Bombay, India, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA. Since July 2004, he has been a Research Staff Member at the IBM Almaden Research Center, San Jose, CA. His main research interests are novel logic and memory devices, device modeling and simulation, self-assembly and nanoimprint lithography. Raymond Woo was born in Paoli, PA in He received the B.S.E. degree in electrical engineering and computer science from Duke University in He is currently pursuing the Ph.D. degree with the Electrical Engineering Department, Stanford University, Stanford, CA. He is a National Science Foundation Graduate Research Fellow. Christoph Jungemann (M 97) received the Dipl.-Ing. and the Dr.-Ing. degrees in electrical engineering in 1990 and 1995, respectively, from the RWTH Aachen (Technical University of Aachen), Aachen, Germany and the venia legendi for Theoretische Elektrotechnik in 2001 from the University of Bremen, Bremen, Germany, respectively. From 1990 to 1995 he was a Research and Teaching Assistant at the Inst itut für Theoretische Elektrotechnik, RWTH Aachen. From 1995 until 1997 he was with the Research and Development facility of Fujitsu Limited, Kawasaki, Japan. He served as a Chief Engineer at the Institut für Theoretische Elektrotechnik und Mikroelektronik, University of Bremen, from 1997 until From 2002 to 2003 he spent a one-year sabbatical at the Center for Integrated Systems, Stanford University, Stanford, CA. Since 2003, he has been a Research Associate at the Technical University of Braunschweig, Braunschweig, Germany. His main research interests are full-band MC simulation of Si and SiGe devices, numerical device modeling, transport in inversion layers, and noise modeling. Peter B. Griffin received the B.E. and M.E. degrees from University College, Cork, Ireland, in 1981 and 1983, respectively, and the Ph.D. degree from Stanford University, Stanford, CA, in He currently with Stanford University. His research interests include process integration and scaling of MOS transistors, compound semiconductors, and biomems.

8 84 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 James D. Plummer (M 71 SM 82 F 85) was born in Toronto, ON, Canada. He received the B.S. degree from the University of California, Los Angeles, and the M.S. and Ph.D degrees in electrical engineering from Stanford University, Stanford, CA. He is currently the John Fluke Professor of Electrical Engineering, the Frederick E. Terman Professor of Engineering, and Dean of the School of Engineering at Stanford University. He has authored or coauthored over 300 technical papers. His current research interests focus on silicon devices and technology. He is particularly interested in the limits of silicon devices and technology, new application areas for chips, and in exploring possible replacement technologies for silicon chips. He consults for and serves on the boards of a number of semiconductor companies. Dr. Plummer has received three Best Paper Awards at the International Solid State Circuits Conference. In 1991, he received the Solid State Science and Technology Award from the Electrochemical Society. He has also received several teaching awards at Stanford University. He was elected to the National Academy of Engineering in 1996, and recently received the Semiconductor Industry Association s 2001 University Research Award.