IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY Impact Ionization MOS (I-MOS) Part I: Device and Circuit Simulations

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY Impact Ionization MOS (I-MOS) Part I: Device and Circuit Simulations Kailash Gopalakrishnan, Peter B. Griffin, and James D. Plummer, Fellow, IEEE Abstract One of the fundamental problems in the continued scaling of transistors is the 60 mv/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mv/dec or lower and ON 1 ma mat 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices. Index Terms Avalanche, avalanche photodiode (APD), gate control of impact ionization, impact-ionization avalanche transit-time (IMPATT), germanium, hot carriers, impactionization (I-MOS), kt/q, low static power, modulated breakdown, MOSFET, nonlinearity, p-i-n, silicon, subthreshold slope, 5 mv/dec. I. INTRODUCTION IN the past 50 years of the semiconductor industry, technology improvements have enabled transistor feature sizes to be scaled at a rate of approximately 0.7 every two years, a law that has become known as Moore s law [1], [2]. This reduction in the minimum transistor feature size has demanded a corresponding reduction in the supply voltage at which the transistor operates. Supply voltage scaling is needed in order to reduce the dynamic power of the transistors and to ensure reliable operation. Scaling achieves performance enhancement through a combination of reduced capacitances, increased drive currents and scaled. The drive current per unit m width for advanced CMOS transistors [3] is given by (1) - (1) where is a constant of proportionality, is a fitting parameter and has a value between 1 and 2 (and depends on the channel Manuscript received August 2, 2004; revised November 1, The review of this paper was arranged by Editor T. Skotnicki. K. Gopalakrishnan was with Stanford University, Stanford, CA USA. He is now with IBM Almaden Research Center, San Jose, CA USA. P.B. Griffin and J.D. Plummer are with Stanford University, Stanford, CA USA. Digital Object Identifier /TED length) and is the threshold voltage. It is apparent, from (1), that in order to maintain or enhance, needs to be reduced at least as rapidly as. However, in conventional MOS transistors, the subthreshold slope, (defined as ), of the drain current versus gate voltage is limited by the diffusion of carriers from the source to the channel of the device. Therefore, the fermi-dirac distribution of the carriers in the source places a thermodynamic limit of kt/q on the subthreshold slope where k is the Boltzmann s constant and T is the absolute temperature. In any transistor with a subthreshold slope at zero, is given by This current is known as the static or the subthreshold leakage current of the transistor since it represents the amount of current flowing in logic gates (such as inverters) in the quiescent state. Reduction of the and with scaling has therefore caused to increase exponentially [29]. In addition, the number of transistors per chip has doubled every two years [2], [4] and both these factors have caused an exponential rise in the leakage power of the chip. It is possible to view the subthreshold slope of a transistor as the gate controlled nonlinearity of the system [5], [6]. Any attempt to modify the subthreshold slope must necessarily involve either modifying the mode of carrier injection from diffusion based to tunneling based mechanisms or steepening the nonlinearity using an amplifier [29]. Using an amplifier to amplify the ON state and suppress the OFF state seems like an interesting solution but this approach has to solve the following major challenges. 1) The amplification mechanism must be internal to the device and must arise from some gain mechanism within the device. 2) The devices must not latch up and a fast mechanism like drift, rather than recombination [10], must remove all the injected carriers when the device switches from the ON to the OFF state. 3) And finally, the most fundamental challenge arises from the understanding that there is a finite bandwidth associated with every gain mechanism and, depending on the magnitude of the gain desired, this gain-bandwidth product may impose fundamental limitations on intrinsic device switching speed. We find one such gain mechanism that satisfies all of the above conditions is impact-ionization related breakdown. When a p n junction diode is used in the post-breakdown mode (i.e., with voltages higher than ), the delay is only proportional (2) /$ IEEE

2 70 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 to the log of the desired gain and is very fast [11], [12]. Thus gated - diodes pulsed into breakdown can show subthreshold slopes much lower than kt/q and can potentially be very fast because carriers can be easily removed by drift. The I-MOS (impact-ionization MOS) uses modulation of the avalanche breakdown voltage of a gated - - structure in order to switch from the OFF state to the ON state and vice-versa. Insulated gate avalanche transistors have been proposed before [32] for use as gated IMPATT oscillators. However, it was never recognized that these devices can have steeper than kt/q transitions. Our approach exploits the ability to create avalanche breakdown in lower bandgap materials at low voltages in a novel structure in order to ensure that the overall operating voltage of these devices is low. II. DEVICE STRUCTURE: THEORY AND PHYSICS The basic device structure for the n-channel version of the I-MOS [29] is shown in Fig. 1 in an silicon-on-insulator (SOI) implementation. Bulk structures work in a similar fashion but SOI devices were simulated (and later fabricated) because of the ease in designing isolation in transistors with both p and n regions. In this n-channel device, the p is the source and the n is the drain because the p-i-n diode is always reverse biased. The device is a gated p-i-n diode and works by modulation of its channel length. At low, there is no inversion layer under the gate and the effective channel length is the entire intrinsic region. The electric field under these conditions is below breakdown because only a fraction of the source/drain voltage gets applied across the i-region outside the gate. Consequently, is limited by the reverse-leakage current of the p-i-n diode. As is increased, an inversion layer forms under the gate and this reduces the effective channel length of the device. With higher and higher, an increasing fraction of falls across the i-region outside the gate and therefore increases the lateral electric fields in that region. In addition, the transverse electric field also increases with increasing gate voltage. The device breaks down when the ionization integral becomes unity [13] i.e. where and are the position (and hence electric field) dependent ionization coefficients and will be explained in some detail in Section III. Note that while the formation of the inversion layer under the gate may be limited by the normal 60 mv/dec limit, the strong dependency of the impact-ionization coefficients on the electric field and the feedback inherent in the avalanche multiplication process produce a very steep subthreshold slope in the I-MOS device. A p-i-n structure as opposed to a p-n structure is used in order to reduce the electric fields required for avalanche breakdown compared to a p n junction. In p n junctions with narrow depletion widths, the electric fields at breakdown are much higher. This increases the probability for band-to-band tunneling (BTBT) and may result in devices with subthreshold slopes worse than kt/q. Conceptually, the I-MOS transistor may be regarded as a combination of a diode and a MOS transistor. These two (3) Fig. 1. Basic device structure for the n-channel SOI version of the I-MOS. This n-channel device has an overlap with the drain of the device (n ) and an offset toward the source (p ) side of the device The I-MOS uses modulation of the channel length to switch from the OFF to the ONstate via avalanche breakdown. Subthreshold characteristics are shown in Fig. 2. elements are however not discrete and their operation is closely linked. The vertical gate induced field and the MOS surface carrier concentration affect the breakdown voltage of the diode and the surface concentration of carriers in the ON state of the MOS transistor depends on the number of carriers injected by the avalanche breakdown mechanism in the diode. III. DEVICE SIMULATIONS: BASICS OF DEVICE OPERATION The rate at which electron-hole pairs are generated and its electric-field (energy) dependency depend strongly on the material and are described by impact ionization coefficients. Germanium (Ge) was chosen as the material of choice in the I-MOS because its for both electrons and holes are much higher than in Si [14], [15]. In Si, is much lower than [16]. This retards the feedback process, thereby increasing the breakdown voltage. In Ge, high and symmetric impact-ionization coefficients ensure that the transition from the OFF state to the ON state is as abrupt as possible and that the breakdown voltage is much lower than in Si. The impact ionization coefficients for both electrons and holes depend on the electric field and are typically modeled using the following expression [17]: where is the critical electric field required for avalanche multiplication [13], is the electric-field component in the direction of the current flow and is the asymptotic value of the avalanche coefficient. The generation rates depend on the seed carrier currents ( and ) and on the impact-ionization coefficients as described in [8]. Simulations were done in Avant!/TMA MEDICI on a Ge I-MOS device. Impact-ionization coefficients were calibrated to available experimental data on Ge devices [14], [15]. Fig. 2(a) shows a typical versus simulated curve for a device with a 25-nm (gate-length) and 25-nm (i-region outside the gate), with an appropriately chosen gate work-function (4.17 ev) for a drain/source voltage of 1 V( and V). These simulations included all models used to describe common device behavior including both impact-ionization and BTBT and were done at 400 K in (4)

3 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS): PART 1 71 Fig. 2. (a) MEDICI simulated I versus V characteristic for a n-channel Ge I-MOS device shown in Fig. 1 with L = L =25nm in Mode 1 (V 0:15 V for V =0, V < 0)atT = 400 K. Simulations show that the subthreshold slope is very small ( 5 mv/dec). (b) Electron and hole current flow patterns in an I-MOS in the ON state. Current underneath the gate is predominantly an electron current and avalanche breakdown happens in the i-region, not underneath the gate. MOS devices (double gate simulated) have lower ON currents even at 300 K for the same V. order to capture the worst-case scenario. It was also assumed that the avalanche coefficients of carriers near the surface are the same as the values in the bulk of the material. The simulated subthreshold slope for this device was approximately 5 mv/dec. The device shows an excellent ON to OFF ratio with ON current ma m, OFF current na m and threshold voltage V for the worst-case set of simulations. It should be noted that the polarities of the voltages required for the ON state are necessary because the threshold voltage of the I-MOS transistor depends on the channel potential which is more strongly coupled to the drain. Operation of the I-MOS device at normal operating voltages V would increase the threshold voltage by for the same gate workfunction but it may be possible to get the threshold voltage back to the desired value V by using a different gate-workfunction or a threshold correction implant. Also, as can be noted from Fig. 2(b), the current underneath the gate is predominantly a surface electron current and the i-region outside the gate suffers an avalanche breakdown and has position dependent electron and hole currents. This mode of breakdown is referred to as Mode 1. As the gate voltage is swept negative for the n-channel I-MOS, we notice a second form of breakdown in the versus characteristics in Fig. 3. The subthreshold slope for this mode of breakdown is around mv/dec. In this mode of breakdown, the negative gate voltage induces holes in the i-region. This increases the electric fields in the field-induced -n junction at the right edge of the gate and consequently an avalanche breakdown occurs under a sufficiently high applied voltage. This mode of breakdown is referred to as Mode 2. Even though the subthreshold slope is also abrupt under these conditions for the device shown in Fig. 1, Mode 2 is theoretically more susceptible to BTBT related soft breakdown effects [30] (depending on the relative threshold fields and applied biases) because it involves the breakdown of a p-n junction (and not a p i n junction). Simulations of room temperature characteristics of the various modes of breakdown of the I-MOS show much lower OFF currents (due to lower leakage) and much higher ON currents (due to the higher mobility at lower temperatures) for both modes of breakdown. The above device simulations were done with a standard local field impact-ionization model [17] that uses local electric fields to determine the impact-ionization generation rates. Previous studies in Si and GaAs have shown that this model is remarkably accurate in predicting the breakdown voltages in p-i-n diodes down to 25-nm i-lengths in spite of significant nonlocal effects [18] [20]. However, there has been no previously available experimental data in Ge p i n diodes to validate some of the above simulations. Therefore the best available estimates of the avalanche multiplication coefficients of Ge in the local field impact ionization model have been used to predict I-MOS device characteristics. In Part II of this paper, we will present some of the experimental values of the breakdown voltage obtained in laterally fabricated Ge p i n diodes and detailed comparison of simulations to experimental data in a variety of different materials. Also, Section VII in this paper will touch upon the implications of a different breakdown voltage on the power/performance trade off in I-MOS devices. It should be mentioned that the I-MOS in Mode 2 is in principle very similar to the Esaki FET [30] since it can involve BTBT. The analysis of Esaki FETs in low bandgap materials will be discussed in detail elsewhere [31]. In Mode 1, is chosen so that the breakdown necessarily involves avalanche breakdown. In this regard, scaling of the I-MOS can involve only scaling of (which results in reduced capacitances and faster switching speeds). cannot be scaled indefinitely since the threshold field for impact-ionization increases with scaling [8]. Therefore, scaling eventually causes BTBT to dominate and the I-MOS in Mode 1 would then be no different from an Esaki tunneling FET or Mode 2. IV. ON CURRENT CHARACTERISTICS In Figs. 2 and 3, conventional Si mobility models have been used to model the ON state due to lack of any knowledge of surface mobility of carriers in Ge. Even with this assumption, it can

4 72 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 Fig. 3. (a) MEDICI simulated I versus V characteristics and (b) current flow patterns for a n-channel Ge I-MOS device shown in Fig. 1 with L = L = 25 nm in Mode 2 (V 0:3 V) at T = 400 K. Simulations show that the subthreshold slope is very small ( mv/dec). Mode 2 is more susceptible to soft breakdown than Mode 1 because it involves the breakdown of a p-i-n junction and not a p n junction. Fig. 4. Simulated I versus V characteristics of an I-MOS transistor with V 0 V =0:8 V(without contact resistance). Unlike a normal MOS transistor, the I versus V characteristics do not saturate. Below the drain breakdown voltage, the current falls to the reverse leakage current of a p i n diode. Above the drain breakdown voltage, the current is exponential with voltage and is due to modulation of the charge injected by the diode with the drain voltage. be seen in Fig. 2, that in the ON state of the I-MOS is higher than of conventional MOS transistors with similar gate overdrives. This is easy to understand by realizing that the threshold voltage and the ON state of the MOS transistor and that of the I-MOS occur at different values of surface carrier concentration. In the ON state of the I-MOS, the carrier concentration under the gate is typically much higher (at comparable ) in order to enable a significant fraction of the to be applied across. MEDICI simulations showed that for the device in Fig. 1 with 25-nm gate lengths and i-length, surface carrier concentrations higher than cm may be necessary to initiate breakdown. Therefore, at the threshold voltage of the I-MOS transistor, the carrier concentration in the channel is much higher than the carrier concentration in the channel of a MOS transistor at its threshold voltage. Therefore, the ON current of the I-MOS transistor is much higher than the ON current of the MOS transistor for comparable gate-lengths. Fig. 4 shows versus characteristics of the I-MOS (without contact resistance) when the is held greater than the breakdown voltage for a given gate overdrive V. It is clear that, in the I-MOS transistor, unlike in a normal MOS transistor, there is no saturation in the versus characteristics. This effect can be explained by modeling the ON current of the diode as the ON current of the MOS-part of the I-MOS transistor but with a carrier concentration at the source that is given by the charge injected by the diode i.e. where the simplifying assumption has been made that all the injected carriers travel at the saturation velocity,.as is increased for a fixed, some part of the applied voltage falls across the diode that pushes it deeper into breakdown. This causes an increased number of carriers to be injected into the channel of the MOS transistor, which increases the ON current in spite of the fact that all the carriers travel at the saturation velocity. The nonsaturation of the versus characteristics can have a significant impact on inverter delay for digital applications and on the transistor gain for analog applications. In digital applications, higher ON current at higher can increase the inverter switching speed but the increased channel (5)

5 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS): PART 1 73 the transverse electric field. There are circuit advantages to reducing as well and these will be explained in Section VII. It should be noted that the above simulations did not account for the effect of variations in on. This may be a reasonable assumption if is defined using a well-controlled sidewall spacer after gate definition. It should be noted that since the breakdown in the I-MOS transistor is a surface controlled effect, the short channel resistance is inherently higher. In UTBSOI and double gate transistors, the point of weakest control is the part of the Si body furthest away from the gate (center of the body for the double gate transistor). Therefore the SCE of the I-MOS transistor is better than that of the MOS transistor. Fig. 5. Simulated comparison of the V roll-off characteristics of a n-channel I-MOS (for different oxide thicknesses) and a MOS transistor (for a 1-nm thin oxide). An ultrathin body ground plane SOI template was used with the bottom oxide thickness as twice the top oxide thickness. I-MOS has better short-channel characteristics than a MOS transistor. It is possible to increase the oxide thickness by up to 3X for the same control of the channel. L is kept constant at 25 nm. conductance would lower the gain needed for analog applications. Higher electric fields in an I-MOS near the source of the device (due to proximity to a breakdown region) can also result in increased in nanoscale devices due to reduced back scattering [22]. V. SCE The I-MOS is theoretically more resistant to deleterious short-channel effects (SCEs) than a simple MOS transistor. This is because the I-MOS has a much longer channel length in the OFF state and can therefore shield the source region from the drain potential more effectively. In a MOS transistor, drain-induced barrier lowering (DIBL) arises because the drain depletion region can penetrate the channel and reduce the effective value of the barrier at the source [23]. In an I-MOS transistor, the band-diagram is monotonic from the source to the drain and is therefore not as susceptible to barrier lowering effects. DIBL should also be lower because only part of the applied voltage is responsible for DIBL. In order to verify the above claims, MEDICI simulations were done to compare the SCE of the I-MOS transistor with those of the MOS transistor. A standard ground-plane ultrathin body (UTB) SOI based template was used with the bottom gate grounded and the bottom oxide thickness set to twice the front gate oxide thickness. The oxide thickness of the MOS transistor was fixed at 1 nm and the oxide thickness of the I-MOS transistor was varied from 1 to 5 nm. Fig. 5 compares the variation in due to a variation in channel length for all the above cases. As predicted, is much better for the same value of the oxide thickness in the I-MOS transistor and it may be possible to increase the value of the oxide thickness by up to 3X and still have comparable SCE to the MOS transistor. A thicker oxide may obviate the need for the introduction of high- gate dielectrics, reduce poly-depletion and also increase the surface mobility by reduction of VI. TRANSIENTS IN THE VARIOUS AVALANCHE PROCESSES IN I-MOS As illustrated in Section I, devices that have internal gain mechanisms tend to latch-up and can exhibit considerable delay in switching from the ON state to the OFF state. There is no latch-up in the I-MOS because, with the gate switched off, the electric fields (and the carrier multiplication values) are reduced to below the breakdown values and there is no further carrier generation. In addition, the excess carriers in the device are removed by drift because of the high electric field in the p i n diode. In a conventional avalanche photodiode (APD), the diode exhibits a finite delay in turning off because the electric field in the i-region is unchanged even when the source of carriers is switched off. Thus, the turnoff mode of the I-MOS is fundamentally different from a conventional APD. Delay in switching from the ON state to the OFF state is of the order of the transit time. Avalanche based devices can also exhibit some delay in switching from the OFF state to the ON state and this delay strongly depends on whether the devices are operated in the pre-breakdown or the post-breakdown mode. There are two major components in switching ON a carrier plasma in a p n junction. 1) Statistical retardation delay: This is the delay in generating the seed carrier used to initiate the avalanche process and has been quantified previously to be negligible in the I-MOS [24], [25], [29], and 2) Avalanche build-up time: For devices that operate in the post-breakdown mode, the avalanche build-up delay required to get to the steady state is usually small and is of the same order of magnitude as the transit time of the device [26]. These modes of avalanche initiation and build-up have been observed in other high speed impact-ionization based devices including IMPATT and TRAPATT oscillators that operate at more than 200 GHz [27]. It is unclear, at this time whether there is any delay in the impact-ionization scattering event itself in Ge. This delay depends on the ionization cross-section versus carrier energy curve for Ge which is not known at this point. However, in all previous experimental instances of avalanche based devices, this delay component has been insignificant. In the n-channel version of the I-MOS, the gate overlaps the n region, which is the drain of the device. When the device is

6 74 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 1, JANUARY 2005 Fig. 6. Band diagrams along the surface during the turn on of the I-MOS device are shown for V =0V and V = 01 V. A gate pulse greater than the threshold voltage is applied (a). Initially the I-MOS is in the OFF state (b). When the gate voltage reaches its peak, carriers do not have time to respond to the gate pulse due to the very fast rise time of the pulse. Therefore capacitive coupling pulls the channel potential up with the gate voltage. This makes the quasi-fermi level for electrons in the channel lower than that in the drain (c). This causes a huge diffusion of carriers from the N drain into the channel (d) in a time comparable to the transit time of the device. switched to the ON state, as explained in Section II, it is necessary to form an inversion layer in order to cause breakdown. This would either require slow recombination-generation processes or for carriers to come from the drain region into the channel. This is counterintuitive since electrons typically prefer to travel to a higher potential and not away from it. MEDICI simulations were done to clarify the mode and the delay in the formation of the inversion layer in the I-MOS. Fig. 6 shows band-diagrams (simulated without impact-ionization) along the surface of the I-MOS device for three snapshots in time as the device is switched ON in a transient fashion [Fig. 6(a)]. When the gate is initially switched ON [Fig. 6(c)], the bands bend downwards due to capacitive coupling of the gate potential to the channel. This makes the channel potential and the electron quasi-fermi level fall to a lower potential than the drain potential making it easy for the electrons in the drain to spill over to the channel though diffusion [Fig. 6(d)]. Therefore, the inversion layer in the I-MOS can be formed in a timescale that is comparable to that in a normal MOS transistor. VII. I-MOS INVERTER DESIGN Devices that have ultralow static leakage are most useful if one can design complementary logic gates with them. Inverters are the basic building blocks of all complex circuits. Inverters and other complementary I-MOS devices can be simply generated by moving the position of the gate [29]. One of the limitations of the I-MOS, that can impact its potential applications, is evident from Fig. 4. abruptly drops down to the reverse saturation current of the p i n diode as is reduced. This is because a finite is needed in order to maintain avalanche breakdown. Therefore if the I-MOS device were used to discharge a capacitor, the output voltage would discharge until it reaches the breakdown voltage ( )at which point there would be no further discharge of the voltage across the capacitor. depends on, the material, and Fig. 7. DC Transfer characteristics of the I-MOS inverter. The output voltage is higher than the input voltage range. Gain of approximately 2.5 is obtained which is good enough for digital applications. on other device parameters. Similarly, the output of an I-MOS inverter operating between and ground would not swing rail to rail (but instead from to ) due to the finite of both the n I-MOS and the p I-MOS device. This makes the design of an I-MOS inverter more complex. All logic gates have one fundamental requirement: that they allow cascadability. If the swing of a logic gate diminishes with every stage, then it is not possible to make logic circuits with it. Fortunately, it is possible to design the I-MOS inverter with output swings that are greater than or equal to input swings. Since the swing of the devices ( to ) is different than the supply rails, it is necessary to ensure that the following conditions are met. 1) When the input voltage is at, the n I-MOS must remain switched OFF and the p I-MOS should switch ON. In addition, the p I-MOS must charge the output to a voltage. 2) Similarly when the input voltage is at, the p I-MOS must remain switched OFF and the n I-MOS should switch ON. In addition, the n I-MOS must discharge the output to a voltage. Design of the I-MOS inverter involves multiple iterations for the desired values of the,, the transistor threshold voltages and supply voltage under the constraints imposed by of both the n I-MOS and p I-MOS devices and the cascadability conditions above. This process is made additionally complex by the fact that in turn depends on the transistor threshold voltages and the input voltages ( and ). MEDICI Circuit Analysis Module (CA-AAM) was used to design the inverter having designed functional n I-MOS and p I-MOS devices. was chosen to be 2.0 V and the swing was chosen to be V at 400 K and under these conditions, the output swing was greater than the input swing. Fig. 7 shows the DC transfer characteristics and output current of the above designed I-MOS inverter. As can be seen, is greater than and a gain of approximately 2.5 is obtained at the switching point, which might be sufficient for digital applications. The transfer characteristics are not as steep as in a CMOS inverter because does not saturate with. Previously [29], we have shown using simulations than a properly sized I-MOS inverter can have a FO delay at 400 K of approximately 10 ps with a static power that is at least

7 GOPALAKRISHNAN et al.: IMPACT IONIZATION MOS (I-MOS): PART 1 75 more difficult. One potential solution to this problem is to have a hybrid I-MOS and MOS circuit in order to make sure that in any series NMOS or PMOS stack, not more than 1 transistor is an I-MOS device. Fig. 8. Effective supply voltage V as a function of swing (1V ), breakdown voltage V and oxide thickness. Thicker oxides result in lower values of dynamic power dissipation and consequently permit large values of breakdown voltage. The effective supply voltage is much lower than the actual supply voltage because of a smaller swing. three orders of magnitude lower than CMOS. This FO delay is better than the FO delay that can be obtained in a ultrathin body SOI (UTB) MOS transistor at 400 K possibly because of a combination of various factors including higher and lower. The net dynamic power dissipation of an inverter driving a capacitance load is given by where is the effective supply voltage of a CMOS inverter driving. The dynamic power dissipation in an I-MOS inverter is much lower than the supply voltage would suggest because of the reduced swing. It is possible to further reduce the dynamic power dissipation by increasing the oxide thickness and thereby reducing the value of the load capacitance. As explained in Section V, we can increase the oxide thickness by 3X for the same short channel characteristics. Inverter FO delay is not affected because both and are scaled down in a similar fashion. Reducing also reduces voltage drops across the parasitic source/drain resistance. Considering all the factors mentioned above, Fig. 8 compares the effective supply voltage,, as a function of the minimum achievable breakdown voltage for different oxide thicknesses and swings. With much thicker oxides, I-MOS inverters with breakdown voltages even as high as 2 V show much lower dynamic power dissipation than CMOS even though the impact of higher voltages on reliability needs to be considered. In addition, dynamic power dissipation can be reduced further by making even smaller but noise margins are severely reduced. It should be mentioned that while it is indeed possible to design simple I-MOS inverters, designing more complex logic gates (NAND, NOR etc.) is more difficult since putting two I-MOS devices in series would increase the output levels. This would require higher for normal operation and makes cascading (6) VIII. CONCLUSION In conclusion, the I-MOS is a novel high-speed internal-gain mechanism based semiconductor device that has a subthreshold slope much lower than kt/q. The switching delays and the dynamic power dissipation in these devices are comparable to those of CMOS devices with comparable dimensions, with the added advantage of ultralow static power dissipation. I-MOS also has lower short channel effects than CMOS which can be traded off for reduced dynamic power dissipation and gate leakage. I-MOS thus has the potential to replace CMOS for low power and high performance digital applications. However, challenges lie ahead primarily in the reduction of breakdown voltage that would enable further scaling of the effective supply voltage. New approaches in circuit design may also be needed to account for the reduced output swing in these devices. In addition, it is anticipated that these devices will exhibit severe hot carrier effects since they operate at high fields and higher operating voltages than conventional MOSFETs. REFERENCES [1] H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Wesler, Nanoscale CMOS, Proc. IEEE, vol. 87, no. 4, pp , Apr [2] (2001) International Technology Roadmap for Semiconductors. International SEMATECH, San Jose, CA. [Online]. Available: WWW: [3] T. Sakurai and A. R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid-State Circuits, vol. 25, no. 4, pp , April [4] B. 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