Si838x Data Sheet. Bipolar Digital Field Inputs for PLCs and Industrial I/O Modules

Transcription

1 Bipolar Digital Fild Inputs for PLCs and Industrial I/O Moduls Th Si838x provids ight channls for 24 V digital fild intrfac to ithr sinking or sourcing inputs with intgratd safty ratd isolation. In combination with a fw xtrnal componnts, this provids complianc to IEC switch typs 1, 2, or 3. Th input intrfac is basd on Silicon Labs' ground-braking CMOS basd LED mulator tchnology which nabls th bipolar capability (sinking or sourcing inputs) with no VDD rquird on th fild sid. Th output intrfac to th controllr allows for low powr opration with 2.25 V opration capability. Ths products utiliz Silicon Laboratoris' propritary silicon isolation tchnology, supporting up to 2.5 kv RMS withstand voltag. This tchnology nabls high CMTI (50 kv/μs), lowr prop dlays and skw, rducd variation with tmpratur and ag, and tightr part-to-part matching. Product options includ paralll or srializd outputs. Cascading capability for a total of 128 channls (16x Si838x) is possibl with srial output option. Th Si838x offrs longr srvic lif and dramatically highr rliability compard to opto-coupld input solutions. Applications: Programmabl logic controllrs Industrial data acquisition Distributd control systms CNC machins I/O moduls Motion control systms Safty Rgulatory Approvals: UL 1577 rcognizd Up to 2500 V RMS for on minut CSA componnt notic 5A approval IEC VDE crtification conformity VDE CQC crtification approval GB KEY FEATURES Bipolar digital intrfac with 24 V sinking or sourcing inputs Eight total inputs in on packag High data rats of up to 2 Mbps Safty ratd intgratd isolation of 2.5 kvrms Low input currnt of 1 ma typ No VDD rquird on fild sid Status LEDs on paralll outputs High lctromagntic immunity Programmabl dbounc tims of up to 100 ms Transint immunity of 50 kv/μs Flow-through output configuration with ight outputs Option for SPI intrfac srializd outputs with daisy-chain capability Wid 2.25 to 5.5 V VDD opration Wid oprating tmpratur rang 40 to +125 C Compliant to IEC Typ 1, 2, 3 RoHS-compliant packags QSOP-20 silabs.com Smart. Connctd. Enrgy-frindly. Rv. 0.5

2 Ordring Guid 1. Ordring Guid Tabl 1.1. Si838x Ordring Guid Ordring Part Numbr Srial or Paralll Output Numbr of High- Spd Channls Low Pass Filtr Dlay Packag Typ Isolation Rating Si8380P-IU P 0 0 ms 20-QSOP 2.5 kvrms Si8382P-IU P 2 0 ms 20-QSOP 2.5 kvrms Si8384P-IU P 4 0 ms 20-QSOP 2.5 kvrms Si8388P-IU P 8 0 ms 20-QSOP 2.5 kvrms Si8380S-IU S 0 0 ms 20-QSOP 2.5 kvrms Si8380PF-IU P 0 10 ms 20-QSOP 2.5 kvrms Si8382PF-IU P 2 10 ms 20-QSOP 2.5 kvrms Si8384PF-IU P 4 10 ms 20-QSOP 2.5 kvrms Si8380PM-IU P 0 30 ms 20-QSOP 2.5 kvrms Si8382PM-IU P 2 30 ms 20-QSOP 2.5 kvrms Si8384PM-IU P 4 30 ms 20-QSOP 2.5 kvrms Si8380PS-IU P ms 20-QSOP 2.5 kvrms Si8382PS-IU P ms 20-QSOP 2.5 kvrms Si8384PS-IU P ms 20-QSOP 2.5 kvrms silabs.com Smart. Connctd. Enrgy-frindly. Rv

3 Functional Dscription 2. Functional Dscription 2.1 Thory of Opration Th opration of a Si838x channl is analogous to that of a bipolar opto-couplr, xcpt an RF carrir is modulatd instad of light. This simpl architctur provids a robust isolatd data path and rquirs no spcial considrations or initialization at start-up. A simplifid block diagram for a singl Si838x channl is shown in th figur blow. This product nabls 24 V bipolar digital inputs to b connctd to its input through a rsistor ntwork which acts as a voltag dividr. Th inputs can b sourcing or sinking typ. To nabl this functionality, thr is a zro drop bridg and an LED mulator at th front nd that drivs an OOK (On-Off Ky) modulator/dmodulator across th capacitiv isolation barrir. On th output sid, th dbounc block controls th amount of dbounc dsird. Thr ar four dbounc dlay tim options availabl: no dlay, or dlays of 10, 30, or 100 ms. In addition, th usr can us th SPI control to program usr-spcific dbounc mods as xplaind in Sction Dbounc Filtring Mods. Th usr-spcific dbounc programming is only availabl on th product option with SPI intrfac. A COM HF Transmittr Modulator CMOS isolation barrir Dmodulator Dbounc VDD B Figur 2.1. Simplifid Channl Diagram 2.2 Srial Priphral Intrfac Th Si8380S includs a Srial Priphral Intrfac (SPI) that provids control and monitoring capability of th isolatd channls using a commonly availabl microcontrollr protocol. Th dirct-mappd rgistrs allow an xtrnal mastr SPI controllr to monitor th status of th ight PLC channls, as wll as to control th dlay and filtring mods for th dbounc of ach channl. Additionally, support is providd to asily daisy-chain up to sixtn PLC dvics. Each of ths daisy-chaind dvics may b uniquly addrssd by on mastr SPI controllr SPI Rgistr Map Th addrssabl SPI rgistrs includ on ight-bit rgistr to rflct th status of ach of th ight channls, which is rad-only. Also, four additional rgistrs provid two bits to spcify th dbounc dlay, and two bits to spcify th dbounc filtring mod for ach of th ight channls. Ths usr accssibl SPI rgistrs ar illustratd in th following tabl. Tabl 2.1. Si838x SPI Rgistr Map Nam Addrss Accss Dscription CHAN_STATUS 0x0 R Currnt valu of ach of th ight PLC channls {PLC[7:0]} DBNC_MODE0 0x1 R/W Mod control bits for th first four channl dbounc filtrs organizd as: {md_ch3[1:0],md_ch2[1:0],md_ch1[1:0],md_ch0[1:0]} DBNC_MODE1 0x2 R/W Mod control bits for th scond four channl dbounc filtrs organizd as: {md_ch7[1:0],md_ch6[1:0],md_ch5[1:0],md_ch4[1:0]} DBNC_DLY0 0x3 R/W Dlay control bits for th first four channl dbounc filtrs organizd as: {dly_ch3[1:0],dly_ch2[1:0],dly_ch1[1:0],dly_ch0[1:0]} DBNC_DLY1 0x4 R/W Dlay control bits for th scond four channl dbounc filtrs organizd as: {dly_ch7[1:0],dly_ch6[1:0],dly_ch5[1:0],dly_ch4[1:0]} silabs.com Smart. Connctd. Enrgy-frindly. Rv

4 Functional Dscription SPI Communication Transactions SPI communication is prformd using a four wir control intrfac. Th four Si838x dvic pins utilizd for SPI includ: SCLK (input) th SPI clock NSS (input) activ low dvic slct MOSI (input) mastr-out-slav-in MISO (output) mastr-in-slav-out Additionally, a fifth wir SDI_THRU (output) is providd as an Si838x dvic pin to facilitat daisy chaining. An Si838x SPI communication packt is composd of thr srial byts. In this squnc, byt0 is th control byt, and spcifis th opration to b prformd as wll as th dvic to b slctd in a daisy chain organization. Th CID[3:0] fild should b st to all zros by th SPI mastr in non-daisy-chaind opration. Nxt, byt1 spcifis th addrss of th intrnal Si838x SPI rgistr to b accssd. Th final byt in th packt consists of ithr th data to b writtn to th addrssd Si838x SPI rgistr (using MOSI), or th data rad from th addrssd Si838x SPI rgistr (using MISO). Dtails of th SPI communication packt ar prsntd in th following figur for an Si838x SPI writ transaction. NSS SCLK MOSI Control[7:0] Addrss[7:0] Data[7:0] Control Byt BRCT R/Wb 0 0 CID[0] CID[1] CID[2] CID[3] Addrss Byt A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Data Byt D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] BRCT R/Wb 1 - broadcast (writ) 0 - only addrssd part (writ) Ignord on rads 1 - rad 0 - writ CTL[5:4] Rsrvd (st to 0,0) CID[3:0] Daisy-chaind part ID (0) is closst to th mastr MOSI. Accomplishd by dcrmnting th CID as it passs through to th nxt Si838x dvic in th daisy chain on SDI_THRU Figur 2.2. SPI Communication Packt Structur, Writ Opration and Control Byt Structur Th SPI mastr will provid th timing of th signals and framing of th communication packts for all Si838x SPI inputs: NSS, SCLK, and MOSI. Data is communicatd from th SPI mastr to th Si838x using th MOSI signal. Th NSS and SCLK signals provid th ncssary control and timing rfrnc allowing th Si838x to discrn valid data on th MOSI signal. Data is rturnd to th SPI mastr by th Si838x utilizing th MISO signal only during th final byt of a thr byt SPI rad communication packt. At all othr tims, th MISO signal is tri-statd by th Si838x. Each of th ight bits for ths thr packts is capturd by th Si838x on ight adjacnt rising dgs of SCLK. Each fram of ight bits is composd within bounding priods whr th dvic slct, NSS, is dassrtd. Upon th rcption of th ight bits within a byt transaction, th dassrtion of NSS advancs th byt countr within th intrnal Si838x SPI stat machin. Should th transmission of an ight bit packt b corruptd, ithr with th dassrtion of NSS bfor th ighth rising dg of SCLK, or with th absnc of th dassrtion of NSS aftr th ighth rising dg of SCLK, th intrnal SPI stat machin may bcom unsynchronizd with th mastr SPI controllr. To r-stablish SPI synchronization with th Si838x, th SPI mastr may, at any tim, dassrt th SPI dvic slct signal NSS, and forc a clock cycl on SCLK. Whn unsynchronizd, th rising dg of SCLK whn NSS is dassrtd (high) r-initializs th intrnal SPI stat machin. Th Si838x will thn trat th immdiatly following ight bit SPI transaction aftr NSS is onc again assrtd as th first byt in a thr byt SPI communication packt. Any prcding communication packt will b abandond by th Si838x at th point synchronization is lost, and th NSS signal is dassrtd. This could occur at any point in th thr byt squnc of a SPI communication packt. On should not that abandoning a SPI writ opration arly, vn during th last byt of th thr byt SPI communication packt, will lav th dstination rgistr unchangd. Howvr, if th numbr of SCLK cycls xcds ight during th last byt of th thr byt SPI writ packt, th dstination Si838x rgistr may b corruptd. To rmdy both of ths situations, it is rcommndd that such a corruptd writ opration b rpatd immdiatly following rsynchronization of th SPI intrfac. silabs.com Smart. Connctd. Enrgy-frindly. Rv

5 Functional Dscription SPI Rad Opration Rfrring to Figur 2.2 SPI Communication Packt Structur, Writ Opration and Control Byt Structur on pag 3, in a SPI rad opration th control byt will only hav bit6 st to a 1 in a singl Si838x dvic organization (no daisy-chaining). For th Si838x, bit7 (th broadcast bit) is ignord during a rad opration sinc only on dvic may b rad at a tim in ithr a singl or daisy chaind organization. Th scond byt in th thr byt rad packt is providd by th SPI mastr to dsignat th addrss of th Si838x intrnal rgistr to b qurid. If th rad addrss providd dos not corrspond to a physically availabl Si838x intrnal rgistr, all zros will b rturnd as th rad valu by th Si838x. Th rad data is providd during th final byt of th thr byt rad communication packt to th qurying mastr SPI dvic utilizing th Si838x s MISO output, which rmains tristatd at all othr tims. Th SPI rad opration timing diagram is illustratd in th figur blow. NSS SCLK MOSI Control[7:0] Addrss[7:0] MISO RadData[7:0] Figur 2.3. SPI Rad Opration SPI Writ Opration Again rfrring to Figur 2.2 SPI Communication Packt Structur, Writ Opration and Control Byt Structur on pag 3, in a SPI writ opration th control byt may optionally hav bit7 (th broadcast bit) st to a 1. During a SPI writ opration, th broadcast bit forcs all daisy-chaind Si838x dvics to updat th dsignatd intrnal SPI rgistr with th supplid writ data, rgardlss of th Si838x dvic bing addrssd using th CID[3:0] fild of th control word. Th scond byt in th thr byt writ packt is providd by th SPI mastr to dsignat th addrss of th Si838x intrnal rgistr to b updatd. If th writ addrss providd dos not corrspond to a physically availabl Si838x intrnal rgistr, no intrnal Si838x SPI rgistr updat will occur. Th writ data is providd by th SPI mastr during th final byt of th thr byt writ communication packt. Th Si838x MISO output rmains tri-statd during th ntir SPI writ opration. Th SPI writ opration timing diagram is illustratd in th figur blow. NSS SCLK MOSI Control[7:0] Addrss[7:0] WritData[7:0] MISO hiz Figur 2.4. SPI Writ Opration silabs.com Smart. Connctd. Enrgy-frindly. Rv

6 Functional Dscription SPI Daisy Chain Organization Th Si838x provids th capability to asily intrconnct multipl Si838x dvics on a common SPI intrfac administrd by a singl SPI mastr rquiring no additional control signals. To accomplish this, th Si838x includs th additional SPI dvic output pin SDI_THRU. Conncting togthr multipl Si838x dvics in this mannr utilizs th SDI_THRU pin of on Si838x dvic to fd th MOSI pin of th nxt Si838x dvic in th daisy-chain. All bits composing a SPI communication packt ar passd dirctly through by th Si838x from th MOSI input to th SDI_THRU output unchangd, xcpt for th CID[3:0] fild of th control byt. Th last significant four bits of th control byt in a SPI communication packt, CID[3:0], ar ddicatd to addrssing on of up to sixtn Si838x dvics thus connctd, with 0000 indicating th dvic whos MOSI pin is fd dirctly by th SPI mastr, 0001 th following Si838x dvic, tc. As this bit fild is passd through th Si838x, it is dcrmntd by on. This four bit fild is placd in th control word by th SPI mastr in rvrs ordr, allowing th carry of th dcrmnt to rippl into th nxt bit in th CID fild as th bits of th control word procd: CID[0] is placd at bit 3 and CID[3] placd at bit 0 of th control word. Whn a givn Si838x dvic in th daisy chain is prsntd with th CID[3:0] cod of 0000, it is activatd as th on to b addrssd. All rmaining oprations btwn th SPI mastr and th Si838x activatd in this mannr procd as prviously discussd for th cas of th singl Si838x slav. Th organization of an Si838x systm daisy-chaind in this mannr is dpictd in th figur blow. Si838x[0] Si838x[1] Si838x[2] Si838x[3] Si838x[4] Si838x[15] mosi sclk nss miso mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru mosi sclk nss miso sdi_thru SPI_mastr Figur 2.5. SPI Daisy Chain Organization From th prcding figur, and rfrring to Figur 2.2 SPI Communication Packt Structur, Writ Opration and Control Byt Structur on pag 3, in ordr to rad from Si838x[1], th control word would b: Control[7:0] = 0100_1000. Similarly, in ordr to writ to Si838x[12], th control word would b: Control[7:0] = 0000_0011. Finally, if it wr dsird to updat an intrnal SPI rgistr of all daisy-chaind Si838x dvics, th control word would b: Control[7:0] = 1000_0000. If th broadcast bit is zro during a writ opration, only th Si838x dvic bing addrssd using th CID[3:0] fild of th control word in a daisy-chain organization will b updatd. If th broadcast bit is on during a writ opration, th CID[3:0] fild is ignord, and all Si838x dvics connctd in a daisy-chain will b updatd. For non-daisy-chain opration, th CID[3:0] fild should always b all zros. Not that thr is a finit combinational dlay associatd with passing th MOSI input pin of a givn Si838x to th SDI_THRU output pin. As a rsult, th maximum possibl SCLK frquncy will b rducd basd on th numbr of Si838x dvics connctd in a daisy-chain organization. silabs.com Smart. Connctd. Enrgy-frindly. Rv

7 Functional Dscription SPI Intrfac Timing Spcification Th timing diagram for th Si838x SPI intrfac is prsntd in th figur blow. Tp sclk Tsu1 Tsu2 Th2 Th1 Tnss nss mosi Rxbit<7> Rxbit<6> Rxbit<5> Rxbit<0> sdi_thru Rxbit<7> Rxbit<6> Rxbit<5> Rxbit<0> miso Txbit<7> Txbit<6> Txbit<5> Txbit<0> Tdo1 Tdo2 Tdz Figur 2.6. SPI Timing Diagram Th timing spcifications dpictd in this figur apply to ach byt of th thr byt Si838x SPI communications packt. Rfr to th SPI timing spcifications in Tabl 4.2 Elctrical Charactristics on pag 12. Although this discussion of th Si838x SPI intrfac has focusd on a prfrrd organization (sparat MISO/MOSI wirs), othr options ar availabl with rgard to th Si838x control intrfac. Possibl Si838x organizations includ: MISO/MOSI wird opration MISO/MOSI may b two sparat wirs, or may b connctd togthr if th SPI mastr is capabl of tri-stating its MOSI during th data byt packt transfr of a rad opration. Multipl Si838x dvics intrfacd in a non-daisy-chain format Th SPI mastr provids multipl NSS signals, on for ach of a multipl of Si838x slavs. Evry Si838x shars a singl trac from its MOSI input back to th SPI mastr (th Si838x SDI_THRU signal is not utilizd). 2.3 Dbounc Filtr Th Si838x includs a usr programmabl dbounc filtr, providing th usr a mchanism to individually control th dbounc bhavior for ach of th ight Si838x isolation channls. Usr control of th dbounc filtr is accomplishd via th includd Si838x SPI intrfac. Consquntly, usr control of this fatur is availabl only on th srial intrfac accssibl Si838x dvic vrsions. Th dbounc filtr is incorporatd into th path of th input data stram allowing signal conditioning of th PLC inputs. Thr ar product options availabl with th paralll output intrfac with discrt dbounc tim constants of 0, 10, 30 or 100 ms ths ar only availabl on th low spd channls. Th high spd channls hav no dbounc filtring (S 1. Ordring Guid for mor dtails on part numbrs). silabs.com Smart. Connctd. Enrgy-frindly. Rv

8 Functional Dscription Dbounc Control Rgistrs Th opration of th Si838x dbounc filtrs is controlld using r/w control rgistrs mappd into th Si838x SPI addrss spac. Th dtails of ths rgistrs ar covrd in th Si838x SPI rgistr map sction of this documnt. Th options availabl using ths rgistrs ar outlind in th following tabls. For ach of th ight PLC channls, two data bits ar allocatd to control th dbounc dlay, and two bits ar usd to stipulat th dbounc filtring mod. This consums a total of 32 bits, which ar allocatd across four individual Si838x SPI control rgistrs of on byt ach. Tabl 2.2. Dbounc Filtr Dlay Control dbnc_dly[1:0] Dlay (ms) Commnt 00 0 Bypass dbounc Tabl 2.3. Dbounc Filtr Mod Control dbnc_mod[1:0] Filtr Mod Commnt 00 no filtr Simpl trailing dg dlay 01 low pass 1X lading dg silabs.com Smart. Connctd. Enrgy-frindly. Rv

9 Functional Dscription Dbounc Filtring Mods In addition to th usr spcifiabl dlays, thr filtring mods ar providd by th dbounc function. Lik th dbounc dlay stting, ths filtring mods may b uniqu for ach of th ight Si838x PLC channls. Th first of ths thr mods, corrsponding to dbnc_mod[1:0] == 00, mploys only a simpl trailing dg dlay. In this mod, onc th dbounc filtr input has bn stabl for th amount of tim spcifid in th corrsponding channl s dbounc dlay stting, D, th output of th dbounc filtr assums th valu of th nw dbounc input. Consquntly, any glitchs on th dbounc input having a duration lss than th channl s dbounc dlay stting, D, will b supprssd. Th scond mod, corrsponding to dbnc_mod[1:0] == 01, prforms a low pass filtring function on th input to th dbounc filtr. Whn th input to th dbounc filtr has assumd a nw valu, a countr bgins counting toward th currnt dlay stting, D. If bfor th count D is rachd th dbounc input rturns to its prvious stat, this countr is dcrmntd. Assuming that th dbounc filtr input again assums th nw valu bfor th countr is dcrmntd back to 0 (i.. glitch width is lss than tim th input had prviously assumd a nw valu), th countr incrmnting rsums from a non-zro valu. Onc this count has rachd th dsignatd dlay, D, th dbounc filtr output assums th valu of th nw dbounc input. Using this mchanism, any input glitchs on th dbounc input having a duration lss than th channl s dbounc dlay stting, D, will b supprssd. Howvr unlik mod 0, whn th dbounc input rturns to th nw valu aftr this glitch, crdit is givn for th tim this nw valu was activ bfor th glitch. Th final mod, corrsponding to dbnc_mod[1:0] == 1X, ralizs a lading dg filtring function on th input to th dbounc filtr. Intrnally, a countr is initializd to zro. Whn th input to th dbounc filtr changs, th output of th dbounc filtr immdiatly assums th nw valu, and th countr is rst to th currnt dlay stting, D. Indpndnt of what occurs on th input of th dbounc filtr, th countr bgins dcrmnting aftr this chang. Whn th countr again rachs zro, th currnt input of th dbounc filtr is compard to th currnt output of th filtr. If thy ar thy ar diffrnt, again th dbounc filtr immdiatly assums th nw valu. If thy ar th sam, th output of th dbounc filtr will immdiatly chang on th nxt nw valu of th dbounc input. In ithr cas, a chang on th dbounc output filtr rsts th countr to th currnt dlay stting, D. A graphical dpiction of th opration and charactristics for ach ths dbounc filtr mods is providd in th following figur. din A B A D t1 t2 dout I mod = 00 (old) A D dout I mod = 01 (old) A t 1 + t2 dout I mod = 1x A B A D D Figur 2.7. Dbounc Filtr Mods Timing Diagram silabs.com Smart. Connctd. Enrgy-frindly. Rv

10 Functional Dscription 2.4 Typical Oprating Charactristics Si838x I F Vs. V F -40C 0C 25C 125C Ovr Tmpratur 8.00 I F (ma) V F (V) Figur 2.8. Input Currnt vs. Input Voltag Ovr Tmpratur silabs.com Smart. Connctd. Enrgy-frindly. Rv

11 Dvic Opration 3. Dvic Opration Tabl 3.1. Truth Tabl Summary VDD Input, Ax/AHx Output, Bx/BHx P 1 ON High P OFF Low UP 2 X Low 1. P = powrd (> UVLO). 2. UP = Unpowrd (< UVLO). 3.1 Dvic Start-up During start-up, Output Bx/BHx ar hld low until th VDD is abov th UVLO thrshold for a tim priod of at last tstart. Following this, th output is high whn th currnt flowing from anod to cathod is > IF(ON). Dvic startup, normal opration, and shutdown bhavior is shown in th figur blow. UVLO + UVLO - VDD HYS V DD I F(ON) I HYS I F t PLH t PHL t START t PHL t START Output: Bx, BHx Figur 3.1. Dvic Start-up 3.2 Undrvoltag Lockout Undrvoltag Lockout (UVLO) is providd to prvnt rronous opration during dvic startup and shutdown or whn VDD is blow its spcifid oprating circuits rang. For xampl, th output sid unconditionally ntrs UVLO whn V DD falls blow V DDUV and xits UVLO whn V DD riss abov V DDUV Layout Rcommndations To nsur safty in th nd usr application, high voltag circuits (i.., circuits with >30 VAC) must b physically sparatd from th safty xtra-low voltag circuits (SELV is a circuit with <30 VAC) by a crtain distanc (crpag/claranc). If a componnt, such as a digital isolator, straddls this isolation barrir, it must mt thos crpag/claranc rquirmnts and also provid a sufficintly larg high-voltag brakdown protction rating (commonly rfrrd to as working voltag protction). Tabl 4.4 Insulation and Safty-Rlatd Spcifications 1 on pag 15 and Tabl 4.6 VDE Insulation Charactristics 1 on pag 16 dtail th crpag/claranc and working voltag capabilitis of th Si838x. Ths tabls also dtail th componnt standards (UL1577, VDE 0884, CSA 5A), which ar radily accptd by crtification bodis to provid proof for nd-systm spcifications rquirmnts. Rfr to th nd-systm spcification ( , tc.) rquirmnts bfor starting any dsign that uss a digital isolator. silabs.com Smart. Connctd. Enrgy-frindly. Rv

12 Dvic Opration Supply Bypass Th Si838x family rquirs a 0.1 µf bypass capacitor btwn VDD and GND. Th capacitor should b placd as clos as possibl to th packag. To nhanc th robustnss of a dsign, th usr may also includ rsistors ( Ω) in sris with th outputs if th systm is xcssivly noisy Output Pin Trmination Th nominal output impdanc of an isolator drivr channl is approximatly 50 Ω, ±40%, which is a combination of th valu of th onchip sris trmination rsistor and channl rsistanc of th output drivr FET. Whn driving loads whr transmission lin ffcts will b a factor, output pins should b appropriatly trminatd with controlld impdanc PCB tracs. silabs.com Smart. Connctd. Enrgy-frindly. Rv

13 Elctrical Spcifications 4. Elctrical Spcifications Tabl 4.1. Rcommndd Oprating Conditions Paramtr Symbol Min Typ Max Unit V DD Supply Voltag V DD V Input data rat, low-spd channls (no dbounc) D 250 Kbps Input data rat, (10 ms dbounc) D 0.1 Kbps Input data rat, (30 ms dbounc) D Kbps Input data rat, (100 ms dbounc) D 0.01 Kbps Input data rat, high-spd channls DH 2000 Kbps Input Currnt I F(ON) ma Oprating Tmpratur (Ambint) T A C Tabl 4.2. Elctrical Charactristics V DD = 2.25 V 5.5 V; GND = 0 V; T A = 40 to +125 C; typical spcs at 25 C; V DD = 5 V DC Paramtr Symbol Tst Condition Min Typ Max Unit Input Currnt Thrshold I F(TH) µa Input Currnt Hystrsis 1 I HYS µa Input Voltag Thrshold V F(TH) V Input Voltag Hystrsis 2 V HYS mv Input Capacitanc C I f = 100 khz 105 pf VDD Undrvoltag Thrshold V DDUV+ VDD rising V VDD Undrvoltag Thrshold V DDUV VDD falling V VDD Undrvoltag Hystrisis VDD HYS 60 mv Low lvl output voltag V OL IOL = 4 ma 0.4 V High lvl output voltag V OH IOH = 4 ma VDD 0.4 V Output Impdanc Z O 50 Ω Output Currnt I SINK Vout = 0.1 V, 50 Ω load 2.0 ma I SOURCE Vout = VDD 0.1 V, 2.0 ma 50 Ω load DC Supply Currnt (All Inputs 0 or 1) IDD All inputs ma All inputs ma 125 khz Supply Currnt IDD All inputs switching ma 1 MHz (2 Mbps) Supply Currnt silabs.com Smart. Connctd. Enrgy-frindly. Rv

14 Elctrical Spcifications DC Paramtr Symbol Tst Condition Min Typ Max Unit IDD All inputs switching ma AC Switching Paramtrs (V DD = 5 V, C L = 15 pf) Propagation Dlay, Low to High Propagation Dlay, High to Low t PLH AHx channls ns Ax channls µs t PHL AHx channls ns Ax channls µs Puls Width Distortion PWD tplh tphl Propagation Dlay Skw t PSK(P-P) Part to part variation Channl Channl Skw t PSK Channl to channl AHx channls 6 50 ns Ax channls 80 ns AHx channls ±30 ns Ax channls ±80 ns variation AHx channls ±30 ns Ax channls ±80 ns Ris Tim t R 50 Ω load 3.9 ns Fall Tim t F 50 Ω load 3.7 ns Dvic Startup Tim t START 150 µs Common Mod Transint Immunity CMTI S Figur 4.1 Common Mod Masurmnt Circuit Si838x high spd channls (AHx) on pag kv/µs Common Mod Transint Immunity CMTI S Figur 4.1 Common Mod Masurmnt Circuit Si838x low spd channls (Ax) on pag kv/μs Srial Data Intrfac (S Figur 2.6 SPI Timing Diagram on pag 6.) Clock rat 3 SCLK 10 MHz Cycl tim (SCLK) 4 T p 100 ns Dlay tim, SCLK fall to MISO activ Tdo1 20 ns Dlay tim, SCLK fall to MISO transition Tdo2 20 ns Dlay Tim, NSS ris to MISO hi-z Stup tim, NSS fall to SCLK fall Tdz 20 ns Tsu1 25 ns Hold tim, SCLK ris to NSS ris Th1 S Figur 2.6 SPI Timing Diagram on pag ns Stup tim, MOSI to SCLK ris Hold tim, SCLK ris to MOSI transition Tsu2 25 ns Th2 20 ns silabs.com Smart. Connctd. Enrgy-frindly. Rv

15 Elctrical Spcifications DC Paramtr Symbol Tst Condition Min Typ Max Unit Dlay tim btwn NSS activ Propagation dlay, Tnss 200 ns Tdthru MOSI to SDI_THRU 3 15 ns Nots: 1. Th currnt valu at which dvic turns off is dtrmind by I F(OFF) = I F(TH) I HYS. 2. Th voltag valu at which th dvic turns off is dtrmind by V F(OFF) = V F(TH) V HYS. 3. S Sction SPI Daisy Chain Organization. 4. For daisy chain opration, s spc for "Propagation dlay, MOSI to SDI_THRU" in this tabl. Input Signal Switch High-sid Rsistor Si838xP VDD 2.25 to 5.5 V Supply High Low Input Output Isolatd Rfrnc Voltags 2.2nF Low-sid Rsistor COM GND Oscilloscop Isolatd Ground Vcm Surg Output Input High Voltag Diffrntial Prob Output High Voltag Surg Gnrator Figur 4.1. Common Mod Masurmnt Circuit silabs.com Smart. Connctd. Enrgy-frindly. Rv

16 Elctrical Spcifications Tabl 4.3. Rgulatory Information (pnding) 1 CSA Th Si838x is crtifid undr CSA Componnt Accptanc Notic 5A. For mor dtails, s Fil : Up to 130 VRMS rinforcd insulation working voltag; up to 1000 VRMS basic insulation working voltag. VDE Th Si838x is crtifid according to VDE0884. For mor dtails, s Fil VDE : 560 Vpak for basic insulation working voltag UL Th Si838x is crtifid undr UL1577 componnt rcognition program. For mor dtails, s Fil E Ratd up to 2500 VRMS isolation voltag for singl protction. CQC Th Si838x is crtifid undr GB Ratd up to 130 VRMS rinforcd insulation working voltag; up to 1000 VRMS basic insulation working voltag. Not: 1. Rgulatory Crtifications apply to 2.5 kvrms ratd dvics that ar production tstd to 3.0 kvrms for 1 s. For mor information, s 1. Ordring Guid. Tabl 4.4. Insulation and Safty-Rlatd Spcifications 1 Paramtr Symbol Tst Condition QSOP-20 Unit Nominal Air Gap (Claranc) L(IO1) 3.6 min mm Nominal Extrnal Tracking (Crpag) L(IO2) 3.6 min mm Minimum Intrnal Gap (Intrnal Claranc) mm Tracking Rsistanc (Proof Tracking Indx) PTI IEC V Erosion Dpth ED mm Rsistanc (Input-Output) 1 RIO Ω Capacitanc (Input-Output) 1 CIO f = 1 MHz 1 pf Not: 1. To dtrmin rsistanc and capacitanc, th Si838x is convrtd into a 2-trminal dvic. Pins 1 10 ar shortd togthr to form th first trminal, and pins ar shortd togthr to form th scond trminal. Th paramtrs ar thn masurd btwn ths two trminals. silabs.com Smart. Connctd. Enrgy-frindly. Rv

17 Elctrical Spcifications Tabl 4.5. IEC Ratings Paramtr Tst Condition QSOP-20 Basic Isolation Group Matrial Group I Installation Classification Ratd Mains Voltags < 150 VRMS I IV Ratd Mains Voltags < 300 VRMS Ratd Mains Voltags < 400 VRMS Ratd Mains Voltags < 600 VRMS I-III I-II I-II Tabl 4.6. VDE Insulation Charactristics 1 Paramtr Symbol Tst Condition Charactristic Unit QSOP-20 Maximum Working Insulation Voltag V IORM 560 V pak Input to Output Tst Voltag V PR Mthod b V pak (VIORM x = VPR,100%) Production Tst, tm = 1 sc, (Partial Discharg < 5 pc) Transint Ovrvoltag V IOTM t = 60 s 4000 V pak Pollution Dgr 2 (DIN VDE 0110, Tabl 1) Insulation Rsistanc at TS, V IO = 500 V R S >10 9 Ω Not: 1. This isolator is suitabl for basic lctrical isolation only within th safty limit data. Maintnanc of th safty data is nsurd by protctiv circuits. Th Si838x provids a climat classification of 40/125/21. Tabl 4.7. IEC Safty Limiting Valus 1 Paramtr Symbol Tst Condition Max Unit QSOP-20 Cas Tmpratur T S 150 C Safty Currnt I S θ JA = 105 C/W 370 ma V F = 2.8 V, T J = 150 C, T A = 25 C Powr Dissipation P S 1.2 W Not: 1. Maximum valu allowd in th vnt of a failur; also s th thrmal drating curv in Figur 4.2 (QSOP-20) Thrmal Drating Curv, Dpndnc of Safty Limiting Valus with Cas Tmpratur pr VDE 0884 on pag 17. silabs.com Smart. Connctd. Enrgy-frindly. Rv

18 Elctrical Spcifications Tabl 4.8. Thrmal Charactristics Paramtr Symbol QSOP-20 Unit IC Junction-to-Air Thrmal Rsistanc θ JA 105 C/W Safty Limit Currnt (ma) VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Tmpratur ( o C) Figur 4.2. (QSOP-20) Thrmal Drating Curv, Dpndnc of Safty Limiting Valus with Cas Tmpratur pr VDE 0884 silabs.com Smart. Connctd. Enrgy-frindly. Rv

19 Elctrical Spcifications Tabl 4.9. Absolut Maximum Ratings 1 Paramtr Symbol Min Max Unit Storag Tmpratur T STG C Ambint Tmpratur T A C Junction Tmpratur T J +150 C Avrag Forward Input Currnt I F(AVG) 30 ma Pak Transint Input Currnt (< 1 µs puls width, 300 ps) I FTR 1 A Input voltag, rfrrd to COM Ax, AHx ± 0.5 ±7 V Supply Voltag V DD V Output Voltag V OUT 0.5 V DD +0.5 V Avrag Output Currnt I O(AVG) 10 ma Input Powr Dissipation P I 480 mw Output Powr Dissipation (includs 3 ma pr channl for status LED) P O 484 mw Total Powr Dissipation P T 964 mw Lad Soldr Tmpratur (10 s) 260 C HBM Rating ESD 4 kv Machin Modl ESD 200 V CDM 500 V Maximum Isolation Voltag (1 s) 3000 V RMS Not: 1. Prmannt dvic damag may occur if th absolut maximum ratings ar xcdd. Functional opration should b rstrictd to th conditions spcifid in th oprational sctions of this data sht. silabs.com Smart. Connctd. Enrgy-frindly. Rv

20 Applications 5. Applications 5.1 Systm Lvl Transitions with th Si838x Fild PLC Digital Input Modul PLC VIN IIN Si838xP VDD ucontrollr VDD Snsor Or Switch 24V DC Fild Potntial C1 2.2nF High Spd Channls Only VD R2 High-sid Rsistor R1 Low-sid Rsistor AHx Input ID COM Isolation Barrir BHx Output GND Currnt Limit Rsistor Status Lamp LED R3 D2 Input GND Figur 5.1. Systm Lvl Drawing of a High-spd Channl on th Si838xP with th Supporting Bill of Matrials Th Si838x combind with an appropriat input rsistor ntwork and indication LED will produc a PLC Digital Input Modul which adhrs to th IEC spcification. Rsistors R1 and R2 st th transition voltags and currnts for th systm, as visualizd in th figur blow, whil capacitor C1, is rquird only for high-spd channls and srvs to improv CMTI prformanc. Furthr, rsistor R3 is slctd basd on dsird LED, D2, brightnss during a systm ON condition. Systm I-V Curv VIN Dvic On VTR1 VTR2 Dvic Off Hystrsis Rgion TR2 Hystrsis Rgion TR1 Dvic Off Dvic On I IN ITR2 ITR1 Figur 5.2. Visualization of Systm Lvl Transitions whn Utilizing a Si838x According to th Rcommndd Dsign Procss silabs.com Smart. Connctd. Enrgy-frindly. Rv

21 Applications 5.2 IEC Complianc Options IEC articulats thr typs of digital inputs for PLC snsing. Each typ catgory dictats boundary conditions on th systm lvl input spac, (V IN, I IN ), dfining th rang of valus for which th modul must output a logic LOW, a logic HIGH, or transition btwn th two. Mor dtails on th spcification can b found on th IEC wbsit: Th tabl blow provids pr-input typ bill of matrials rcommndations for plug-n-play dsigns adhring to th spcification or as a starting point for custom dsigns. Ths rcommndations assum a rsistor tolranc of 5%. Tabl 5.1. Si838x Rcommndd Input Bill of Matrials and Systm Lvl Transition Valus 1 Input Rsistor Valus Nominal TR1 Valus Nominal TR2 Valus PLC Digital Input Typ R1 (Ω) R2 (Ω) I IN (ma) V IN (V) I IN (ma) V IN (V) Typ Typ Typ Not: 1. Basd on 24 V DC PLC digital input typs. 5.3 Custom Bill of Matrials A PLC digital input modul basd on th Si838x can hav its transition valus customizd on a pr-channl basis in accordanc with th systm lvl quations and tolrancs. An xtndd discussion of this procss and an xampl dsign ar availabl in "AN970: Dsign Guid for PLC Digital Input Moduls Using th Si838x". silabs.com Smart. Connctd. Enrgy-frindly. Rv

22 Pin and Packag Dfinitions 6. Pin and Packag Dfinitions Th Si838x consists of multipl dis in on packag. Each packag and bond-out srvs a customr nd and may rflct multipl bond options. Th following packags ar dfind: QSOP Ordring Guid dscribs th part numbr and OPN configuration quantitis nvisiond for ths products. Subsqunt sctions dfin th pins for ach packag typ. 6.1 Pin Dscriptions AI/AH B1/BH1 A MISO A2/AH B2/BH2 A MOSI A3/AH3 A4/AH4 COM COM A5/AH Isolation Barrir B3/BH3 B4/BH4 VDD GND B5/BH5 A3 A4 COM COM A Isolation Barrir SPI NSS SCLK VDD GND SDITHRU A6/AH B6/BH6 A NC A7/AH B7/BH7 A NC A8/AH B8/BH8 A NC Si8380P/Si8388P Si8380S AH BH1 AH BH1 AH BH2 AH BH2 A1 A2 COM COM A Isolation Barrir B1 B2 VDD GND B3 AH3 AH4 COM COM A Isolation Barrir BH3 BH4 VDD GND B1 A B4 A B2 A B5 A B3 A B6 A B4 Si8382P Si8384P Figur 6.1. Si838x Pin Assignmnts silabs.com Smart. Connctd. Enrgy-frindly. Rv

23 Pin and Packag Dfinitions Tabl 6.1. Si838x Pin Dscriptions Pin Nam Dscription A1 A8 AH1-AH8 COM B1-B8 BH1-BH8 VDD GND MOSI SCLK NSS Low-spd input channls High-spd input channls Common. Can b connctd to ground or 24 V Low-spd output channls High-spd output channls Controllr sid powr supply Controllr sid ground SPI, input SPI Clock SPI Chip slct SDITHRU SPI Srial data out for cascading multipl Si838x (up to 16) MISO SPI, output silabs.com Smart. Connctd. Enrgy-frindly. Rv

24 Packag Outlin 7. Packag Outlin Th figur blow illustrats th packag dtails for th 20-pin QSOP packag. Th tabl blow lists th valus for th dimnsions shown in th illustration. Figur Pin QSOP Packag Outlin silabs.com Smart. Connctd. Enrgy-frindly. Rv

25 Packag Outlin Tabl 7.1. Packag Dimnsions Dimnsion Min Max A 1.75 A A b c D E E BSC 6.00 BSC 3.91 BSC BSC L L BSC h θ 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd All dimnsions shown ar in millimtrs (mm) unlss othrwis notd. 2. Dimnsioning and Tolrancing pr ANSI Y14.5M This drawing conforms to th JEDEC Solid Stat Outlin M0-137, Variation AD. 4. Rcommndd card rflow profil is pr th JEDEC/IPC J-STD-020 spcification for Small Body Componnts. silabs.com Smart. Connctd. Enrgy-frindly. Rv

26 Land Pattrn 8. Land Pattrn Th figur blow illustrats th PCB land pattrn dtails for th 20-pin QSOP packag. Th tabl blow lists th valus for th dimnsions shown in th illustration. Figur Pin QSOP PCB Land Pattrn Tabl Pin QSOP PCB Land Pattrn Dimnsions Dimnsion Fatur mm C1 Pad Column Spacing 5.40 E Pad Row Pitch X1 Pad Width 0.40 Y1 Pad Lngth This Land Pattrn Dsign is basd on IPC-7351 dsign ruls for Dnsity Lvl B (Mdian Land Protrusion). 2. All fatur sizs shown ar at Maximum Matrial Condition (MMC), and a card fabrication tolranc of 0.05 mm is assumd. silabs.com Smart. Connctd. Enrgy-frindly. Rv

27 Top Marking 9. Top Marking Figur 9.1. Si838x Top Marking (20-Pin QSOP) Tabl 9.1. Top Marking Explanation (20-Pin QSOP) Lin 1 Marking: Lin 2 Marking: Bas Part Numbr Ordring Options S 1. Ordring Guid for mor information. YY = Yar WW = Workwk TTTTTT = Mfg Cod Si838 = 8-ch PLC input isolator X = # of high spd channls Y = S, P S = srial outputs P = paralll outputs U = Dbounc option F = fast dbounc, 10 ms M = slowr dbounc, 30 ms S = slow dbounc, 100 ms Assignd by th Assmbly Hous. Corrsponds to th yar and workwk of th mold dat and manufacturing cod from Assmbly Purchas Ordr form. silabs.com Smart. Connctd. Enrgy-frindly. Rv

28 Documnt Chang List 10. Documnt Chang List 10.1 Rvision 0.5 April 4, 2016 Initial rlas. silabs.com Smart. Connctd. Enrgy-frindly. Rv

29 Tabl of Contnts 1. Ordring Guid Functional Dscription Thory of Opration Srial Priphral Intrfac SPI Rgistr Map SPI Communication Transactions SPI Rad Opration SPI Writ Opration SPI Daisy Chain Organization SPI Intrfac Timing Spcification Dbounc Filtr Dbounc Control Rgistrs Dbounc Filtring Mods Typical Oprating Charactristics Dvic Opration Dvic Start-up Undrvoltag Lockout Layout Rcommndations Supply Bypass Output Pin Trmination Elctrical Spcifications Applications Systm Lvl Transitions with th Si838x IEC Complianc Options Custom Bill of Matrials Pin and Packag Dfinitions Pin Dscriptions Packag Outlin Land Pattrn Top Marking Documnt Chang List Rvision Tabl of Contnts 28

30 Smart. Connctd. Enrgy-Frindly. Products Quality Support and Community community.silabs.com Disclaimr Silicon Laboratoris intnds to provid customrs with th latst, accurat, and in-dpth documntation of all priphrals and moduls availabl for systm and softwar implmntrs using or intnding to us th Silicon Laboratoris products. Charactrization data, availabl moduls and priphrals, mmory sizs and mmory addrsss rfr to ach spcific dvic, and "Typical" paramtrs providd can and do vary in diffrnt applications. Application xampls dscribd hrin ar for illustrativ purposs only. Silicon Laboratoris rsrvs th right to mak changs without furthr notic and limitation to product information, spcifications, and dscriptions hrin, and dos not giv warrantis as to th accuracy or compltnss of th includd information. Silicon Laboratoris shall hav no liability for th consquncs of us of th information supplid hrin. This documnt dos not imply or xprss copyright licnss grantd hrundr to dsign or fabricat any intgratd circuits. Th products ar not dsignd or authorizd to b usd within any Lif Support Systm without th spcific writtn consnt of Silicon Laboratoris. A "Lif Support Systm" is any product or systm intndd to support or sustain lif and/or halth, which, if it fails, can b rasonably xpctd to rsult in significant prsonal injury or dath. Silicon Laboratoris products ar not dsignd or authorizd for military applications. Silicon Laboratoris products shall undr no circumstancs b usd in wapons of mass dstruction including (but not limitd to) nuclar, biological or chmical wapons, or missils capabl of dlivring such wapons. Tradmark Information Silicon Laboratoris Inc., Silicon Laboratoris, Silicon Labs, SiLabs and th Silicon Labs logo, Blugiga, Blugiga Logo, Clockbuildr, CMEMS, DSPLL, EFM, EFM32, EFR, Embr, Enrgy Micro, Enrgy Micro logo and combinations throf, "th world s most nrgy frindly microcontrollrs", Embr, EZLink, EZRadio, EZRadioPRO, Gcko, ISOmodm, Prcision32, ProSLIC, Simplicity Studio, SiPHY, Tlgsis, th Tlgsis Logo, USBXprss and othrs ar tradmarks or rgistrd tradmarks of Silicon Laboratoris Inc. ARM, CORTEX, Cortx-M3 and THUMB ar tradmarks or rgistrd tradmarks of ARM Holdings. Kil is a rgistrd tradmark of ARM Limitd. All othr products or brand nams mntiond hrin ar tradmarks of thir rspctiv holdrs. Silicon Laboratoris Inc. 400 Wst Csar Chavz Austin, TX USA

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