AOZ8904 Ultra-Low Capacitance TVS Diode Array

Transcription

1 Ultra-Low Capacitanc TS Diod Array Gnral Dscription Th AOZ8904 is a transint voltag supprssor array dsignd to protct high spd data lins from lctro Static Discharg (SD) and lightning. This dvic incorporats ight surg ratd, low capacitanc string diods and a Transint oltag Supprssor (TS) in a singl packag. During transint conditions, th string diods dirct th transint to ithr th positiv sid of th powr supply lin or to ground. Thy may b usd to mt th SD immunity rquirmnts of IC , Lvl 4 (±15k air, ±8k contact discharg). Th AOZ8904 coms in a Halogn Fr and RoHS compliant SOT-23 and SC-70 packags. It is ratd ovr a -40 C to +85 C ambint tmpratur rang. Faturs SD protction for high-spd data lins: xcds: IC (SD) ±24k (air), ±24k (contact) IC (Lightning) 4A (8/20µs) Human Body Modl (HBM) ±24k Small packag savs board spac Low insrtion loss Protcts four I/O lins Low clamping voltag Low oprating voltag: 5.0 Applications USB 2.0 Powr and Data Lin Protction ido Graphics Cards Monitors and Flat Panl Displays Digital ido Intrfac (DI) Typical Application USB Host Controllr R T R T BUS AOZ Downstram Ports BUS D+ D- GND R T R T +5 BUS D+ D- GND Figur 1. 2 USB High Spd Ports Rv. 2.1 January Pag 1 of 11

2 Ordring Information Part Numbr Ambint Tmpratur Rang Packag nvironmntal AOZ8904CIL AOZ8904HIL -40 C to +85 C SOT-23-6 SC-70-6 RoHS Compliant Grn Product AOS Grn Products usd rducd lvls of Halogns, and ar also RoHS compliant. Plas visit for additional information. Pin Configuration CH1 1 6 CH4 N 2 5 P CH2 3 4 CH3 SOT-23-6 / SC-70-6 (Top iw) Absolut Maximum Ratings xcding th Absolut Maximum ratings may damag th dvic. Paramtr P N Pak Puls Currnt (I PP ), t P = 8/20µs Pak Powr Dissipation (8 x 20µs@ 25 C) Storag Tmpratur (T S ) SD Rating pr IC , contact (1) SD Rating pr IC , air (2) SD Rating pr Human Body Modl (2) Junction Tmpratur (T J ) Rating 6 4A 50W -65 C to +150 C ±24k ±24k ±24k -40 C to +125 C Nots: 1. IC discharg with C Discharg = 150pF, R Discharg = 330Ω. 2. Human Body Discharg pr MIL-STD-883, Mthod 3015 C Discharg = 100pF, R Discharg = 1.5kΩ. Rv. 2.1 January Pag 2 of 11

3 lctrical Charactristics T A = 25 C unlss othrwis spcifid Symbol Paramtr Conditions Min. Typ. Max. Units RWM Rvrs Working oltag Btwn pin 5 and 2 (4) 5.5 BR Rvrs Brakdown oltag I T = 1mA, btwn pins 5 and 2 (5) 6.6 I R Rvrs Lakag Currnt RWM = 5, btwn pins 5 and 2 1 µa F Diod Forward oltag I f = 15mA CL Channl Clamp oltag Positiv Transints Ngativ Transint I PP = 1A, tp = 100ns, any I/O pin to Ground (3)(6)(8) Channl Clamp oltag Positiv Transints Ngativ Transint Channl Clamp oltag Positiv Transints Ngativ Transint IPP = 5A, tp = 100ns, any I/O pin to Ground (3)(6)(8) IPP = 12A, tp = 100ns, any I/O pin to Ground (3)(6)(8) C j Junction Capacitanc R = 0, f = 1Mhz, any I/O pin to Ground (3)(7) pf ΔC j Channl Input Capacitanc Matching R = 0, f = 1Mhz, btwn I/O pins (3)(7) 0.03 pf Nots: 3. Ths spcifications ar guarantd by dsign. 4. Th working pak rvrs voltag, RWM, should b qual to or gratr than th DC or continuous pak oprating voltag lvl. 5. BR is masurd at th puls tst currnt I T. 6. Masurmnts prformd with no xtrnal capacitor on P (Pin 5 floating). 7. Masurmnts prformd with P biasd to 3.3 olts (Pin 3.3). 8. Masurmnts prformd using a 100 nsc Transmission Lin Puls (TLP) systm. Rv. 2.1 January Pag 3 of 11

4 Typical Prformanc Charactristics Clamping oltag, CL () Clamping oltag vs. Pak Puls Currnt (tpriod = 100ns, tr = 1ns) Pak Puls Currnt, I PP (A) Insrtion Loss (db) I/O Gnd Insrtion Loss (S21) vs. Frquncy (p = 3.3) Frquncy (MHz) 7 Forward oltag vs. Forward Currnt (tpriod = 100nS, tr = 1ns) 20 Analog Crosstalk (I/O I/O) vs. Frquncy Forward oltag () Forward Currnt, I PP (A) Insrtion Loss (db) Frquncy (MHz) Insrtion Loss (db) I/O I/O Insrtion Loss (S21) vs. Frquncy (p = Float) Frquncy (MHz) Rv. 2.1 January Pag 4 of 11

5 Application Information Th AOZ8904 TS is dsign to protct four data lins from fast damaging transint ovr-voltag by clamping it to a rfrnc. Whn th transint on a protctd data lin xcd th rfrnc voltag th string diod is forward bias thus, conducting th harmful SD transint away from th snsitiv circuitry undr protction. PCB Layout Guidlins Printd circuit board layout is th ky to achiving th highst lvl of surg immunity on powr and data lins. Th location of th protction dvics on th PCB is th simplst and most important dsign rul to follow. Th AOZ8904 dvics should b locatd as clos as possibl to th nois sourc. Th placmnt of th AOZ8904 dvics should b usd on all data and powr lins that ntr or xit th PCB at th I/O connctor. In most systms, surg pulss occur on data and powr lins that ntr th PCB through th I/O connctor. Placing th AOZ8904 dvics as clos as possibl to th nois sourc nsurs that a surg voltag will b clampd bfor th puls can b coupld into adjacnt PCB tracs. In addition, th PCB should us th shortst possibl tracs. A short trac lngth quats to low impdanc, which nsurs that th surg nrgy will b dissipatd by th AOZ8904 dvic. Long signal tracs will act as antnnas to rciv nrgy from filds that ar producd by th SD puls. By kping lin lngths as short as possibl, th fficincy of th lin to act as an antnna for SD rlatd filds is rducd. Minimiz intrconncting lin lngths by placing dvics with th most intrconnct as clos togthr as possibl. Th protction circuits should shunt th surg voltag to ithr th rfrnc or chassis ground. Shunting th surg voltag dirctly to th IC s signal ground can caus ground bounc. Th clamping prformanc of TS diods on a singl ground PCB can b improvd by minimizing th impdanc with rlativly short and wid ground tracs. Th PCB layout and IC packag parasitic inductancs can caus significant ovrshoot to th TS s clamping voltag. Th inductanc of th PCB can b rducd by using short trac lngths and multipl layrs with sparat ground and powr plans. On ffctiv mthod to minimiz loop problms is to incorporat a ground plan in th PCB dsign. Th AOZ8904 ultra-low capacitanc TS is dsignd to protct four high spd data transmission lins from transint ovr-voltags by clamping thm to a fixd rfrnc. Th low inductanc and construction minimizs voltag ovrshoot during high currnt surgs. Whn th voltag on th protctd lin xcds th rfrnc voltag th intrnal string diods ar forward biasd, conducting th transint currnt away from th snsitiv circuitry. Good circuit board layout is critical for th supprssion of SD inducd transints. Th following guidlins ar rcommndd: 1. Plac th TS nar th IO trminals or connctors to rstrict transint coupling. 2. Fill unusd portions of th PCB with ground plan. 3. Minimiz th path lngth btwn th TS and th protctd lin. 4. Minimiz all conductiv loops including powr and ground loops. 5. Th SD transint rturn path to ground should b kpt as short as possibl. 6. Nvr run critical signals nar board dgs. 7. Us ground plans whnvr possibl. 8. Avoid running critical signal tracs (clocks, rsts, tc.) nar PCB dgs. 9. Sparat chassis ground tracs from componnts and signal tracs by at last 4mm. 10. Kp th chassis ground trac lngth-to-width ratio <5:1 to minimiz inductanc. 11. Protct all xtrnal connctions with TS diods. Rv. 2.1 January Pag 5 of 11

6 I 1394 PHY TPBIASx TPAx+ 1μ 56Ω 56Ω I 1394 Connctor TPBx+ TPAx- TPBx- GND 56Ω 5.1kΩ 56Ω 270p AOZ8904 I394 Port Connction Rv. 2.1 January Pag 6 of 11

7 Packag Dimnsions, SOT-23-6L D Gaug Plan c Sating Plan 0.25mm L θ1 b A A2.010mm A1 RCOMMNDD LAND PATTRN UNIT: mm Dimnsions in millimtrs Symbols Min. A 0.90 A A b 0.30 c 0.08 D L 0.30 θ1 0 Nom. Max BSC 1.90 BSC Dimnsions in inchs Symbols A A1 A2 b c D L θ1 Min Nom Max BSC BSC Nots: 1. Packag body sizs xclud mold flash and gat burrs. Mold flash at th non-lad sids should b lss than 5 mils ach. 2. Dimnsion L is masurd in gaug plan. 3. Tolranc 0mm (4 mil) unlss othrwis spcifid. 4. Followd from JDC MO-178C & MO-193C. 6. Controlling dimnsion is millimtr. Convrtd inch dimnsions ar not ncssarily xact. Rv. 2.1 January Pag 7 of 11

8 Tap and Rl Dimnsions, SOT-23-5&6L Tap P2 P1 D0 D1 K0 B0 2 P0 A0 Unit: mm Fding Dirction Packag A0 B0 K0 D0 D1 2 P0 P1 P2 T SOT23-5/6L LP / ± ±0.03 Rl W1 S R M N K J H Unit: mm Tap Siz Rl Siz M N W1 H S K R J 8mm ø177.8 ø177.8 Max Min / / Min 10.1 Min ±0.1 Ladr/Trailr and Orintation Trailr Tap 300mm min. Componnts Tap Orintation in Pockt Ladr Tap 500mm min. Rv. 2.1 January Pag 8 of 11

9 Packag Dimnsions, SC-70-6L D Gaug Plan θ 0.15mm L b c A A2.010mm A1 RCOMMNDD LAND PATTRN UNIT: mm Dimnsions in millimtrs Symbols Min. A A A2 0.7 b 0.15 c 0.08 D L 0.26 θ 0 Nom. Max BSC 1.30 BSC Dimnsions in inchs Symbols A A1 A2 b c D L θ Min. Nom. Max BSC BSC Nots: 1. All dimnsions ar in millimtrs. 2. Dimnsions ar inclusiv of plating 3. Packag body sizs xclud mold flash and gat burrs. Mold flash at th non-lad sids should b lss than 3 mils. 4. Di is facing up for mold and facing down for trim/form; i.., rvrs trim/form. 5. Dimnsion L is masurd in gaug plan. 6. Controlling dimnsion is millimtr, convrtd inch dimnsions ar not ncssarily xact. Rv. 2.1 January Pag 9 of 11

10 Tap and Rl Dimnsions, SC-70-6L Carrir Tap T D1 P1 P2 2 B0 K0 UNIT: mm A0 D0 P0 Fding Dirction Packag SC-70, 6L (8mm) A B K D Min. D ± P P P T 0.25 Rl W1 G S M N K R H W Tap Siz 8mm Rl Siz ø180 M ø ±0.50 N ø60.50 W 9.00 ±0.30 W ±1.00 H ø /-0.20 K S 2.00 ±0.50 G ø9.00 R Ladr/Trailr and Orintation Trailr Tap 300mm min. or 75 mpty pockts Componnts Tap Orintation in Pockt Ladr Tap 500mm min. or 125 mpty pockts Rv. 2.1 January Pag 10 of 11

11 Part Marking AOZ8904CIL (SOT-23) AKOW LT Assmbly Lot Cod Part Numbr Cod Undrscor Dnots Grn Product Wk & Yar Cod Otption & Assmbly Location Cod AOZ8904HIL (SC-70) AWL Part Numbr Cod Undrscor Dnots Grn Product Assmbly Lot & Location Cod Wk & Yar Cod This datasht contains prliminary data; supplmntary data may b publishd at a latr dat. Alpha & Omga Smiconductor rsrvs th right to mak changs at any tim without notic. LIF SUPPORT POLICY ALPHA & OMGA SMICONDUCTOR PRODUCTS AR NOT AUTHORIZD FOR US AS CRITICAL COMPONNTS IN LIF SUPPORT DICS OR SYSTMS. As usd hrin: 1. Lif support dvics or systms ar dvics or systms which, (a) ar intndd for surgical implant into th body or (b) support or sustain lif, and (c) whos failur to prform whn proprly usd in accordanc with instructions for us providd in th labling, can b rasonably xpctd to rsult in a significant injury of th usr. 2. A critical componnt in any componnt of a lif support, dvic, or systm whos failur to prform can b rasonably xpctd to caus th failur of th lif support dvic or systm, or to affct its safty or ffctivnss. Rv. 2.1 January Pag 11 of 11