GUx. Data Sheet. HSMP-389x Series, HSMP-489x Series Surface Mount RF PIN Switch Diodes. Features. Description/Applications

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1 HSMP-89x Series, HSMP-89x Series Surface Mount R PIN Switch Diodes Data Sheet Description/Applications The HSMP-89x series is optimized for switching applications where low resistance at low current and low capacitance are required. The HSMP-89x series products feature ultra low parasitic inductance. These products are specifically designed for use at frequencies which are much higher than the upper limit for conventional PIN diodes. Pin Connections and Package Marking GUx 6 5 eatures Unique Configurations in Surface Mount Packages Add lexibility Save Board Space Reduce Cost Switching Low Capacitance Low Resistance at Low Current Low ailure in Time (IT) Rate [] Matched Diodes for Consistent Performance Better Thermal Conductivity for Higher Power Dissipation Lead-free Option Available Note:. or more information see the Surface Mount PIN Reliability Data Sheet. Notes:. Package marking provides orientation, identification, and date code.. See lectrical Specifications for appropriate package marking.

2 Package Lead Code Identification, SOT-/ (Top View) Package Lead Code Identification, SOT- (Top View) Package Lead Code Identification, SOT-6 (Top View) SINGL SRIS SINGL SRIS UNCONNCTD TRIO 6 5 DUAL SWITCH MODL 6 5 #0 COMMON ANOD # COMMON CATHOD B COMMON ANOD C COMMON CATHOD L LOW INDUCTANC SINGL 6 5 R SRIS SHUNT PAIR 6 5 # UNCONNCTD PAIR #5 # DUAL ANOD 890 DUAL ANOD 89B T HIGH RQUNCY SRIS 6 5 U RING QUAD V #7 UNDR DVLOPMNT Absolute Maximum Ratings [] T C = +5 C Symbol Parameter Unit SOT-/ SOT-/6 I f orward Current ( µs Pulse) Amp P IV Peak Inverse Voltage V T j Junction Temperature C T stg Storage Temperature C -65 to to 50 θ jc Thermal Resistance [] C/W Notes:. Operation in excess of any one of these conditions may result in permanent damage to the device.. T C = +5 C, where T C is defined to be the temperature at the package pins where contact is made to the circuit board. SD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge.

3 lectrical Specifications, T C = 5 C, each diode Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Configuration Voltage V BR (V) R S (ý) C T (p) 890 G0 [] 0 Single G [] Series 89 G [] Common Anode 89 G [] Common Cathode 895 G5 [] 5 Unconnected Pair 89B G0 [] B Single 89C G [] C Series 89 G [] Common Anode 89 G [] Common Cathode 89L GL [] L Unconnected Trio 89R S [] R Dual Switch Mode 89T Z [] T Low Inductance Single 89U GU [] U Series-Shunt Pair 89V GV [] V High requency Series Pair Test Conditions V R = V BR I = 5 ma V R = 5 V Measure f = 00 MHz f = MHz I R 0 µa Notes:. Package marking code is white.. Package is laser marked. High requency (Low Inductance, 500 MHz GHz) PIN Diodes Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Voltage Resistance Capacitance Capacitance Inductance HSMP- Code [] Configuration V BR (V) R S (ý) C T (p) C T (p) L T (nh) 89x GA Dual Anode Test Conditions V R = V BR I = 5 ma f = MHz V R = 5 V f=500 MHz Measure V R = 5 V f = MHz GHz I R 0 µa Note:. SOT- package marking code is white; SOT- is laser marked. Typical Parameters at T C = 5 C Part Number Series Resistance Carrier Lifetime Total Capacitance HSMP- R S (ý) τ (ns) C T (p) 89x V Test Conditions I = ma I = 0 ma f = 00 MHz I R = 6 ma

4 HSMP-89x Series Typical Performance, T C = 5 C, each diode R RSISTANC (OHMS) I ORWARD BIAS CURRNT (ma) igure. Total R Resistance at 5 C vs. orward Bias Current. TOTAL CAPACITANC (p) GHz MHz V R RVRS VOLTAG (V) igure. Capacitance vs. Reverse Voltage. INPUT INTRCPT POINT (dbm) Diode Mounted as a Series Attenuator in a 50 Ohm Microstrip and Tested at MHz I ORWARD BIAS CURRNT (ma) igure. nd Harmonic Input Intercept Point vs. orward Bias Current T rr RVRS RCOVRY TIM (ns) V R = V V R = 5V V R = 0V I ORWARD CURRNT (ma) C 5 C 50 C ORWARD CURRNT (ma) igure. Typical Reverse Recovery Time vs. Reverse Voltage. V ORWARD VOLTAG (V) igure 5. orward Current vs. orward Voltage. Typical Applications for Multiple Diode Products ON O 0 0 +V V b b b 5 6 R in R out igure 7. HSMP-89L Unconnected Trio used in a Dual Voltage, High Isolation Switch. igure 6. HSMP-89L used in a SPT Switch.

5 Typical Applications for Multiple Diode Products (continued) ON O +V 0 0 +V R out R in R out R in igure 8. HSMP-89L Unconnected Trio used in a Positive Voltage, High Isolation Switch. igure 9. HSMP-89T used in a Low Inductance Shunt Mounted Switch. Bias Xmtr C Ant λ C Rcvr Bias Xmtr Ant λ Rcvr Bias bias Xmtr Antenna PA HSMP-89V LNA HSMP-89U λ Rcvr λ igure 0. HSMP-89U Series/Shunt Pair used in a 900 MHz Transmit/Receive Switch. igure. HSMP-89V Series/Shunt Pair used in a.8 GHz Transmit/Receive Switch. 5

6 Typical Applications for Multiple Diode Products (continued) R COMMON R COMMON R R R R BIAS BIAS BIAS BIAS igure. Simple SPDT Switch, Using Only Positive Current. igure. High Isolation SPDT Switch, Dual Bias. R COMMON R COMMON BIAS R R R BIAS R igure. Switch Using Both Positive and Negative Bias Current. igure 5. Very High Isolation SPDT Switch, Dual Bias. 6

7 Typical Applications for HSMP-89x Low Inductance Series Microstrip Series Connection for HSMP-89x Series In order to take full advantage of the low inductance of the HSMP 89x series when using them in series applications, both lead and lead should be connected together, as shown in igure 7. quivalent Circuit Model HSMP-89x Chip* R s R j 0.5 Ω C j HSMP-89x igure 6. Internal Connections. 0. p* * Measured at -0 V R T = R j C T = C P + C j R j = 0 Ω I 0.9 I = orward Bias Current in ma * See AN for package models igure 7. Circuit Layout. Microstrip Shunt Connections for HSMP-89x Series In igure 8, the center conductor of the microstrip line is interrupted and leads and of the HSMP-89x diode are placed across the resulting gap. This forces the.5 nh lead inductance of leads and to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0. nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.0" thick material. Co-Planar Waveguide Shunt Connection for HSMP-89x Series Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in igure 0. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. Co-Planar Waveguide Groundplane Center Conductor Groundplane 50 OHM MICROSTRIP LINS igure 0. Circuit Layout. 0. p PAD CONNCTD TO GROUND BY TWO VIA HOLS 0.75 nh igure 8. Circuit Layout..5 nh.5 nh igure. quivalent Circuit. 0. p A SPIC model is not available for PIN diodes as SPIC does not provide for a key PIN diode characteristic, carrier lifetime. 0. nh 0. nh igure 9. quivalent Circuit. 7

8 Assembly Information igure. PCB Pad Layout, SOT-6. (dimensions in inches) igure. PCB Pad Layout, SOT-. (dimensions in inches) DIMNSIONS IN inches mm igure. PCB Pad Layout, SOT DIMNSIONS IN inches mm igure 5. PCB Pad Layout, SOT-. 8

9 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT package, will reach solder reflow temperatures faster than those with a greater mass. Avago Technologies diodes have been qualified to the time-temperature profile shown in igure 6. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (T MAX ) should not exceed 60 C. These parameters are typical for a surface mount assembly process for Avago Technologies diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. Tp Ramp-up tp Critical Zone T L to Tp Temperature T L Ts max Ts min ts Preheat t L Ramp-down 5 t 5 C to Peak Time igure 6. Surface Mount Assembly Profile. Lead-ree Reflow Profile Recommendation (IPC/JDC J-STD-00C) Reflow Parameter Lead-ree Assembly Average ramp-up rate (Liquidus Temperature (T S(max) to Peak) C/ second max Preheat Temperature Min (T S(min) ) 50 C Temperature Max (T S(max) ) 00 C Time (min to max) (t S ) seconds Ts(max) to TL Ramp-up Rate C/second max Time maintained above: Temperature (T L ) 7 C Time (t L ) seconds Peak Temperature (T P ) 60 +0/-5 C Time within 5 C of actual Peak temperature (t P ) 0-0 seconds Ramp-down Rate 6 C/second max Time 5 C to Peak Temperature 8 minutes max Note : All temperatures refer to topside of the package, measured on the package body surface 9

10 Package Dimensions Outline (SOT-) Outline SOT- (SC-70 Lead).0 (0.00) 0.89 (0.05) 0.5 (0.0) 0.7 (0.05) DAT COD (X) PACKAG MARKING COD (XX).0 (0.05) R. DAT COD (X) PACKAG MARKING COD (XX) X X X.0 (0.055).0 (0.07).65 (0.0).0 (0.08).0 (0.087).00 (0.079) X X X.5 (0.05).5 (0.05) 0.60 (0.0) 0.5 (0.08).0 (0.080).78 (0.070) TOP VIW.06 (0.0).80 (0.0) 0.5 (0.006) (0.00) 0.0 (0.00) 0.00 (0.00).0 (0.087).80 (0.07) BSC (0.05) 0.0 R. 0.5 (0.07) TYP. 0.0 (0.00) 0.0 (0.0005) SID VIW.0 (0.0) 0.85 (0.0) 0.69 (0.07) 0.5 (0.08) ND VIW 0.5 (0.00) 0.5 (0.006).00 (0.09) 0.80 (0.0) DIMNSIONS AR IN MILLIMTRS (INCHS) (0.0) 0.0 (0.00) 0.0 (0.008) 0.0 (0.00) DIMNSIONS AR IN MILLIMTRS (INCHS) Outline (SOT-) Outline SOT-6 (SC-70 6 Lead) 0.9 (0.06) 0.78 (0.0) DAT COD (X) PACKAG MARKING COD (XX).0 (0.05) R. DAT COD (X) PACKAG MARKING COD (XX) X X X.0 (0.055).0 (0.07).65 (0.0).0 (0.08).0 (0.087).00 (0.079) X X X.5 (0.05).5 (0.05) 0.60 (0.0) 0.5 (0.08).0 (0.080).78 (0.070) 0.5 (0.0) 0.7 (0.05).0 (0.087).80 (0.07) BSC (0.05) 0.5 (0.07) TYP..06 (0.0).80 (0.0) 0.5 (0.006) 0.09 (0.00) 0.0 (0.00) 0.00 (0.00) 0.0 R..0 (0.0) 0.85 (0.0) 0.0 (0.00) 0.0 (0.0005) DIMNSIONS AR IN MILLIMTRS (INCHS) 0.69 (0.07) 0.5 (0.08) 0.5 (0.00) 0.5 (0.006).00 (0.09) 0.80 (0.0) (0.0) 0.0 (0.00) 0.0 (0.008) 0.0 (0.00) DIMNSIONS AR IN MILLIMTRS (INCHS) Package Characteristics Lead Material Copper (SOT-/6); Alloy (SOT-/) Lead inish Tin 00% Maximum Soldering Temperature 60 C for 5 seconds Minimum Lead Strength pounds pull Typical Package Inductance nh Typical Package Capacitance 0.08 p (opposite leads) 0

11 Ordering Information Specify part number followed by option. or example: HSMP - 89x - xxx Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 00 pcs. per antistatic bag -TRG = Tape and Reel, 000 devices per 7" reel -TRG = Tape and Reel, 0,000 devices per " reel Tape and Reeling conforms to lectronic Industries RS-8, Taping of Surface Mounted Components for Automated Placement. Device Orientation or Outlines SOT-, - RL TOP VIW mm ND VIW CARRIR TAP 8 mm ABC ABC ABC ABC USR D DIRCTION or Outline SOT- COVR TAP or Outline SOT-6 Note: "AB" represents package marking code. "C" represents date code. TOP VIW mm ND VIW TOP VIW mm ND VIW 8 mm ABC ABC ABC ABC 8 mm ABC ABC ABC ABC Note: "AB" represents package marking code. "C" represents date code. Note: "AB" represents package marking code. "C" represents date code.

12 Tape Dimensions and Product Orientation or Outline SOT- P D P P 0 W t D 9 MAX Ko 8 MAX.5 MAX A 0 B 0 CAVITY PRORATION CARRIR TAP DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH DPTH PITCH BOTTOM HOL DIAMTR DIAMTR PITCH POSITION THICKNSS A 0 B 0 K 0 P D D P 0 W t.5 ± ± 0.0. ± ± ± ± ± ± ± ± ± ± ± ± DISTANC BTWN CNTRLIN CAVITY TO PRORATION ( DIRCTION) CAVITY TO PRORATION (LNGTH DIRCTION) P.50 ± ± ± ± 0.00 or Outline SOT- P P0 D P W D t 9 MAX K 0 9 MAX A 0 B 0 CAVITY PRORATION DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH DPTH PITCH BOTTOM HOL DIAMTR DIAMTR PITCH POSITION A 0 B 0 K 0 P D D P 0.9 ± ± 0.0. ± ± ± ± ± ± ± ± ± ± 0.00 CARRIR TAP THICKNSS W t ± DISTANC CAVITY TO PRORATION ( DIRCTION) CAVITY TO PRORATION (LNGTH DIRCTION) P.50 ± ± ± ± 0.00

13 Tape Dimensions and Product Orientation or Outlines SOT-, -6 P D P P 0 C W t (CARRIR TAP THICKNSS) D T t (COVR TAP THICKNSS) An K 0 An A 0 B 0 CAVITY PRORATION CARRIR TAP COVR TAP DISTANC ANGL DSCRIPTION SYMBOL SIZ (mm) SIZ (INCHS) LNGTH DPTH PITCH BOTTOM HOL DIAMTR DIAMTR PITCH POSITION THICKNSS TAP THICKNSS CAVITY TO PRORATION ( DIRCTION) CAVITY TO PRORATION (LNGTH DIRCTION) A 0 B 0 K 0 P D D P 0.0 ± ± ± ± ± ± ± 0.0 W t 8.00 ± ± 0.0 P.50 ± ± 0.05 OR SOT- (SC70- LAD) An 8 C MAX OR SOT-6 (SC70-6 LAD) C 5. ± 0.0 T t 0.06 ± C MAX 0.09 ± ± ± ± ± ± ± ± ± ± ± ± ± 0.00 or product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. Obsoletes N AV0-08N - July 7, 008