FPGA Implementation vector control of tandem converter fed induction machine

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1 See dscussons, stts, nd uthor profles for ths pulcton t: FPGA Implementton vector control of tndem converter fed nducton mchne ARTICLE CITATIONS 3 READS 25 4 AUTHORS: József Vásárhely Unversty of Mskolc 38 PUBLICATIONS 75 CITATIONS Már Imecs Unverstte Tehnc Cluj-Npoc 65 PUBLICATIONS 178 CITATIONS SEE PROFILE SEE PROFILE Cs Szo Unverstte Tehnc Cluj-Npoc 45 PUBLICATIONS 131 CITATIONS Ion Incze Unverstte Tehnc Cluj-Npoc 31 PUBLICATIONS 84 CITATIONS SEE PROFILE SEE PROFILE All n-text references underlned n lue re lnked to pulctons on ReserchGte, lettng you ccess nd red them mmedtely. Avlle from: Már Imecs Retreved on: 09 Aprl 2016

2 FPGA Implementton Vector Control of Tndem Converter Fed Inducton Mchne József Vásárhely 1, Már Imecs 2, Cs Szó 2, Ion Iov Incze 2 1 Egyetemváros, Unversty of Mskolc, H-3515 Mskolc, Hungry vjo@mzsol.t.un-mskolc.hu 2 Techncl Unversty of Cluj-Npoc, P. O Box 99, Cluj-Npoc, Romn {cs.szo, on.ncze, mecs}@edr.utcluj.ro Astrct: The pper focuses on the mplementton n Feld Progrmmle Gte Arrys (FPGA) of vector control systems of the nducton motor suppled from the tndem (hyrd) sttc-frequency converter. The pper tres to gve synthess of the tndem vector control structure mplementton. The mplementton ws mde usng the lrry elements for rpd prototypng of vector control systems for nducton motor. The mplementton nlyss s presented. Keywords: FPGA, emedded system, vector control, tndem nverted, moton control. 1 Introducton There re two types of dgtl sgnl processng lgorthms: flterng lgorthms nd sgnl nlyss lgorthms. These lgorthms re sed on ether dfferentl equtons (recursve nd non-recursve), or dscrete Fourer trnsformton (DFT), nd cn e mplemented n ny of the followng forms: hrdwre, frmwre, nd softwre. In the softwre pproch, the lgorthm s mplemented s computer progrm on generl-purpose computer such s workstton, mncomputer, personl computer, progrmmle DSP chp, or mcrocontroller or other hrdwre support. In the hrdwre pproch, the lgorthm s mplemented usng dgtl crcutry, such s the shft regster to provde the delyng operton, the dgtl multpler, nd the dgtl dder (such s Feld Progrmmle Gte Arrys - FPGA). Alterntvely, specl purpose VLSI chp my e desgned nd frcted to mplement specfc flterng lgorthm (.e. Applcton Specfc Integrted Crcut - ASIC).

3 Fnlly, n the frmwre pproch, the lgorthm s mplemented usng oth hrdwre nd softwre solutons. Addtonl control crcutres, nd storge regsters, re usully needed n the fnl hrdwre or frmwre relzton. Ths pper presents the mplementton spects nd some results of dgtl sgnl processng (DSP) lgorthms for vector control for the tndem nverter. 1.1 Vector Control of the Tndem Inverter An lterntve soluton for medum- nd hgh-power AC drves s the tndem sttc frequency converter (SFC) fed nducton motor. Ths confgurton s hyrd SFC, whch comnes the dvntges of two, prllel workng, dfferent types nd dfferent power rnges DC-lnk converters. A lrge power Current Source Inverter (CSI), opertng n Pulse Ampltude Modulton (PAM) converts the ctve power, nd smll power Voltge Source Inverter (VSI) workng n Pulse Wdth Modulton (PWM) nd supples the rectve power requred for mprovng the qulty of the motor currents [9], [11]. To otn the est dynmc ehvour the control of the tndem-converter-fed nducton motor cn e cheved usng conventonl vector-control structures. The tndem converter needs dfferent control strteges dependng on the chrcter of the workng component-converter nd on the modulton procedure used for the VSI [11]. The tndem converter needs dfferent control strteges dependng on the type of the PWM procedure used for the VSI. The selected PWM procedure cn chnge the source chrcter of the VSI nd of the tndem converter, too [12]. The openloop voltge-control PWM procedures,.e. crrer wve or Spce-Vector Modulton (SVM), keep the voltge-source chrcter of the VSI, ut usng closed-loop current-control PWM procedures (e.g. the common ng-ng current control) the ehvour of the VSI ecomes of current-source chrcter Current Controlled PWM-VSI-Fed Inducton Motor wth Rotor- Feld Orentton Due to the voltge-source chrcter of the tndem converter, the motor sors freely ts sttor currents. Consequently, the VSI wll e the ctutor ensurng the vector control of the nducton motor drve. It s possle to pply the common PWM procedures (voltge- or current controlled ones) chrcterstc to the VSI. Applyng to the VSI current-controlled-pwm, n mnner of the ng-ng converter, the tndem-converter-fed motor wll e controlled n fct n current. Constnt swtchng frequency s otned usng synchronzed on-off swtchng controllers. The ove-mentoned procedures re pproprte for feld-orenttonsed tndem-fed drves.

4 In Fgure 1 the nducton motor opertes suppled from the oth converters n tndem mode. Becuse of the dffcultes encountered y drect mesurement of the modulted-voltge wves, the sttor voltge s dentfed n lock V s Id usng the mesured DC-lnk voltge nd the stte of nverter swtches ccordng to the PWM logc tkng nto ccount the voltge losses on semconductor devces, too. Ψ r ω r Ψr Flux Controller Speed Controller sd λ r sd λ r Identfed Feld Coordnte Trnsformton cosλr CooT [D(-λr)] VA2 snλr ψrd ψrq sd sq ψrco sd sq ψsd ψsq CSI Current s ψsc sd sq vsd vsq π 2 3 VA1 PhT [A] -1 PhT [A] PhT [A] DC + Phse Trnsformton εs DC-lnk Current Controller α - DC Synchronston [s ] + - PWM logc [s] fs εcsi V sid Thyrstor Rectfer PAM-CSI [vs]* AC lne Ld Dode Rectfer Cd PWM- VSI ωr Mechncl Angulr Speed Rotor-flux Compenston Sttor-flux Computton Fgure 1 Rotor-feld Orented Vector Control System wth Current Feedck Modulton for the Tndem Converter-Fed Inducton Motor [13] Bsed on the sttor-voltge nd current components trnsformed n d-q reference frme, the lock Ψ s C ntegrtes the nturl sttor-voltge equtons yeldng t ts outputs the sttor-flux d-q components. In order to otn the orentton flux, the lock Ψ r Co compenstes the sttor flux. The vector-nlyzer VA 2 computes the mpltude nd the ngulr poston of the orentton feld. The reference vlues of the sttor-current spce-phsor components re otned from the flux- nd speedcontrol loops. After the coordnte trnsformton, they wll e trnsformed to the three-phse references of the hysteress ded nd current-controllers [9] nd [13]. 2 Vector Control Structure Anlyses The creton of lrry for modellng nd rpd prototypng of vector control system for AC drves ws motvted y the fct tht the FPGA undnt resources llow the mplementtons n low prced FPGA chps. Ths posslty gve the de to mplement smulton nd lso n mplementton lrry (usng Mtl Smulnk), whch s completely prmetrcl nd ny chnge on the vector control

5 system s structure cn e ppled very fst nd esy n the mplementton hrdwre. The elements of the lrry re the most common modules of vector control systems, nd ech present stndlone unt n the lrry. The nlyss of the vector control schemes nd especlly the vector control structures from the pont of vew of modulrty were presented n detl n [10]. The equtons of vector control schemes cn e decomposed n elementry mthemtcl opertons [10]. Wht s more, these elementry opertons cn e comned n the most used DSP functon multply nd ccumulte : c = k = 1 ( ) (1) The dfference etween the DSP nd FPGA mplementton of the multply nd ccumulte (MAC) s tht n the cse of ltter one the opertons from equton (1) re executed n prllel nd not sequentlly. In such wy, the executon tme s reduced y the prllel computton. Usng ths feture of the FPGAs, we cn mke decomposton of the vector control system n MAC elementry functons. [10] Tkng nto ccount these crcumstnces, one cn use dfferent types of mplementton topologes: sequentl, prllel nd the comnton of the oth types. The prllel mplementton of the lgorthm results n very fst executon speed. For ths reson, the smplng perod cn e decresed untl the technology nd the PID controllers llow t. The prllel computton of equtons control equtons gve sgnfcnt mprovement compred to the DSP sequentl computton. The prllel mplementton method dsdvntges could e the ntensve hrdwre resource consumng nd the prce pd for chp. 3 IP Core Implementton There re some mjor dvntges of usng pre-desgned prmetrcl model when mplementton s trgeted. These dvntges re: - The mplementton tme of the smulton model s short, s the smulton model s the mplementton tself. Ths cn e done wth the trnslton of the cores n confgurton dt (usng the Xlnx development envronment). - The computton speed ncrese. Ths results from the prllel mplementton of computton lgorthm of oth components (d, q) nd the prllel computton of ech IP core. Ths s sgnfcnt dvntge compred to the DSP sequentl mplementtons.

6 - The prmeters of ech IP core element cn e djusted esly to ny AC motor chrcterstcs. Even the dt formt cn e modfed f necessry. - Flexlty n mplementton: ech IP core cn e trnslted seprtely nd the vector control system cn e trnslted s whole. - The trgeted devce cn e chnged f necessry. - The optmston of the IP elements s mde for speed or/nd re, whch re chrcterstc to FPGA mplementtons. In the followng, we wll present some of the mplemented IP lrry elements n detls, whle the mplementton results wll e presented n Tle 1. All the equtons n the followng sectons re referred s per unt equtons. The mplementton chrcterstcs of the mplemented lrry elements re chrctersed from pont of vew such s tme dely ntroduced y the module n the control loop nd hrdwre resources occuped n the FPGA. The chrcterstc modules of the vector control system wll e presented frst. These modules re the drect nd reverse phse trnsformton, vector nlyser, nd coordnte trnsformton. 3.1 Drect Phse Trnsformton Block PHT[A] The so-clled drect Prk trnsformtons execute the chnge of vrle from the three-phse qunttes g, g, g c to nother three ones g d, g q, g 0. They re the two components of the spce phsor n the complex plne nd the correspondng zerosequence component. The mplementton s sed on equton: g 2 = k ( g + g + g ), (2) ph c 2 k Ph = (3) 3 g g g 0 d q = g g 0; 1 = 3 ( g g ); c g + g + gc = ; (5) 3 To keep generlty of the mplementton equtons (3) nd (5) were relsed. Fgure shows the mplementton. (4)

7 g xlddsu - fpt dl gd g-gc g-g0 xlddsu - x fpt dl gq 1/sqrt(3) g xlddsu + gc g+g xlddsu + g+g+gc 1/3 x fpt dl g0 Fgure 2 System Genertor Implementton of the PHT[A] The nlyses of the PHT[A] lock s mde fter the trnslton of the lock n VHDL lnguge nd fter the mplementton. As result of these steps, we otned the followng mplementton report (see Fgure 3). From the mplementton report presented n Fgure 3 t results the resources used for the mplementton of the PHT[A] module. The totl numer of slces used for the mplementton s 152, whch s only 5% of the chp trgeted. The numer of LUT used s 4 nputs LUT s 277. The mount of LUT used to mplement comntorl functons s 253 nd 24 LUT re used for routng. Desgn Summry Numer of errors: 0 Numer of Slces: 152 out of 3,008 5% Numer of Slces contnng unrelted logc: 0 out of 152 0% Totl Numer 4 nput LUTs: 277 out of 6,016 4% Numer used s LUTs: 253 Numer used s route-thru: 24 Fgure 3 Desgn mplementton summry of IP core PHT[A] The pd to pd dely (Fgure 4), whch s the module nput to output dely, s 27ns. Ths dely s composed from the dely ntroduced y the mplementton logc (15.7ns) nd the dely ntroduced y the routng nets (11.3ns).

8 Relese Trce F.23 Copyrght (c) Xlnx, Inc. All rghts reserved. Desgn fle: pht.ncd Physcl constrnt fle: pht.pcf Devce,speed: xc2vp4,-5 (ADVANCED ) All vlues dsplyed n nnoseconds (ns) Pd to Pd Source Pd Destnton Pd Dely g<0> g0<0> g<0> gd<7> g<11> g0<2> g<12> gd<15> g<14> g0<0> g<10> gq<1> Anlyss completed Thu Jn 30 17:07: Totl ns (15.744ns logc, ns route) (58.2% logc, 41.8% route) Fgure 4 Post Plce nd route sttc tmng report of module PHT[A] 3 x 10-4 Spce phsor dgrm of the quntston error of u sq - u sd 2 quntston error q usd quntston error q usq x 10-4 Fgure 5 Quntston error of the lock PHT[A] for the vrles u sd - u sq From the mplementton results the quntston error ntroduced y ths module: [ , ] nd Δε [ , 3 10 ], Δ ε (6) d q where Δε d/q s the quntston error. We cn sy tht comprng the nput vlue rnge of the voltge/current vlue s cceptle. In the smplfed PHT[A] module mplementton we hve consdered the zero sequence component g 0 =0. Snce ths

9 mplementton omts the zero sequence components, t s much smple, nd for ths reson, the consumed hrdwre resources re lower. The mplementton contns only sutrcton module nd constnt multpler. 3.2 Vector Anlyzer Module Whle ll the other modules were mplemented usng System Genertor lrry elements, the mplementton of the VA module s mplemented usng Xlnx Core Genertor nd VHDL. The opertons were mplemented n VHDL code nd then the code ws mported for smulton/mplementton nto the Smulnk model. The VA module ws mplemented n ccordnce wth equtons: 2 2 gq gd g = g d + g q ; nd sn α = ; cosα =. (7) g g In Fgure 6 there re two multplexers, who llow mplement/smulte VHDL code n Smulnk. The squre operton s mde y the multplers Mult nd Mult1, nd the ddton of the two squres re mde y the lock AddSu. The module fnlly s computed y the squre root (sqrt) operton nd mplemented n VHDL code pss_nt1 1 gd 2 gq Pulse Genertor Sum7 Mux Mux xlddsu Gtewy In AddSu1 Constnt Gtewy In4 Gtewy In6 f(u) sn l f(u) cos l f(u) l xlmult () g Mult xlmult () q Mult1 xlddsu + xlconvert cst g2_q Convert2 AddSu x_n xllckox2 x_out clk_ sqrt xlconvert cst Convert1 dvdendquot dvsor xllckox2 clk_ remd snx dvdendquot dvsor xllckox2 clk_ remd cosx Gtewy xlconvert cstin2 Convert Gtewy In5 xlconvert cst Convert4 Gtewy In3 fpt dl Gtewy Out2 fpt dl Gtewy Out5 xlsmmux xlsmmux xlsmmux fpt dl snlr fpt dl coslr fpt dl modg Fgure 6 VA module mplementton nd smulton model The run-tme computton of the sne nd cosne functons computed n ccordnce wth equton (8) y the locks sn(α) nd cos(α). Tle 1 presents the IP module mplementton results (see next secton).

10 4 Implementton of Rotor-feld Orented Vector Control System The mplementtons of the reconfgurle vector control system contn three mjor elements tht cn clerly seprte n three ndependent ords. These three elements re the confgurton supervsor nd/or AD control crd, the 6 chnnel A/D converter nd the control-system mplementton FPGA crd(s). The ntercton etween these crds s sed on the vector control system structure nd reconfgurton lgorthms. The sx-chnnel A/D converter s DEM ADS7864 Texs Instruments ord, wth sx smultneous smplng chnnels, 2μs totl throughput per chnnel, 1MHz effectve smplng perod nd 12 t ccurcy. The A/D-converter smplng perod lmts the smplng perod of the control system. Even f the FPGA llow fster computng tmes, the A/D converter lmts the smplng perod to 12μs. Ths tme results from the fct tht the converted dt re trnsmtted serlly. The FPGA ords mplements the vector control system. The ord s composed of Xlnx Sprtn 3 XC3S-5FT256 chp. Tle 1 presents the IP lrry elements mplementton. The tle shows the LC (Logc Cell) slces consumed y ech lock, the worth pth dely ntroduced y the lock. There s shown the quntston error where the module cn e chrctersed y ths prmeter. Another chrcterstc of the modules s the mxmum workng frequency f sequentl crcuts mplement the module. The tle shows, tht the VA consumed the mxmum numer of logc cells. The mxmum dely ntroduced s round 48ns. The lowest workng frequency s 48MHz. These vlues were otned when ech module ws ndependently mplemented. In the ove tle, n.. mens not vlle, such s for the comntorl modules the mxmum clock frequency s unvlle. The most smple vector control structure s the vector control system wth current feedck modulton VSI-fed nducton motor wth rotor-foc. We consdered ths vector control structure for mplementton. Tle 1 shows lso the mplementton results of the mentoned structure. The ntroduced tme dely s 48ns nd llows mxmum workng frequency of 38MHz. We cn sy tht the 4496 slces consumed for the mplementton llow the mplementton n the Sprtn 3 chp. Conclusons Ths pper presented the mplementton n FPGA of vector control system for tndem converted fed FOC system. It presented n ntellectul property lrry, whch llows the smulton nd rpd prototypng of ny vector control system. The lrry s extensle to sensorless nd/or ntellgent control systems, ut ths ws not suject of ths pper.

11 Module nme Drect Phse Trnsformton Block Reverse Phse Trnsformton Block Sttor+Rotor-flux Compenston Tle 1 Chrcterstcs of the mplemented vector control lrry modules Slces needed for mplementton Worth pth dely ntroduced td[ns] Quntston error q e<1.5*10-4 n ~0 n. Mx. workng f[mhz] <q e<0.1 42,00 Vector Anlyser n. 166,90 Coordnte < n. Trnsformton Spce Vector n.. n. Modulton Current feedck n Modulton Flux Controller ~0.6*10-4 n. Speed Controller ~0.6*10-4 n. Flux+Speed qeflux -6* Controller -0.1<qespeed<0.16 DC-lnk Current Controller Reconfgurton n. Multplexer CSI current constnt *10-5<q e<5*10-5 n. multpler Totl Estmted resources 4496 slces 1058 FF 9334 LUT n From the mplementton results of ech element one cn estmte the hrdwre needed to mplement the vector control system, the mxmum dely ntroduced y the system, whch nfluence the smplng perod of the control system, nd cn nlyse the quntston error of ech module, whch nfluence the computton ccurcy. We dd not ntend to compre the performnces of the mplemented control system compred to other mplementtons. We concentrted only on the reconfgurle vector control mplementton. We nlysed lso the condtons they re le to mplement vector control nd ther possle dsdvntges. The control system presents modulrty nd ths modulrty cn e used to crete module lrry. The modulrty cn help the reconfgurton process. erences [1] Kelemen A., Imecs M., Vector Control of AC Drves, OMIKK Pulsher Budpest, ISBN , Budpest, Hungry, 1992

12 [2] Auéprt F., Poure P., Brun F., Contruton to System-on-Chp n moton control: VLSI desgn of dgtl controller for n nducton mchne, PCIM 2001 Power Electroncs Intellgent Moton Power Qulty, June 19-21, 2001 Nuremerg, Germny, pp [3] Beerke S., Rpd Implementton of Feld-Orented Control Method for Fxed-Pont DSP Controlled Asynchronous Servo Drves, Europen Power Electroncs Chpter Symposum on Electrc Drve Desgn nd Applctons, orgnzed y EPFL Lusnne, Swtzerlnd; Oct. 1994, pp [4] Belmmoun M. H., Monmsson E., Smus E., Modulrty n Code Development for DTSFC Algorthms Implementton on Fxed-Pont DSP, PCIM 2002 Power Electroncs, Intellgent Moton, Power Qulty, My 12-16, 2002 Nuremerg, Germny, pp [5] Crste M., McCormck M., Intellgent ASIC control of power electroncs, Proceedngs of PCIM 98 Conference on Power Converson nd Intellgent Moton, Nuremerg, Germny, My 1998, pp [6] Crste M., Aouns A., McCormck M., Rpd Prototypng of Inducton Motor Vector Control System Bsed on Reusle VHDL Dgtl Archtectures nd FPGA Implementton, PCIM 2002 Power Electroncs Intellgent Moton Power Qulty, My 14-16, 2002 Nuremerg, Germny, pp [7] Imecs M., Bkflv P, Nedevsch S., Vásárhely J.: Implementton of Confgurle Controller for n AC Drve Control Cse Study, Proceedngs of IEEE Symposum on FCCM 2000, Np, Clforn, USA, 2000 pp [8] Imecs M., Bkflv P, Nedevsch S., Vásárhely J.: Implementton of Reconfgurle Controller for n AC Drve Control, on the CD of the Proceedng of Control 2000 Conference CD-ROM nd Book of Astrcts Control 2000, Oxford, pp. 199 [9] Imecs Mr, Incze I. I., Vásárhely J., Szó Cs.: Tndem Converter Fed Inducton Motor Drve Controlled Wth Re-Confgurle Vector Control System, PCIM 2001 Power Electroncs Intellgent Moton Power Qulty, June 19-21, 2001 Nuremerg, Germny, pp nd CD-ROM [10] Imecs M., Vásárhely J., Incze J. J., Szó Cs.: Vector Control Of Tndem Converter Fed Inducton Motor Drve Usng Confgurle System On A Chp, INES 2001 IEEE Interntonl Conference on Intellgent Engneerng Systems, Septemer 16-18, 2001, Helsnk-Stockholm-Helsnk, Fnlnd- Sweden, pp [11] Imecs M., Incze I. I., Szó Cs.: Control Strteges of Inducton Motor Fed y Tndem DC Lnk Frequency Converter, Europen Conference on

13 Power Electroncs nd Applcton, EPE 2001, Grz, Aug. 2001, Book of Astrcts p. L1-7 nd CD-ROM [12] Imecs M., Trzyndlowsk A. M., Ptrcu N., Rdn Kreszer M.: Aout Performnces of Current Controlled SVM-VSI nd Tndem Inverter Used n Inducton Motor Drves, SPEEDAM 2000, Isch, Itly, pp C4-7 C4-12, 2000 [13] Imecs M., Incze J. J., Szó CS., Vásárhely J.: Smple Approch For Inducton Motor Control usng Reconfgurle Hrdwre, Proceedngs of the Ntonl Conference on Automton CNAE 2002, ISBN , Glt, Romn, pp , 2002 [14] Mkmoto T.: The Rsng Wve of Feld Progrmmlty, Proceedngs of Feld Progrmmle Applctons FPL2000, Vllch, Austr, August 2000, pp.1-6 [15] Monmsson, E., Hpot J. C., Grndperre M.: A Dgtl Control System Bsed on Feld Progrmmle Gte Arry for AC Drves. EPE Journl, Vol. 3, no. 4 (1993), pp [16] Poure P., Auéprt F., Brun F., ICs for rel tme Moton Control: A desgn methodology for rpd prototypng, PCIM 2001 Power Electroncs Intellgent Moton Power Qulty, June 19-21, 2001 Nuremerg, Germny, pp [17] Vásárhely J., Imecs M., Incze J. J., Szó Cs.: Module Lrry for Rpd Prototypng nd Hrdwre Implementton of Vector Control Systems, INES 2002 IEEE Interntonl Conference on Intellgent Engneerng Systems, My 26-28, 2002, Optj, Crot, ISBN , pp [18] Vásárhely J.: Reconfgurle Archtectures for Vector Control Structures of Inducton Motor Drves, PhD thess, Techncl Unversty of Cluj, Romn, Aprl 4, 2004, pp.180 [19] Imecs M., Trzyndlowsk A. M., Incze I. I., Szo Cs.: Vector control schemes for tndem-converter fed nducton motor drves, IEEE Trnsctons n Power Electroncs. Vol. 20, no. 2, 2005, pp