A Novel Control Method for Input Output Harmonic Elimination of the PWM Boost Type Rectifier Under Unbalanced Operating Conditions

Transcription

1 A Novel Control Method for nput Output Hrmonc Elmnton of the PWM Boost Type Rectfer Under Unblnced Opertng Condtons A. V. Stnkovc T. A. Lpo Electrcl nd Computer Engneerng Clevelnd Stte Unversty Deprtment of Electrcl nd Computer Engneerng Unversty of Wsconsn-Mdson Abstrct-Ths pper presents new control strtegy to mprove the performnce of the PWM Boost Type Rectfer when opertng under n unblnced supply. An nlytcl soluton for hrmonc elmnton under unblnced nput voltges s obtned resultng n smooth (constnt power flow from c to dc sde n spte of the unblnced voltge condton. Bsed on the nlyss of the open loop confgurton, closed loop control soluton s proposed. Smulton results show excellent response nd stble operton of the new rectfer control lgorthm. A lbortory prototype hs been desgned to verfy the dscussons nd nlyses done n ths pper. Theoretcl nd expermentl results show excellent greement. Elmnton of the possblty of low order c nd dc sde hrmoncs due to unblnce s expected to mterlly ffect the cost of dc lnk cpctor nd c sde flter. The proposed method wll be prtculrly useful n pplctons where the lrge second hrmonc t the DC lnk my hve severe mpct on system stblty of multply connected converters on common lnk.. NTRODUCTON The Boost Type PWM Rectfer hs been ncresngly employed n recent yers snce t offers the possblty of low dstorton lne current wth unty power fctor for ny lod condton [] [6]. Another dvntge over trdtonl phse-controlled thyrstor rectfers s ts cpblty for nerly nstntneous reversl of power flow. Unfortuntely, the fetures the PWM Boost Type Rectfer offers re fully relzed only when the supply three phse nput voltge source s blnced both n terms of ts Thevenn equvlent voltge nd mpednce, whch s often not the cse n rel power system. t hs been shown [] tht unblnced nput voltges or mpednces cuse n bnorml second hrmonc t the dc bus whch reflects bck to the nput cusng (nonzero sequence thrd-order hrmonc current to flow. Next, the thrd-order hrmonc current cuses fourth-order hrmonc voltge on the dc bus, nd so on. Ths results n the ppernce of even hrmoncs t the dc output nd odd hrmoncs n the nput currents. These ddtonl components cuse dded losses n the dc lnk flter cpctor. They must lso be consdered n the flter desgn of these converters snce they clerly dd to the cost becuse they re of low frequency. n ddton, rpple on the dc lnk s known cuse of ntercton between current regultors whch cn even cuse system nstblty [7]. The problem ncreses n severty s the number of converters connected to the lnk ncreses. Whle n ttempt ws mde to reduce low order hrmoncs t the nput nd the output of the PWM Boost Type Rectfer under unblnce [4], hrmoncs were only reduced but not elmnted. Enjet nd Choudhury [5] proposed method for the hrmonc elmnton of the buck c to dc converter under unblnced condtons. However, the pproch does not lend tself well to the more populr boost type rectfer so tht n exct soluton for ths problem hs never been ddressed. Ths pper proposes completely new control strtegy for hrmonc elmnton of the PWM Boost Type rectfer opertng under unblnced nput voltges. Specfclly, by PWM current regulton, the mgntudes nd the phse ngles of the three nput currents re ndependntly djusted n order to mntn smooth output dc voltge level entrely elmntng low-order hrmoncs. The proposed technque mntns hgh qulty snusodl current nput nd dc current output even though the nput voltges remn unblnced. However, the power fctor cnnot be djusted n ths cse. Ths s not seen s dsdvntge prtculrly n stutons where mblnce n the nput supply s temporry phenomenon. Smulton s well s expermentl results s presented to confrm the proposed control strtegy. The theoretcl nd expermentl results show excellent greement.. THEORETCAL APPROACH n Fg. t s ssumed tht the PWM rectfer s suppled by unblnced nput voltges but blnced nput mpednces. The ssumptons used n the dervton re:. The system s lossless.. The swtchng functons used to represent swtchng cton of the converter re unblnced but contn no zero sequence.. Only fundmentl components of swtchng functons nd SW, SW, SW nput currents re tken nto ccount (PWM swtchng hrmoncs re not consdered. By usng symmetrcl component theory, lne to neutrl swtchng functons re gven s: SW SW SW. S S 0 (

2 Snce the zero sequence current s never present n ths crcut, currents, nd re gven by,. 0 where S nd S re postve nd negtve sequence swtchng functons, nd re postve nd negtve 0 sequence currents nd 0 Output current 0 s gven by, 0 SW SW SW ( S S ( ( S S ( ( S S ( S S ( n the tme domn, the pulstng component of the output current s expressed s: 0 ( jwt j Re l( s jwt j t S e e Re l( e e jwt j s jwt j Re l( S e e Re l( e e By usng trgonometrc dentty: cos( cos( cos( cos( one rrves t the result: [ ] o(wt S cos(wt s S cos(wt s The bove equton shows the presence of the second-order hrmonc t the output of the rectfer. t lso ndctes tht the second-order hrmonc could be elmnted under the followng condtons. ( (4 (5 Z U Vs (7 Z U V s (8 wherev s ndv s re the postve nd negtve sequence voltges t the rectfer nput ndu ndu re the postve nd negtve sequence nput voltges. V s Vdc S wherevdc where Pdc s the s the, V s Vdc S output dc voltge. Pdc Rel(U U The soluton for hrmonc elmnton s obtned by combnng (6, (7, (8 nd (9. The soluton s gven by the followng set of equtons: S. S. u. S 4. sn ( U U s u s The set of four equtons shown bove represents the stedystte soluton for nput-output hrmonc elmnton of the PWM Boost Type Rectfer under unblnced nput voltges. A. The Physcl Menng of the Proposed Soluton n d-q Sttonry Frme The proposed soluton for hrmonc elmnton cn be explned n the d-q sttonry frme, where cncellton of nput verge output power. u U cos( Vdc u s Pdc Z s ( U U (9 (0 ( ( (. S S. s s (6 - where S, S, s nd s re mgntudes nd phse shfts of postve nd negtve swtchng functons.,, nd re mgntudes nd phse shfts of nput currents. The per-phse equvlent crcut under unblnced nput voltges nd unblnced syntheszed voltges t the nput of the rectfer re shown n Fg.. From Fg., two ddtonl equtons cn be obtned nd gven by, U U U L SW SW SW L L 0 Vdc L O A D From the power equton, the followng reltonshp cn be obtned: Fg. The PWM Boost Type Rectfer

3 Z U Vs U Vs Fg. Per-phse postve nd negtve sequence equvlent crcut pulstng power becomes more obvous. The postve nd negtve sequence components of the nput voltges nd currents re nstntneous qunttes nd re shown on Fg.. The nstntneous power nput, p (t s gven by: p t p p p p ( ( 0 t (4 where, p 0( t ( u pqpq u pdpd unqnq undnd (5 p ( t ( u pqnq unqpq u pdnd undpd (6 p( t ( u pdpq u pqpd (7 p( t ( undnq unqnd (8 The frst term, p 0 ( t, represents the constnt porton of nput pulstng power, snce ll ts components re products of n-phse q nd d qunttes of the postve nd negtve sequence nput voltges nd currents. Ths term lso exsts n blnced three-phse system. The second term, p ( t, represents the pulstng porton, snce ll ts components re products of the postve nd negtve n-phse components of nput currents nd voltges. t bsclly represents mutul ntercton between postve nd negtve sequence qunttes, whch normlly does not exst n blnced three-phse system. The thrd term, p ( t, represents the ntercton between d nd q postve sequence qunttes. Ths term exsts n blnced three-phse system. The fourth term, p ( t, represents the ntercton between d nd q negtve sequence qunttes. Ths term does not normlly exst n blnced three-phse system. u n (t d n (t Fg. The postve nd negtve sequence nput voltges nd currents n d-q sttonry frme Smlrly, nstntneous power on the nductor, p l (t, conssts of three prts nd cn be expressed s: q u p p Z pl wl( pdnq pqnd (9 p l wl( pq pq pd pd (0 p l wl( nqnq ndnd ( The soluton for second hrmonc elmnton ssumes the followng form:. p pl (. p pl (. p pl (4 The power gong nto the converter s gven by, pc p( t pl (5 The power gong nto the converter, s shown n Fg.4, s constnt snce ll the other components re shown to cncel out.. CONTROL METHOD Bsed on the nlyss of the open loop confgurton presented bove, feed-forwrd control method s proposed. n order to control the output dc voltge nd elmnte hrmoncs t the nput nd output of the PWM Boost Type Rectfer under unblnce, not only current mgntudes but lso ther phse ngles hve to be controlled. The DC bus error s used to synthesze the mgntudes nd the phse ngles of the postve nd negtve sequence reference currents. The sequence components re then trnsformed nto three phse (bc qunttes whch become reference sgnls for the hysteress controller []. The reltonshp between nput currents nd nput voltges n the open loop confgurton for hrmonc elmnton s obtned by combnng (7, (8, (0 nd ( nd gven by, U U (6 u u (7 However, t s lwys true tht verge power nput s equl to verge power output nd gven by the followng equton, Pdc Vdcdc U cos( u U cos( u (8 The output DC voltge s proportonl to the postve nd negtve sequence currents (mgntudes, so s the error sgnl ( V Vdc. n order to stsfy (6, the condton for ref second hrmonc elmnton, the postve nd negtve sequence commnds for current mgntudes should stsfy (9 nd (0.

4 K p U ( Vref Vdc (9 K p U ( Vref Vdc (0 p(t (t p l 0 u K p cos( Vref Vdc ( where cos s n nverse cosne functon. Equtons ( nd ( re pproxmted by the followng two equtons: u K p( Vref Vdc ( u K p( Vref Vdc (4 Postve nd negtve sequence current commnds re trnsformed to bc qunttes nd used s references for hysreress controller. The trnsformton s gven by, ref sn( wt sn( wt (5 ref (6 sn( wt sn( wt ref sn( wt sn( wt (7 Only two proportonl controllers re utlzed (one for the mgntude, the other for phse ngle control whch hs been determned to be suffcent for good regulton. An ntegrl controller cn be dded to further reduce the stedy stte error. The proposed control method s shown n more detl n Fgure 5. U L U U L CONVERTER L Vdc L O A D p c ( t p 0 constnt Fgure 4. Cncellton of the nstntneous pulstng power Equtons (9 nd (0 represent postve nd negtve sequence mgntude commnds. The postve nd negtve sequence commnds for phse ngles re derved from (7 nd (8. Therefore, the phse ngle commnds re gven by, K cos( V V ( u p ref dc

5 U U U ref Control Logc L L L Control Logc Unblnced Detector nd Symetrcl Component Clcultor Trnsform. To bc ref Hysteress Controller ref h SW SW Current Sensors SW Lmter 0 Voltge Sensor Vdcref Fgure 5. The proposed control loop soluton under unblnced nput voltges. V SMULATON AND EXPERMENTAL RESULTS n order to demonstrte fesblty, the system shown n Fg. 5 hs been smulted n SABER. The prmeters used for the smulton re shown n Tble. TABLE Prmeters used n smulton Prmeter Vlue Prmeter Vlue nput supply U 00V DC-lnk 00 F pek voltges U 05V cpctor, C U 04V DC-lnk voltge, V dc nput, L nductnces 70V Output resstve lod, R mh Fundmentl frequency, f Kp Kp Vdc 00Ω 50Hz The plot n Fg.6 shows the controlled output dc voltge under unblnced nput voltges. t lso gves the current commnds for the hysteress controller. Good control of the dc voltge s evdent n spte of the phse unblnce. A lbortory prototype ws bult to confrm the theoretcl results. The brdge conssts of sx GBT swtches nd sx dodes connected n prllel. The control crcut conssts of: voltge sensor bord, current sensor bord, L O A D hysteress bord, gte drver bord nd DSP56000 development system, s shown n Fg.7. CPU runs t 7MHz nd s connected to n BM personl computer. The zero voltge detector long wth one counter (counter ( whch runs t MHz,mesures the frequency of the system nd synchronzes the control functons (current commnds for D/A converter. The output of the zero voltge detector, s shown n Fg.7, s connected to the nterrupt lne (prorty level nd to the gte of the counter. On the fllng edge of the nput sgnl, the output of the zero crossng detector, counter ( stops countng. Snce the progrm jumps nto nterrupt subroutne t tht pont (RQ, the second counter (counter (, whch runs t 8Mhz, gets loded wth the vlue mesured by counter ( dvded by 55. n other words, the second counter s loded by T/55 whch represents the smplng tme of the system. Snce the frequency of the network my vry, the ppernce of the second nterrupt my vry ccordngly. The hysteress bord conssts of three comprtors nd three nverters. The nputs to the three comprtors, s shown n Fg.7, come from the current sensor bord nd the outputs of the D/A bord. The softwre hs been wrtten n ssembly lnguge nd conssts of mn loop nd two levels of nterrupton loops. The mn structure of the progrm s shown n Fg.8. The frst level of nterrupton loop (RQ occurs once n cycle. t detects the zero ponts of the nput voltge. Ths subroutne sets the vlue n counter ( to be T/55. t lso reds the nstntneous vlues of the three nput voltges nd clcultes vrbles necessry for clcultng the sequence components of the three nput voltges. At the end of ths subroutne current commnds re sent to the D/A converter. Fg.9 shows the smplfed flowchrt of the loop RQ. The second level of the nterrupton loop (RQ occurs 55 tmes cycle. t mesures the nput voltges nd clcultes vrbles necessry for clcultng the sequence components. At the end of ths subroutne, the commnds for three nput currents re sent to D/A converters. Fg.0 shows the smplfed flowchrt of the loop RQ. The mn loop (MAN occurs once cycle nd clcultes the sequence components of the three nput voltges bsed on mesurements nd clcultons performed n two nterrupton loops. t lso mesures the output dc voltge nd clcultes the error between ts set nd mesured vlue. Fnlly, t clcultes the sequence commnds for the three nput currents. Fg. shows the smplfed flowchrt of the loop MAN. Expermentl results re shown on Fg., Fg., nd Fg.4. Fg. shows nput currents n phse nd phse under unblnced nput voltges. The currents re unblnced, s expected, to cncel the pulstng power comng from the nput. The currents re snusodl nd do not contn low-order hrmoncs. Fg. shows the output dc voltge of the PWM Boost Type Rectfer under unblnced supply voltges. Fg.4 shows the frequency spectrum of the output DC voltge. Phse s sgnfcntly unblnced (by 50% wth respect to other two phses. n spte of the level of unblnce, the output voltge s smooth nd contns no low order hrmoncs.

6 Fg. 6. Controlled output voltge, nput currents nd commnds for the hysteress controllers (smulton results. Fgure 8. The mn structure of the progrm Fgure 7. Hrdwre confgurton Fgure 9. Flowchrt of nterrupton loop (RQ

7 Fgure. Currents n phse nd under unblnced nput voltges (expermentl results Fgure 0. Flowchrt of nterrupton loop (RQ Fgure. Controlled output dc voltge nd three nput voltges (expermentl results Fgure 4. Frequency spectrum of the output dc voltge (expermentl results V. CONCLUSONS Fgure. Flowchrt of the mn loop (MAN Ths pper proposes new control strtegy to mprove the performnce of the PWM Boost Type Rectfer under unblnced opertng condtons. An nlytcl soluton for

8 hrmonc elmnton under unblnced nput voltges nd blnced nput mpednces s obtned. Bsed on nlyss of the open loop confgurton, closed loop soluton s proposed. Wth the proposed technque, hgh qulty nput nd output wveforms re mntned under unblnced nput voltges nd blnced nput mpednces. The smulton results show the excellent response nd stble operton of the PWM Boost Type Rectfer under unblnced opertng condtons when ths method s ppled. The lbortory prototype hs been desgned to verfy the dscussons nd nlyses done n ths pper. An excellent greement occurs between the theoretcl nd expermentl results. REFERENCES [] L. Morn, P.D. Zogs, nd G. Joos, Desgn Aspects of Synchronous PWM Rectfer-nverter System Under Unblnced nput Voltge Condtons, EEE Trnsctons on ndustry Applctons, vol. 8, no. 6, pp.86-9, Nov./Dec. 99. [] J.W. Wlson, The Forced-Commutted nverter As Regenertve Rectfer, EEE Trnsctons on ndustry Applctons, vol. A-4, no. 4, pp. 5-40, July/Aug [] D.M. Brod nd D.W. Novotny, Current Control of VS-PWM nverters, EEE Trnsctons on ndustry Applctons, vol. A-, no. 4, pp , Nov./Dec [4] P. Roul, H. Poulquen, nd J.P Lous, Regulton of PWM Rectfer n the Unblnced Network Stte, EEE- PESC, Conf. Rec., pp , 99. [5] P. Enjet nd S.A. Choudhury, A new Control Strtegy to mprove the Performnce of PWM AC to DC Converter Under Unblnced Opertng Condtons, EEE- PESC Con.Rec., 99, pp [6] T.A. Lpo, Recent Progress nd Development of Sold Stte AC Motor Drves, EEE Trnsctons on Power Electroncs, vol., no., pp. 05-7, Aprl 988. [7] R.P. Strtford, D.E. Steeper, "Rectve Compenston nd Hrmonc Supresson for ndustrl Power Systems Usng Thyrstor Converters", 974 AS Annul Meetng, pp.