Single-Phase SOGI-PLL Based Reference Current Extraction for Three-Phase Four-Wire DSTATCOM

Transcription

1 Sngle-Phse SOG-PLL Bsed Reference Current Extrcton for Three-Phse Four-Wre DSTATCOM Hreesh Kumr Yd Reserch Scholr, Deprtment of Electrcl Engneerng, JNTU, Hyderbd, Telngn, NDA. Dr.M.S.R Murthy Professor, Deprtment of Electrcl Engneerng, ATR, Hyderbd, Telngn, NDA. Abstrct Ths pper descrbes novel control lgorthm bsed on sngle-phse SOG (Second Order Generlzed ntegrtor PLL (Phse Locked Loop for three-phse fourwre DSTATCOM (Dstrbuton Sttc Compenstor. The proposed DSTATCOM performs vrous functons such s lod blncng, hrmonc mtgton, rectve power compenston nd neutrl current compenston under dstorted lod condtons. Ths control lgorthm extrcts the fundmentl component of the lod currents for estmtng the reference currents bsed on three sngle-phse SOG-PLLs. The mn objectve of the controller s to reduce the overll complexty nd computtonl burden. SOG-PLL s enhncng the cpblty of reference current trckng for compenston under the step chnges n lod currents. Durng the desgn procedure, the effects of lod unblncng nd sudden ncrese/decrese n lods re lso tken nto ccount nd performnce s found stsfctory. The effectveness of the desgn s smulted nd shown usng MATLAB/Smulnk. ndex Terms Second Order Generlzed ntegrtor, Phse -Locked Loop, DSTATCOM, Lod blncng, Power Qulty (PQ. E. NTRODUCTON FFCENT phse trckng cpblty for utlty grd voltge s the mportnt fctor n converters for custom power pplctons. The reference component generted from the phse-locked loop decdes the performnce of the converters for compenstng power qulty problems such s lod unblnce, hrmonc mtgton, hgh neutrl current nd rectve power compenston. The PLL should respond effectvely n dstorted lod condtons by detectng the phse ngle nd mpltude t fster rte. n recent dys, Non-lner lods re ncresed extensvely t the utlty end nd cusng power qulty problems t the PCC n the supply system [1]. These nonlner lods nclude dode brdge rectfers, vrble speed drves, thyrstor converters nd vrble power supples []. Hrmoncs ply mjor role n the power qulty problems t the consumer end nd shunt ctve power flter s the crucl tool n mtgtng hrmoncs nd lso other PQ ssues [] [4]. Vrous reserchers hve dscussed numerous control technques for estmton of reference components to mtgte PQ problems usng three-phse four-wre DSTATCOM. The neutrl current should not be more thn % of the full lod current [5]-[6]. Severl PLL technques hve been ntroduced for detectng the mpltude nd phse ngle for grd-connected systems. A three phse Synchronous Reference Frme PLL gves stsfctory performnce under del condtons but poor performnce under dstorton [7]. The DFT (Dgtl Fourer Trnsform nd RDFT (Recursve Dgtl Fourer Trnsform re frequency domn pproches tht suffer from hgh computtonl burden but wdely used owng to ccurcy [8]-[1]. Josep M. Guerrero nd Seed Golestn hve been deeply nlyzed the structures of two dfferent PLLs nmely SOG nd Prk PLL [11]. The LPN-PLL nd Prefltered SRF PLL ws excellent under stedy-stte nd 1

2 Fg. 1 Lne Dgrm of the Proposed System. trnsent condtons n comprson wth SRF-PLL [1]- [1]. Severl control lgorthms hs been developed for the stsfctory operton of DSTATCOM [14]-[16]. n ths pper, novel control lgorthm usng SOG- PLL hs been ntroduced for extrctng the reference components under dstorted lod condtons. The proposed lgorthm mntns blnced snusodl currents wth stff DC bus voltge t DSTATCOM. Ths control lgorthm s used to reduce hrmoncs nd rectve power compenston under unblnced non lner lods. The control structure hs dvntges, Ampltude nd Phse detecton ccordng to the chnge n requrements. b Speed nd Accurcy c fundmentl component extrcton under dverse lod condtons. Fnlly, n effectve mplementton of the lgorthm to reduce the overll computtonl burden, low bulkness nd low complexty n desgn nd vrble compenston for three-phse fourwre DSTATCOM s presented. Ths pproch s bsed on sngle-phse SOG-PLL to extrct three phse reference components. n ths technque, Power qulty mprovement wth neutrl current compenston s lso done usng four leg VSC nd the effectveness of the system s shown through smulton results. Smultons re crred out usng MATLAB/Smulnk, smpower systems block set.. PROPOSED SYSTEM CONFGURATON Fg. 1 shows lne dgrm of the proposed system wth control dgrm for four leg VSC (Voltge Source Converter feedng nonlner lods. The DSTATCOM s connected n prllel to the source nd lod t the Pont of Common Couplng (PCC through nterfcng nductor L c to reduce the rpple currents n the controller current. The VS bsed DSTATCOM s cpble of suppressng the hrmoncs n the source currents, power fctor correcton nd lod blncng. A smll cpcty rted R-C flter s connected n prllel wth the source to elmnte the hgh swtchng rpple content of the VSC. DSTATCOM s connected to the.c mns through source mpednce (R s, L s nd Lods. The lod under consderton s combnton of lner nd non-lner type. A rpple flter (R f, C f s lso connected n prllel to the lod nd source to reduce the hgh frequency nose t the PCC. The controller currents ( c, cb, cc re njected nto PCC to compenste hrmoncs nd rectve power n the lod. The lod current s sensed nd mde s nput to the SOG PLL to extrct the ccurte phse nd mpltude. The SOG PLL s chosen becuse of ts low computtonl burden nd desred performnce under dstorted condtons.. CONTROL ALGORTHM The control lgorthm conssts of four modules: SOG PLL, Actve & Rectve Component Extrcton, Reference Current Generton nd Current Controller. A. SOG-PLL The bsc block dgrm of the PLL s shown n Fg.. The bsc PLL conssts of three buldng blocks s shown n Fg.. 1 Phse Detector tht genertes sgnl whch s the dfference n phse between the nput nd feedbck sgnl nd then t s pssed through the loop flter (LF. LF s used to control the Voltge Controlled Osclltor (VCO. VCO genertes the frequency sgnl from ts nomnl frequency. The proposed method of desgnng SOG PLL s shown n Fg.. n fg (b, the outputs nd β genertes two sne wves wth phse shft of 9. The component nd Lα L hs the sme mgntude nd phse. The SOG structure s defned s [11]. w G (1 s + w Where w- Resonnce Frequency of the SOG Lα H d ( H L Lβ q ( L The k shown n fgure. ffects the bndwdth of the closed-loop system. When the grd frequency hs fluctutons, problems my occur s the structure s frequency dependent. Hence, the w vlue of the SOG s tuned ccordng to the frequency provded by the PLL structure. Lα L

3 Fg. Block Dgrm of PLL. Usng the proposed method, the nput L f fltered ledng to two wveforms ( nd β becuse of the resonnt Lα frequency. The gn k decdes the level of flterng nd the flter bnd pss becomes nrrower nd dynmc response wll become slower wth the decrese n k. Prk trnsformton s used to convert αβ to dq. cos ˆ θ sn ˆ θ T (4 sn ˆ θ cos ˆ θ To ttenute the hgh frequency noses, the trnsformton output Lq s pssed through Proportonl ntegrl (P controller. The fundmentl frequency (W ff s dded to the P control sgnl nd then t s ntegrted to generte the estmted phse ngleθˆ. n order to get blnced set of n-qudrture outputs wth exct mpltudes, the SOG frequency must be equl to the nput fundmentl frequency. B. Estmton of Unt Voltge Templtes The bsc equtons for estmton of the dfferent control sgnls re shown below. The three phse source voltges my be unblnced or conssts of hrmoncs nd those re processed through flters to elmnte the nose nd hrmoncs. The ndvdul phses re estmted through squrng them nd then processed through flters s follows [16]. L V V V ' t ' tb ' tc v s (, v sb ( v sc ( Where, (v s, v sb, nd v sc re the phse voltges nd V t, V tb, V tc re the constnt vlue mpltudes. The n-phse unt templtes of PCC voltges re estmted s: v s sb u ; ub ; uc Vt Vtb v v V Qudrture unt templtes of PCC voltges re estmted s: ( ub + uc ( u + ub u w, wb c, (9 ( u + ub uc wc sc The mpltude of the PCC voltge s estmted s: v' t ( v s + v sb + v sc Ths mpltude ( v' s suppled to the low pss flter to t reduce the rpples nd to ttn the mpltude of the fundmentl postve-sequence voltges for controllng the PCC voltges. These unt vector templtes re now used to extrct the ctve nd rectve components of currents. tc (5 (6 (7 ` (8 (1 ( Fg.4 Block Dgrm of Actve nd Rectve Component Extrcton (b Fg. Bsc Desgn of SOG PLL b SOG Block. C. Actve nd Rectve Component Extrcton Fg.4 shows the block dgrm of the ctve nd rectve component extrcton bsed on SOG PLL scheme. n ths lgorthm, lod currents ( L, Lb, Lc, unt vector (u,u b,u c

4 nd qudrture vector templtes (w,w b,w c re requred for extrcton of n-phse ( ph nd qudrture currents ( qh. The n-phse component nd qudrture component for ech phses,b,c re clculted s follows: p α w + β u q - α u + β w pb αb w b + βb u b qb - αb u b + βb w b pc αc w c + βc u c qc - αc u c + βc w c (11 (1 (1 (14 (15 (16 The verge mpltude of ctve nd rectve components of the three phse lod currents re estmted for lod blncng nd to be used n the extrcton of three phse source currents s: ph qh p q + pb qb D. Reference Current Generton pc qc Fg.5 shows the block dgrm of the reference current generton. Ths block requres DC lnk voltge (V dc, Lod Voltges (V bcl, ctve, rectve component of currents ( ph, qh nd unt vector templtes to generte the reference source currents. The voltge cross the DC cpctor V dc s sensed nd compred wth the reference DC bus voltge V * dc nd ths error t the n th smplng nstnt s expressed s: V de (n V * dc(n - V dc (n (19 Ths voltge error s fed to P controller to mntn the DC voltge of the DSTATCOM. At n th smplng nstnt, the output of the P controller s s: Fg.5 Block Dgrm of Reference Currents Generton (17 (18 cd (n cd (n-1+k pt {v dcer (n-v dcer (n-1}+k t v dcer (n ( Where, K pt nd K t re the proportonl nd ntegrl gn constnts of the P controller. V de (n nd V de (n-1 re the voltge errors of the DC bus n n th nd n-1 th nstnt nd cd (n nd cd (n-1 re the mpltude of ctve power component of the fundmentl reference current t n th nd (n-1 th nstnt. u + (1 sp sbp b ( ph cd ( ph cd ( u + scp u c ph + cd ( The output of the P controller ( cd s summed to the mpltude of ctve component ( ph nd the resultnt s multpled wth the unt vector of the three phses (u, u b, u c to generte the mpltude of fundmentl ctve component of current sp, sb bp nd scp respectvely s shown n fg.5. The voltge cross the lod s used to generte the mpltude of the lod voltge (V tm s n (1 nd compred wth the reference lod voltge V * tm nd ths error t the n th smplng nstnt s expressed s: * V ( r V ( r V ( r (4 ter t t Ths voltge error s fed to P controller to regulte the AC voltge to ts reference vlue. At n th smplng nstnt, the output of the P controller s s: ( r ( r 1 + k { V ( r V ( r 1 } k V ( r (5 cq cq pt ter Where, K pt nd K t re the proportonl nd ntegrl gn constnts of the P controller. V ter (r nd V ter (r-1 re the voltge errors of the AC bus n r th nd r-1 th nstnt nd cq (r nd cq (r-1 re the mpltude of rectve power component of the fundmentl reference current t r th nd (r-1 th nstnt. The output of the P controller ( cq s summed to the mpltude of rectve component ( qh nd the resultnt s multpled wth the unt qudrture vector of the three phses (w, w b, w c c to generte the mpltude of fundmentl rectve component of current sq, sbq nd scq respectvely s shown n fg.5. w + (6 sq sbq b ( qh cq ( qh cq ( w + w + scq c qh cq ter + ( Fnlly, the ctve nd rectve component of currents re summed to generte reference supply currents s *, sb *, sc * respectvely. * s sp + sq (9 * sb sbp + scq ( * sc scp + scq (1 t ter (7 (8 4

5 PCC Voltge Source Current njected Current Nuetrl Current Dc Lnk Voltge Vs Vsb Vsc s sb sc Tme (sec Fg. 6 Performnce of DSTATCOM for the consdered L Lb Lc c cb cc sn Vdc Ln These estmted three phse reference source currents (* s, * sb, * sc nd * sn re compred wth sensed source currents ( s, sb, sc nd sn ( s + sb + sc to estmte the current errors. These errors re regulted usng P controllers nd re compred wth crrer sgnls to generte PWM pulses for DSTATCOM. V. SMULATON RESULTS AND DSCUSSON The proposed control lgorthm for three-phse fourwre DSTATCOM s modeled n MATLAB / Smulnk usng Smpower systems toolbox. The performnce of the control lgorthm s studed for hrmonc compenston, lod compenston/neutrl current Compenston nd Power Fctor correcton/rectve Power Compenston whch re dscussed ndvdully n ths secton. Fg. 6. Shows the PCC-Voltge (Vpcc, Source Current (s_bc, s ( L, Lb, Lc, Compenston Currents (c_bc, Neutrl Currents ( N_S, N_L nd the DC-Bus voltge (Vdc. The prmeters for the system re gven n ppendx. Quntty A. Hrmonc Compenston Fg. 7 nd Fg.8 shows the results for the cse hrmonc compenston. A sngle phse-current source type of nonlner lod s ppled on ll the three phses for whch the source currents re obtned snusodl. The hrmonc spectrum for the nonlner lod currents nd the obtned source currents re shown n the fg. 8. Lod current ( L hve THD of 5.17% wth fundmentl component of 5.44A nd the source current hs THD of 1.7% wth fundmentl component of 4.19A. Thus, the mgntude nd THD of the Lod currents nd the source currents shows the effectveness of the proposed control lgorthm. B. Lod / Neutrl Current Compenston The performnce of the DSTATCOM wth the proposed control lgorthm for the unblnced nd vryng lods for the cse of lod compenston/neutrl current compenston s shown n fg.7 nd fg.1. The unblnce n the lod s creted by openng the phse, phse b durng 1.9sec to.5sec nd sec to.15sec respectvely. Tble- Source Source s s Source Currents s Currents Currents THD % THD % THD % THD % THD % THD % Norml Condton Un-Blnced Condton ncrese n Lod Condton Ph Ph-b Ph-c

6 PCC Voltge Vs Vsb Vsc Source Current s sb sc L Lb Lc njected Current c cb cc Nuetrl Current sn Ln Dc Lnk Voltge Vdc Tme (sec Fg. 7 Performnce of DSTATCOM under unblnced nd vryng nonlner lods sbc Lbc Mg (% of Fundmentl Mg (% of Fundmentl Tme (s FFT wndow: of 14 cycles of selected sgnl Fundmentl (5Hz 5.8, THD 5.% Hrmonc Order Tme (s Fundmentl (5Hz 4.19, THD 1.7% Hrmonc order Fg. 8. Hrmonc Spectrum of -ph of Lod Current nd Source Current The ncrese n lod neutrl current cn be observed wth the ncrese n the unblnced lod currents shown n fg.1. The source neutrl current s observed to be lmost zero, whch presents the effectveness of the control lgorthm. The source currents re observed to be blnce under ll these condtons. The DC bus voltge of DSTATCOM s regulted to the reference vlue under ll lod condtons. The vlues of ech phse currents re tbulted wth ll the condtons n Tble-. C. Rectve Power Compenston / Power Fctor Correcton Power fctor correcton t vrous lod condtons re shown n Fg. 9. The source voltge s scled to (1/V for effectve vsulzton of zero crossng of source current ( s nd Source Voltge (V s. From the fgure, t cn be observed tht the source current s n phse wth the source voltge t vrous lod condtons. 5 Source Voltge Source Current Fg. 9 Results presentng the zero crossng of source voltge nd source current t vrous lod levels 6

7 PCC Voltge Source Current njected Current Nuetrl Current Dc Lnk Voltge Vs Vsb Vsc s sb sc Tme (sec Fg.1 Performnce of DSTATCOM under Vryng Nonlner lod condtons A three-leg sngle-phse voltge source converter (VSC bsed DSTATCOM [15] requres 1 swtches nd hence the cost nd complexty s hgh. The splt cpctor bsed VSC hs dsdvntge of mntnng sme DC voltge t the seres cpctors [15]. Zg-Zg trnsformer wth three-leg VSC hs better performnce n neutrl current compenston but costly nd effectve desgn should be done [16]. A T-connected trnsformer lso requres two sngle-phse trnsformers nd compenston hs no much chnge compred wth the zg-zg trnsformer [17]. A str/delt trnsformer s lso reported n the lterture for neutrl current compenston [18]-[]. The dsdvntges of the bove mentoned topologes requre n ddtonl trnsformer speclly desgned for proper compenston. Becuse, the level of compenston s ffected by the trnsformer mpednce. The four-leg VSC bsed DSTATCOM s superor nd requres 8 swtches but the controller s to be tuned ccordngly. The proposed controller hs proved ts effectveness n voltge regulton, hrmonc elmnton, power fctor correcton, neutrl current compenston nd lod blncng. L Lb Lc c cb cc sn Vdc Ln V. CONCLUSON A control lgorthm bsed on SOG-PLL for DSTATCOM hs been mplemented for compenston of three-phse four-wre non-lner - Unblnced nd Vryng lods. The four-leg, eght swtches VSC s used s the DSTATCOM. The smulton results hve proved the fst nd effectve response for the extrcton of fundmentl component of lod currents for hrmonc compenston, lod blncng, neutrl current compenston nd power fctor / rectve power compenston wth lmt of EEE stndrd gudelnes. The proposed SOG controller s tkng less computtonl burden nd hs proved ts effectveness n mtgtng source-neutrl current nd the DC bus voltge s regulted compred wth the reference nd power fctor s lso mproved s expected. The dynmcs nd effcency confrms the potentl for mplementng n reltme pplctons. APPENDX AC supply source -Phse, 415 V (L-L Frequency 5Hz Source mpednce Rs.5 Ω, Ls mh Non-lner: Three phse R4 Ω, L 8mH full brdge uncontrolled rectfer Non-lner: Sngle phse R5 Ω full brdge uncontrolled rectfer Rtng of VSC 1 KVA Rpple flter Rf 5Ω, Cf 7μF Swtchng frequency 8kHz Reference dc bus voltge 7V nterfcng nductor Ls5mH Gns of P controller for kpt, kt. dc bus Cut off frequency of low 45Hz pss flter used n dc bus voltge Cut off frequency of low 16Hz pss flter used n c bus voltge Gns of P controller for kpt., kt. AC bus REFERENCES [1] F. F. Ewld nd A. S.M.Mohmmd, Power Qulty n Power Systems nd Electrcl Mchnes. London, U.K.: Elsever Acdemc Press, 8. [] G. Arndm nd L. Gerrd, Power Qulty Enhncement usng Custom Power Devces, Sprnger nterntonl Edton ed. Delh, nd: Sprnger, 9. [] C. Snkrn, Power Qulty. Boc Rton, FL: CRC, 1. [4] EEE Recommended Prctces nd requrement for Hrmonc Control on electrc power System, EEE Stndrd 519,

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