Realization of Unified Power Quality Conditioner for Mitigating All Voltage Collapse Issues

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1 Crcuts and Systems, 2016, 7, Publshed Onlne May 2016 n ScRes. Realzaton of nfed Power Qualty Condtoner for Mtgatng All Voltage Collapse Issues Parthasarathy Pugazhendran 1, Jeevarathnam Baskaran 2 1 Department of Electrcal and Electroncs Engneerng, IFET College of Engneerng, Vllupuram, Inda 2 Department of Electrcal and Electroncs Engneerng, Adhparasakth College of Engneerng, Melmaruvathur, Inda Emal: pugazh.ceg@gmal.com, bask11@gmal.com Receved 10 March 2016; accepted 8 May 2016; publshed 13 May 2016 Copyrght 2016 by authors and Scentfc Research Publshng Inc. Ths work s lcensed under the Creatve Commons Attrbuton Internatonal Lcense (CC BY). Abstract Ths paper proposes about a powerful control mechansm of PQC (nfed Power Qualty Condtoner) work on voltage source nverter whch can effectvely compensate source current harmoncs and also mtgate all voltage collapse such as dp, swell, voltage unbalances and harmoncs. The consoldaton of seres and parallel actve power flters sharng mutual DC bus capactor forms PQC. PI (Proportonal Integral) controller s manly used n order to mantan contnual DC voltage along wth the hysteress current controller. The parallel and seres power flters were desgned usng 3-phase voltage source nverter. The reference sgnals for shunt and seres actve power flters were obtaned by Synchronous Reference Frame (SRF) theory and Power Reactve (PQ) theory respectvely. By usng these theores, reference sgnals were obtaned whch was fed to the controllers for generatng swtchng pulses for parallel and seres actve flters. The PQC dynamc performance s obtaned through testng terms lke the compensaton of voltage, current harmoncs and all voltage dstorton assocated wth 3-phase 3-wre power system whch s smulated usng MATLAB-Smulnk software. Keywords Power Qualty Condtoner, Voltage Sag (Dp), Voltage Swell, Current Harmoncs Mtgaton, Power Qualty Improvement 1. Introducton Due to ncrease n use of power electroncs devces n ndustral area as well as n customer loads whch uses How to cte ths paper: Pugazhendran, P. and Baskaran, J. (2016) Realzaton of nfed Power Qualty Condtoner for Mtgatng All Voltage Collapse Issues. Crcuts and Systems, 7,

2 non-lnear loads, non-lnear loads at utlty cause large supply of reactve power whch pollutes the source sde equpment largely. The man requrement of mtgaton equpment s that they should be fast and dynamc response helps to reduce the source sde harmoncs. Due to ncreasng use of non-lnear loads, nowadays actve flters are replacng the olden days mtgaton methods lke swtchng capactor and thyrstor controlled nductor coupled wth passve flters [1]-[4]. There are types of actve power flters used: parallel actve flter elmnates current harmoncs and seres actve flter mtgates all types of voltage ssues. The nfed Power Qualty Condtoner (PQC) s a soluton to mtgate current and voltage ssues; t s the combned desgn of shunt and seres actve power flters coupled through mutual DC lnkage capactor whch rejects the nstabltes spread from the supply sde and the nterconnected supplementary loads. In general, the task of PQC, parallel actve flter estmates the rembursng current harmoncs called mtgatng current harmoncs and helps n VAR generaton usng the control crcutry [5]-[8]. The seres actve flters are able to mtgate all voltage ssues. The devce used to control the seres actve power flter analyzes the reference voltage to be noculated by matchng the voltage at termnal aganst the reference voltage. From the lterature revew of varous works done so far, descrbng the balanced or unbalanced source condtons by voltage ether dp or rse. In ths work, dfferent knd of voltage based PQ ssues such as sag, swell, transents, nterrupton and current harmoncs are smultaneously mtgated under balanced and unbalanced source condtons as well as lnear and non-lnear loadng condtons. Ths artcle proposes about three-phase three-wre system havng voltage source nverter usng streamlned control method. The seres actve flter s mantanng load voltage, dp/swell, harmoncs and flckers. The voltage on DC capactor s mantaned constant by parallel actve flters. PQC performances are smulated and verfed usng MATLAB tool. The Rght Shunt type nfed Power Qualty Condtoner (PQC) wth voltage source nverter s acted as a flter and ts modellng s delberated n Secton 2. The proposed control method based on hysteress controller for seres and parallel actve flter s explaned n Secton 3. A Smulnk model and ts detaled result and dscusson of the projected control scheme are descrbed n Secton4 for two dfferent source condtons. The concluson of the work s summarzed n Secton nfed Power Qualty Condtoner (PQC) Ths system proposes about the 3-phase source coupled to a power system feedng non-lnear load. Fgure 1 shows the PQC, and t has a dual voltage source nverters havng one shunt and other s seres actve power flter. The seres flter s connected between supply and DC common lnk through a sngle phase transformers on each phase havng turns ratos 1:1. These transformers act as a flter to elmnate the swtchng rpples actvely mtgate from seres flter. The voltage source nverters are constructed usng IGBT s (Insulated Gate Bpolar Transstors). Synchronous Reference frame theory for parallel (shunt) flter and nstantaneous reactve power theory were used as control algorthm for PQC. A seres flter composed of nductance along wth capactance s connected wth transformers whch mtgate rpple contents [6] [7] [9]-[11]. Fgure 1. PQC confguraton system. 780

3 2.1. Voltage Source Inverter From olden days, several nverters have been used due to dfferent applcatons. Voltage Source nverters have wde applcatons whch nclude drve control strategy, STATCOM, HVDC transmsson, and more mportant s that the nterfacng of renewable energy resources. In Power Qualty mprovement voltage source topology was wdely used n SVC s, PQC s, etc. due fast and dynamc response characterstcs [8] [11]. Moreover, n PQC, voltage source converters certan unbalance DC lnk voltage due fast short duraton operaton. The advantages of voltage source nverter are: -Produce pure snusodal current waveforms by reducng unwanted harmoncs. -Lessens the overvoltage produce by refecton on extended cable. -Rpple s two tmes normal the swtchng frequency n the frst set. Fgure 2 shows the Voltage source nverter (VSI) topology as an actve flter.ths topology permts swtches to tolerate hgher DC voltage nput on the stes that the swtches wll not elevate the level of wthstandng voltage [6] [10] Hysteress Controller Conventonal control topology for parallel actve flter controlled by the hysteress scheme n voltage source nverter s shown n Fgure 3 and ts modelng s defned as follows. Fgure 2. Voltage source nverter. Fgure 3. Voltage source nverter hysteress control. 781

4 Three phase voltage s gven as: Vas = V sn ( ωt) 2π Vbs = V sn ωt 3 2π Vcs = V sn ωt + 3 where V s the lne voltage measured across three phases a, b, c correspondngly. Hysteress Current Controller s helpng to dentfy the mtgated reference current. Then the nsde and outsde of hysteress comparator are stated as: hysteress ( ) dx 1, f dx > h = 0, f dx < h = x= abc (3) * ;,, dx dx dx Effectve swtchng pulses are used to generate three dfferent voltages on the AC sde of the actve flter. pper and lower voltages exstng n the negatve and postve phase voltages of the nverter acted as an actve flter. In optmstc sde voltage produced on two levels, 0 and l 2, and the destructve sde voltage level produced are, l 2 and 0. A Voltage l 2 s produced n order to ncrease the level of compensatng voltage, whereas the level of voltage on hgh sde 0 s to reduce compensated voltage. Thus, for every half cycle n swtchng hgh and low level voltage was selected alternately n order to select compensated current for each thyrstor [6] [12]-[14]. Ta 1 = sgn( Vas ) 1 hysteress ( da ) (4) where ( ) 1 sx ( ) ( ) Ta 2 = 1 sgn Vas hysteress da (5) ( ) ( ) 1 ( ) 1 ( ) Sa = sgn Vas hysteress da + sgn Vas hysteress da (6) ( ) ( ) Tb 1 = sgn Vbs 1 hysteress db (7) ( ) ( ) Tb 2 = 1 sgn Vbs hysteress db (8) ( ) ( ) 1 ( ) 1 ( ) Sb = sgn Vbs hysteress db + sgn Vbs hysteress db (9) ( ) ( ) Tc 1 = sgn Vcs 1 hysteress dc (10) ( ) ( ) Tc 2 = 1 sgn Vcs hysteress dc (11) ( ) ( ) 1 ( ) 1 ( ) Sc = sgn Vcs hysteress dc + sgn Vcs hysteress dc (12) sgn V =, f V > 0 ; or 0 f V < 0 and x = a, b, c Logc Control sx sx Logc control s used n controllng the both Actve Power Flters for provdng gate sgnals. The Dfference between the njected and reference current gves a reference modulaton waveform. The nverter control s determned by two strateges [12] [13]. Determnaton of ntermedate sgnals V m1 and V m2 : - If E c 1 at that tme V m1 = 1 - If E c 1 at that tme V m1 = 0 - If E c 1 at that tme V m2 = 0 - If E c 1 at that tme V m2 = 1 where V m1 and V m2 are mdway sgnal, E c s the modulaton reference error sgnal. (1) (2) 782

5 3. Control Approach The control approach for generaton of the reference sgnal s based upon error sgnal generaton and tme delay bass for effectve compensaton of PQC. The tme delay and reference current generaton manly to compensate dstortons, unbalance voltages and current durng any fault condtons. The proposed control approach s most sutable and effectve for mtgatng current and voltages durng undesrable condtons.the control strategy for parallel and seres actve flters are shown n Fgure 4 and Fgure 5 respectvely Parallel Actve Flter Control The man am of ths control approach s to compensate current harmoncs whch usually based upon the synchronous reference frame detecton method [3]. The control approach s based upon the load currents la, lb, lc, are converted nto 3 phase (a,b,c) reference frame and then to two phase (α β ) statonary reference frame currents α and β usng: [15]-[20] La α Lb = β Lc 2 2 (13) Fgure 4. Parallel actve flter control strategy. Fgure 5. Seres actve flter control strategy. 783

6 By means of phase locked loop (PLL), that make possble for generatons of cos ( θ ) and sn ( ) phase voltages such as, V as, V bs, and V cs. The α and β currents obtaned from (d-q) reference frame are wrtten as: ( θ ) cos ( θ ) ( θ ) sn ( θ ) d sn et et α = q cos et et β et θ from The d and q current are transformed nto DC components and usng a low pass flter harmonc components are obtaned: d d + d = q q The equaton for the reference current α -ref and β -ref as, The abc reference frame s gven as: ( θet ) cos ( θet ) ( θ ) sn ( θ ) 1 α ref sn d β ref = cos et et q ( θ ) cos ( θ ) ( θ ) sn ( θ ) α ref sn et et d + d β ref = cos et et q 1 0 a ref ref α b ref = β ref c ref Fnally, the compensaton currents are obtaned as; = = = acomp a ref La bcomp b ref Lb ccomp c ref Lc In order to mtgate, ntally the nverter losses are reduced and then normalze the DC lnk voltages usng a PI voltage controller [21]. The loop produces an equvalent current gven as: 3.2. Seres Actve Flter Control et (14) (15) (16) (17) (18) (19) Ic, los = kp DC + K DC dt (20) For generatng reference frame for seres actve flter dependng upon the PQ theory, we assume phase voltages are symmetrc and dstorted: [3] [15] [17] [19]. The Fgure 5 shows the seres actve flter control for generatng the flter reference voltage at the tme of dstorton occurred n the supply voltage. 2nsn ( nωt + θn) n= 1 A 2π B = 2nsn nωt + θn n= 1 3 C 2π 2nsn nωt + θ n n= 1 3 (21) 784

7 The n and θ n are rms voltages and prmary phase angle, n s the harmonc order. When n = 1, t means that the fundamental 3-phasesupply voltage; Equaton (10) s converted nto reference frame: The fundamental 3-phase current s framed as: 21sn ( ωt + θ1) A 2π B = 21sn ωt + θ1 3 C 2π 21sn ωt + θ 1 3 sn ( nωt + θ ) A n n α n 1 C 32 = B 3 = = β nsn C ( nωt + θn) n= 1 C = sn ( ωt) a 2 2π b = sn ωt 3 3 c 2π sn ωt + 3 Equaton (10) s transformed to (α β ) reference frame: a α sn ( t) C 32 ω b = = β cos ( ωt) c The DC components are obtaned by passng P and Q n low pass flter (LPF), then p cos ( θ ) ( θ ) q = 1sn 1 From the above equaton the transformaton s made as: The DC mechansms of p and q as: The fundamental reference frame s gven as: The three-phase fundamental voltages are gven as: p α β α α β α q = β α = β β α β p α f β f α α β α f q = = β f α f β β α β f 1 α f α β p = β f β α q (22) (23) (24) (25) (26) (27) (28) (29) (30) 785

8 1sn ( ωt + θ1) Af α f 2π Bf = C sn ωt θ1 = + β f 3 Cf 2π 1sn ωt + θ 1 3 C = (31) (32) 4. Smulaton Results and Dscusson 4.1. PQC Performance for Voltage Compensaton for Balanced Source Voltage Here both shunt and seres power flters are put nto operaton at dfferent tme nstants. Consderng nonlnear load for smulaton source parameters consdered are as follows. Input source voltages: V a = 230 V, V b = 230 V, V c = 230 V. The load element and flters wth VSC has been bult usng MATLAB /SIMLINK. The followng observatons are drawn from the smulaton outcomes. The control algorthm provdes reactve and harmonc power compensaton. Here balanced source voltage s consdered and after compensaton balanced source current s prescrbed n followng results. Fgure 6 shows the three phase balanced source voltages whch s beng suppled to the system. Fgure 7 depcts the three phase error voltage whch s generated due to the load connected to PQC. At tme nstant for t = 0 to 0.05 sec system s workng wthout any ssues, whch does not requre any compensaton and after t = 0.05 voltage dp s ntroduced, n ths tme perod seres flter comes nto operaton for compensatng voltage harmoncs. The voltage dp occurs tll 0.1 sec, the system s agan at normal workng condton. Then a short tme nterrupton s led whch occur from t = 0.14 to 0.15 sec, followng the nterrupton Fgure 6. Three phase balanced source voltage. Fgure 7. Three phase error voltage. 786

9 voltage swell s hosted from t = 0.15 to 0.18 sec at that tme shunt flter comes nto operaton for compensatng harmoncs due rse n voltage, then the system voltage come back to ts normal workng condton. In Fgure 8 voltage from t = 0 to 0.05 sec reman zero because of normal operaton at tme 0.05 sec voltage dp arse the reference voltage generator generates requred amount of voltage to compensate dp whch occur tll 0.1 sec. At t = 0.14 sec there s a small nterrupton for 0.01 sec so reference voltage generator generates the necessary voltage to mantan source voltage as normal. At t = 0.15 sec there s 10% rse (V s = 253 volt) n voltage tll 0.18 sec. So reference voltage generator generates the requred voltage n the opposte drecton for mtgaton. Three phase actual (generated) error voltage whch s beng added to the system error voltage to obtan the compensated source voltage of 230 volts for an entre operatng perod, t s shown n Fgure 9. In Fgure 8 and Fgure 9 there are few overshoots at t = 0.5 secs, t = 0.1 secs, t = 0.14 ecs, t = 0.18 secs respectvely. Ths overshoots are due to sudden njecton of reference components (voltage/current) whle mtgatng the pq ssues lke sag, swell and etc., n the respectve fault ponts. The duraton of ths overshoot exst for few mll or mcro seconds. These overshoots can be reduced by selectng sutable values of L and C of the actve flters and ts controllers n the proposed PQC. The supply current before compensaton s non-snusodal due to the non-lnear load connected to the system whch s shown n Fgure 10. Fgure 8. Three phase actual error voltage. Fgure 9. Compensated Source voltage after compensaton. Fgure 10. Source current before compensaton. 787

10 The generated reference current for compensaton usng hysteress controller s exactly follows the reference flter current shown n Fgure 11. It s generated by the synchronous reference current generator and s presented n Fgure 12. The generated reference current Fgure 12 s njected nto the source current at the load termnal (normally at the pont of common couplng). It results snusodal current whch s n phase wth the source voltage shown n Fgure 13. Hence the Total Harmonc Dstorton (THD) s mproved from 30.59% to 0.83%. There s a small dsturbance n tme t = 0.05, 0.1, 0.14 and 0.15 respectvely, whch s due the operaton of controller durng the mtgaton process of dp, nterrupton and swell. Fgure 11. Flter reference current. Fgure 12. Actual flter current. Fgure 13. Compensated source voltage n phase wth the source current after compensaton. 788

11 4.2. PQC Performance for Voltage Compensaton for nbalanced Source Voltage Consderng same smulaton load parameters, but havng unbalanced sources are as follows. Input source voltages: V a = 230 V, V b = 220 V, V c = 230 V. From t = 0.05 sec voltage dp s ntroduced, n ths tme perod seres flter comes nto operaton for compensatng voltage harmoncs. Then a short tme nterrupton s led whch occur from t = 0.14 to 0.15 sec, followng the nterrupton voltage swell s hosted from t = 0.15 to 0.18 sec at that tme shunt flter comes nto operaton for compensatng harmoncs due rse n voltage, then the system voltage come back to ts normal workng condton. Here unbalanced source voltage s consdered and after compensaton balanced source current s prescrbed n followng results. Fgure 14 shows the three phase unbalanced source voltages whch are suppled to the system. Fgure 15 and Fgure 16 are the error voltage and ts correspondng actual error voltage generated by usng proposed control strategy. Three phase actual (generated) error voltage shown n Fgure 16, whch s beng added to the system error voltage to obtan the compensated source voltage of 230 volts for an entre operatng perod, t s shown n Fgure 17. Fgure 18 shows the supply current before compensaton and whch s n non-snusodal due to non-lnear Fgure 14. nbalanced source voltages. Fgure 15. Three phase error voltages. Fgure 16. Three phase actual error voltages. 789

12 Fgure 17. Compensated three phase source voltages. Fgure 18. ncompensated source current. load connected to the system. The actual flter current generated by the synchronous reference current generator usng hysteress controller for the connected non-lnear load s shown n Fgure 20. It s exactly matched wth source reference current shown n Fgure 19. Fgure 20 shows compensated source voltage n phase wth the source current whch s obtaned by njecton of generatng reference current to source current at load termnal. There s a small rpple n the compensated current waveform shown n Fgure 21 s due to the njecton of reference current and voltages at varous ponts at the pont of common couplng. By desgnng a sutable flter component, the short duraton rpples are quenched quckly. The above tasks are analyzed by usng MATLAB Smulnk for two dfferent operatng condtons such a balanced and unbalanced source voltage condtons. The amount of harmonc dstorton reducton s up to the benchmark level and ts results are tabulated n Table 1. Table 1 shows the numercal statstcs of the THD values under before and after compensaton of the current n the proposed system. The THD mprovement n both operatng condtons s more satsfactory wth the standard of IEEE value. 5. Concluson For the mprovement of power qualty ssues n the source current due to harmoncs delvered by the nonlnear loads, a new PQC confguraton s constructed. The voltage source nverter topology s proposed to mtgate the ssues by actng as a flter. The control approach s based on the power nstantaneous method for seres flter and synchronous reference frame topology for parallel flter s proposed. PQC confguraton s proposed and valdated usng MATLAB/SIMLINK software. PQC confguraton s satsfactory observed for dfferent power qualty ssues such as current harmoncs mtgaton, voltage sag and voltage swell and unbalance compensaton. Anyhow, n the proposed work the performance of PQC has been agreed for varous power qualty mtgatons lke dp, swell and nterrupton under balanced and unbalanced condton of the consdered nonlnear load. The mprovement of THD n the source current s mproved from 30.59% to 0.83% for balanced source voltage and unbalanced source voltage THD value s mproved from 42.05% to 0.92%. Thus the prospectve 790

13 Fgure 19. Reference flter current. Fgure 20. Actual Reference current. Fgure 21. Compensated source current n phase wth source voltage. Table 1. Table of comparson of results before and after compensaton. S.No Total Harmonc Compensaton Before Compensaton After Compensaton 1 Balanced Source Voltage % 0.83% 2 nbalanced Source Voltage 42.05% 0.92% performance of the PQC control approach could be replaced by ntellgent control strategy and t s useful for potental usage of PQC under many crcumstances. 791

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