NTD4813N. Power MOSFET 30 V, 40 A, Single N -Channel, DPAK/IPAK

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NTD813N Power MOSFET 3 V,, Single N -Channel, DPK/IPK Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses

1 NTD813N Power MOSFET 3 V,, Single N -Channel, DPK/IPK Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb-Free Devices pplications CPU Power Delivery DC-DC Converters High Side Switching V (BR)DSS R DS(ON) MX I D MX 13 3 V 2 D MXIMUM RTINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain--to--Source Voltage V DSS 3 V Gate--to--Source Voltage V GS ±2 V Continuous Drain Current R θj (Note 1) T =25 C T =85 C I D Power Dissipation R θj (Note 1) Continuous Drain Current R θj (Note 2) Power Dissipation R θj (Note 2) Continuous Drain Current R θjc (Note 1) Power Dissipation R θjc (Note 1) Pulsed Drain Current Steady State T =25 C P D 1.9 W T =25 C ID 7.6 T =85 C 5.9 T =25 C P D 1.27 W T C =25 C I D T C =85 C 31 T C =25 C P D 35.3 W t p =ms T =25 C I DM 9 Current Limited by Package T =25 C I DmaxPkg 35 Operating Junction and Storage T J, to C Temperature T STG +175 Source Current (Body Diode) I S 29 Drain to Source dv/dt dv/dt 6 V/ns Single Pulse Drain--to--Source valanche Energy (V DD =2V,V GS =V, I L =12 pk,l=1.mh,r G =25Ω) Lead Temperature for Soldering Purposes (1/8 from case for s) ES 72 mj T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability Drain YWW 8 13NG G 2 1 Drain 3 Gate Source S N -CHNNEL MOSFET CSE 369 DPK (Bent Lead) STYLE 2 MRKING DIGRMS & PIN SSIGNMENTS Drain YWW 8 13NG Drain YWW 8 13NG Gate Drain Source Gate Drain Source Y = Year WW = Work Week 813N = Device Code G = Pb--Free Package CSE 369C 3IPK (Straight Lead) CSE 369D IPK (Straight Lead DPK) ORDERING INFORMTION Seedetailedorderingandshippinginformationinthepackage dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2 June, 2 - Rev. 6 1 Publication Order Number: NTD813N/D

2 NTD813N THERML RESISTNCE MXIMUM RTINGS Parameter Symbol Value Unit Junction--to--Case (Drain) R θjc.25 Junction--to--TB (Drain) R θjc--tb 3.5 Junction--to--mbient Steady State (Note 1) R θj 77.5 Junction--to--mbient Steady State (Note 2) R θj Surface--mounted on FR board using 1 sq--in pad, 1 oz Cu. 2. Surface--mounted on FR board using the minimum recommended pad size. C/W ELECTRICL CHRCTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHRCTERISTICS Drain--to--Source Breakdown Voltage V (BR)DSS V GS =V,I D = 25 m 3 V Drain--to--Source Breakdown Voltage Temperature Coefficient V (BR)DSS / T J 2.5 mv/ C Zero Gate Voltage Drain Current I DSS V GS =V, V DS =2V 1 T J = 125 C Gate--to--Source Leakage Current I GSS V DS =V,V GS = ±2 V ± n ON CHRCTERISTICS (Note 3) Gate Threshold Voltage V GS(TH) V GS =V DS,I D = 25 m V Negative Threshold Temperature Coefficient Drain--to--Source On Resistance R DS(on) V GS =Vto 11.5 V V GS(TH) /T J 5. I D = I D =15.3 V GS =.5V I D = I D = Forward Transconductance g FS V DS =15V,I D = 6. S CHRGES ND CPCITNCES Input Capacitance C ISS 86 Output Capacitance C OSS V GS =V,f=1.MHz,V DS =12V 21 pf Reverse Transfer Capacitance C RSS 115 Total Gate Charge Q G(TOT) Threshold Gate Charge Q G(TH) 1.2 Gate--to--Source Charge Q GS V GS =.5V,V DS =15V;I D =3 3.1 nc Gate--to--Drain Charge Q GD 3.6 Total Gate Charge Q G(TOT) V GS =11.5V,V DS =15V; I D = nc SWITCHING CHRCTERISTICS (Note ) m mv/ C mω Turn--On Delay Time t d(on).5 Rise Time t r V GS =.5V,V DS =15V,I D =15, 19.3 Turn--Off Delay Time t d(off) R G =3.Ω.1 Fall Time t f Pulse Test: pulse width 3 ms, duty cycle 2%.. Switching characteristics are independent of operating junction temperatures. ns 2

3 NTD813N ELECTRICL CHRCTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHRCTERISTICS (Note ) Turn--On Delay Time t d(on) 6. Rise Time t r V GS =11.5V,V DS =15V, 18.3 Turn--Off Delay Time t d(off) I D =15,R G =3.Ω 17.7 ns Fall Time t f 2.1 DRIN -SOURCE DIODE CHRCTERISTICS Forward Diode Voltage V SD VGS =V, I S =3 T J = 125 C.9 V Reverse Recovery Time t RR 16 Charge Time t a V GS = V, dis/dt = /ms, ns Discharge Time t b I S =3 5.6 Reverse Recovery Charge Q RR 7. nc PCKGE PRSITIC VLUES Source Inductance L S 2.9 nh Drain Inductance, DPK L D.16 Drain Inductance, IPK L D T =25 C 1.88 Gate Inductance L G 3.6 Gate Resistance R G 2.5 Ω 3. Pulse Test: pulse width 3 ms, duty cycle 2%.. Switching characteristics are independent of operating junction temperatures. 3

4 NTD813N TYPICL PERFORMNCE CURVES I D, DRIN CURRENT (MPS) R DS(on), DRIN--TO--SOURCE RESISTNCE (Ω) V 6V 5V V I D, DRIN CURRENT (MPS) 3V T J =--55 C V DS, DRIN--TO--SOURCE VOLTGE (VOLTS) V GS, GTE--TO--SOURCE VOLTGE (VOLTS) Figure 1. On -Region Characteristics Figure 2. Transfer Characteristics V 3.8 V 3.6 V I D = V GS, GTE--TO--SOURCE VOLTGE (VOLTS) Figure 3. On -Resistance vs. Gate -to -Source Voltage R DS(on), DRIN--TO--SOURCE RESISTNCE (Ω) V DS V T J = 125 C 15 2 V GS =.5V V GS =11.5V I D, DRIN CURRENT (MPS) Figure. On -Resistance vs. Drain Current and Gate Voltage 6 R DS(on), DRIN--TO--SOURCE RESISTNCE (NORMLIZED) I D =3 V GS =V I DSS, LEKGE (n),, V GS =V T J = 15 C T J = 125 C T J, JUNCTION TEMPERTURE ( C) V DS, DRIN--TO--SOURCE VOLTGE (VOLTS) Figure 5. On -Resistance Variation with Temperature Figure 6. Drain -to -Source Leakage Current vs. Drain Voltage

5 NTD813N TYPICL PERFORMNCE CURVES C, CPCITNCE (pf) 9 8 C iss C oss 2 C rss V DS, DRIN--TO--SOURCE VOLTGE (VOLTS) V GS, GTE--TO--SOURCE VOLTGE (VOLTS) Q T Q 1 Q 2 I D =3 V DD =15V V GS =11.5V Q G, TOTL GTE CHRGE (nc) Figure 7. Capacitance Variation Figure 8. Gate -To -Source and Drain -To -Source Voltage vs. Total Charge t, TIME (ns) 1 t r t d(off) t d(on) t f V DD =15V I D =3 V GS =11.5V 1 R G, GTE RESISTNCE (OHMS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance, SOURCE CURRENT (MPS) IS V GS =V V SD, SOURCE--TO--DRIN VOLTGE (VOLTS) Figure. Diode Forward Voltage vs. Current ID, DRIN CURRENT (MPS) V GS =2V SINGLE PULSE T C =25 C ms ms 1ms R DS(on) LIMIT THERML LIMIT ms PCKGE LIMIT 1 dc.1 1 V DS, DRIN--TO--SOURCE VOLTGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating rea ES, SINGLE PULSE DRIN--TO--SOURCE VLNCHE ENERGY (mj) I D = T J, JUNCTION TEMPERTURE ( C) Figure 12. Maximum valanche Energy vs. Starting Junction Temperature 5

6 NTD813N TYPICL PERFORMNCE CURVES ID, DRIN CURRENT (MPS) C C 25 C.1 1 PULSE WIDTH (ms) Figure 13. valanche Characteristics r(t), EFFECTIVE TRNSIENT THERML RESISTNCE (NORMLIZED) 1..1 D= E--5.1 SINGLE PULSE 1.E-- 1.E--3 P (pk) 1.E--2 t, TIME (ms) Figure 1. Thermal Response t 1 t2 DUTY CYCLE, D = t 1 /t 2 1.E--1 R θjc (t) = r(t) R θjc D CURVES PPLY FOR POWER PULSE TRIN SHOWN RED TIME T t 1 T J(pk) -- T C =P (pk) R θjc (t) 1.E+ 1.E+1 ORDERING INFORMTION NTD813NTG Device Package Shipping DPK (Pb--Free) 25 / Tape & Reel NTD813N--1G DPK--3 (Pb--Free) 75 Units / Rail NTD813N--35G IPK Trimmed Lead ( mm) (Pb--Free) 75 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. 6

7 NTD813N PCKGE DIMENSIONS DPK (SINGLE GUGE) CSE ISSUE B L3 L b2 e E b3 b D B DETIL c.5 (.13) M C C c2 H L2 GUGE PLNE L L1 DETIL ROTTED 9 CW 1 H C Z SETING PLNE NOTES: 1. DIMENSIONING ND TOLERNCING PER SME Y1.5M, CONTROLLING DIMENSION: INCHES. 3. THERML PD CONTOUR OPTIONL WITHIN DIMENSIONS b3, L3 and Z.. DIMENSIONS D ND E DO NOT INCLUDE MOLD FLSH, PROTRUSIONS, OR BURRS. MOLD FLSH, PROTRUSIONS, OR GTE BURRS SHLL NOT EXCEED.6 INCHES PER SIDE. 5. DIMENSIONS D ND E RE DETERMINED T THE OUTERMOST EXTREMES OF THE PLSTIC BODY. 6. DTUMS ND B RE DETERMINED T DTUM PLNE H. INCHES MILLIMETERS DIM MIN MX MIN MX b b b c c D E e.9 BSC 2.29 BSC H L L1.8 REF 2.7 REF L2.2 BSC.51 BSC L L Z SOLDERING FOOTPRINT* STYLE 2: PIN 1. GTE 2. DRIN 3. SOURCE. DRIN SCLE 3:1 mm inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 NTD813N PCKGE DIMENSIONS 3 IPK, STRIGHT LED CSE 369C--1 ISSUE O V B R C E NOTES: 1.. DIMENSIONING ND TOLERNCING PER NSI Y1.5M, CONTROLLING DIMENSION: INCH. 3. SETING PLNE IS ON TOP OF DMBR POSITION.. DIMENSION DOES NOT INCLUDE DMBR POSITION OR MOLD GTE. SETING PLNE W F G K J H D 3PL.13 (.5) W INCHES MILLIMETERS DIM MIN MX MIN MX B C D E F G.9 BSC 2.29 BSC H J K R V W IPK (STRIGHT LED DPK) CSE 369D--1 ISSUE B V B R C E NOTES: 1. DIMENSIONING ND TOLERNCING PER NSI Y1.5M, CONTROLLING DIMENSION: INCH. S - T - SETING PLNE F G K D 3PL J.13 (.5) M T H Z INCHES MILLIMETERS DIM MIN MX MIN MX B C D E F G.9 BSC 2.29 BSC H J K R S V Z STYLE 2: PIN 1. GTE 2. DRIN 3. SOURCE. DRIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTD813N/D

NTMKB4895NT3G. Power MOSFET 30 V, 82 A, Single N Channel, ICEPAK

NTMKB4895NT3G. Power MOSFET 30 V, 82 A, Single N Channel, ICEPAK Power MOSFET V,, Single N Channel, Features Low Package Inductance Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses