NTB90N02, NTP90N02. Power MOSFET 90 Amps, 24 Volts N Channel D 2 PAK and TO 220

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NTB9N, NTP9N Power MOSFET 9 mps, Volts NChannel D PK and TO Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.

1 NTB9N, NTP9N Power MOSFET 9 mps, Volts NChannel D PK and TO Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features PbFree Packages are vailable Typical pplications Power Supplies Converters Power Motor Controls Bridge Circuits V (BR)DSS V R DS(on) TYP 5. V 7.5 V NChannel D I D MX 9 MXIMUM RTINGS ( unless otherwise noted) G Rating Symbol Value Unit DraintoSource Voltage V DSS Vdc GatetoSource Voltage Continuous V GS Vdc Drain Current T = 5 C Single Pulse (t p = s) Total Power T = 5 C Derate above 5 C I D 9* I DM P D W W/ C Operating and Storage Temperature T J, T stg 55 to +5 C Single Pulse DraintoSource valanche Energy Starting (V DD = 8 Vdc, V GS = Vdc, L = 5. mh, I L(pk) = 7, RG = 5 ) Thermal Resistance JunctiontoCase Junctiontombient (Note ) Maximum Lead Temperature for Soldering Purposes, /8 from case for seconds E S 7 mj R JC.55 R J 7 C/W T L 6 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. When surface mounted to an FR board using pad size, (Cu rea.7 in ).. When surface mounted to an FR board using minimum recommended pad size, (Cu rea. in ). *Chip current capability limited by package. NTx9N x Y WW TOB CSE STYLE 5 Gate D PK CSE 8B STYLE Gate = Device Code = P or B = ssembly Location = Year = Work Week S MRKING DIGRMS Drain NTx9N YWW Drain Drain NTx9N YWW Drain Source Source ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 5 March, 5 Rev. Publication Order Number: NTB9N/D

2 NTB9N, NTP9N ELECTRICL CHRCTERISTICS ( unless otherwise noted) OFF CHRCTERISTICS Characteristic Symbol Min Typ Max Unit DraintoSource Breakdown Voltage (Note ) (V GS = Vdc, I D = 5 dc) Temperature Coefficient (Positive) V (BR)DSS 7 5 Vdc mv/ C Zero Gate Voltage Drain Current (V DS = Vdc, V GS = Vdc) (V DS = Vdc, V GS = Vdc, T J = 5 C) I DSS. dc GateBody Leakage Current (V GS = Vdc, V DS = Vdc) I GSS ± ndc ON CHRCTERISTICS (Note ) Gate Threshold Voltage (Note ) (V DS = V GS, I D = 5 dc) Threshold Temperature Coefficient (Negative) V GS(th) Vdc mv/ C Static DraintoSource OnResistance (Note ) (V GS = Vdc, I D = 9 dc) (V GS =.5 Vdc, I D = dc) (V GS = Vdc, I D = dc) (V GS =.5 Vdc, I D = dc) R DS(on) m Forward Transconductance (Note ) (V DS = 5 Vdc, I D = dc) g FS 5 mhos DYNMIC CHRCTERISTICS Input Capacitance (V DS = Vdc, V GS = Vdc, C iss pf Output Capacitance f =. MHz) C oss 9 Transfer Capacitance C rss 6 SWITCHING CHRCTERISTICS (Note ) TurnOn Delay Time (V DD = Vdc, I D = dc, t d(on) 6 ns Rise Time V GS =.5 Vdc, R G = 5 ).5 t r 9 TurnOff Delay Time t d(off) 8 Fall Time t f 6 Gate Charge (V DS = Vdc, I D = dc, V GS =.5 Vdc) (Note ) SOURCEDRIN DIODE CHRCTERISTICS Forward OnVoltage (I S =. dc, V GS = Vdc) (I S = dc, V GS = Vdc) (Note ) (I S =. dc, V GS = Vdc, T J = 5 C) Reverse Recovery Time (I S =. dc, V GS = Vdc, di S /dt = / s) (Note ) Q T 9 nc Q 8. Q V SD Vdc t rr ns t a t b 8 Reverse Recovery Stored Charge Q RR.6 C. Pulse Test: Pulse Width s, Duty Cycle %.. Switching characteristics are independent of operating junction temperatures.

3 NTB9N, NTP9N I D, DRIN CURRENT (MPS) V 8 V 6.5 V. V.6 V.8 V 5 V 5. V 6 V. V V.8 V.6 V. V. V V GS =. V V DS, DRINTOSOURCE VOLTGE (V) Figure. OnRegion Characteristics I D, DRIN CURRENT (MPS) 6 5 V DS V T J = 5 C T J = 55 C 5 6 V GS, GTETOSOURCE VOLTGE (V) Figure. Transfer Characteristics R DS(on), DRINTOSOURCE RESISTNCE ( ) V GS, GTETOSOURCE VOLTGE (V) I D = R DS(on), DRINTOSOURCE RESISTNCE ( ) V GS =.5 V V GS = V I D, DRIN CURRENT () 85 9 R DS(on), DRINTOSOURCE RESISTNCE (NORMLIZED) Figure. OnResistance versus GateToSource Voltage I D = 9 V DS =.5 V T J, JUNCTION TEMPERTURE ( C) I D = V DS = V Figure 5. OnResistance Variation with Temperature I DSS, LEKGE (n).. Figure. OnResistance versus Drain Current and Gate Voltage V GS = V T J = 5 C T J = C 8 6 V DS, DRINTOSOURCE VOLTGE (V) Figure 6. DrainToSource Leakage Current versus Voltage

4 NTB9N, NTP9N C, CPCITNCE (pf) 5 C iss C oss C rss V GS = V 8 6 V GS V DS GTETOSOURCE OR DRINTOSOURCE VOLTGE (V) Figure 7. Capacitance Variation V GS, GTETOSOURCE VOLTGE (V) 8 6 V D Q Q Q T V GS 8 I D =. 5 Q g, TOTL GTE CHRGE (nc) Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge 8 6 V DS, DRINTOSOURCE VOLTGE (V) t, TIME (ns) V DD = V I D = V GS = V t r t f t d(off) t d(on) R G, GTE RESISTNCE ( ) Figure 9. Resistive Switching Time Variation versus Gate Resistance I S, SOURCE CURRENT (MPS) V GS = V V SD, SOURCETODRIN VOLTGE (V) Figure. Diode Forward Voltage versus Current ORDERING INFORMTION Device Package Shipping NTP9N TOB 5 Units / Rail NTP9NG TOB (PbFree) 5 Units / Rail NTB9N D PK 5 Units / Rail NTB9NG D PK (PbFree) 5 Units / Rail NTB9NT D PK 8 Tape & Reel NTB9NTG D PK (PbFree) 8 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D.

5 NTB9N, NTP9N POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. ccordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(V) ) can be made from a rudimentary analysis of the drive circuit so that t Q IG(V) During the rise and fall time interval when switching a resistive load, V GS remains virtually constant at a level known as the plateau voltage, V SGP. Therefore, rise and fall times may be approximated by the following: tr Q R (VGG VGSP) tf Q R VGSP where: V GG = the gate drive voltage, which varies from zero to V GG R G = the gate drive resistance and Q and V GSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) RG Ciss In [VGG (VGG VGSP)] The capacitance (C iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off). t high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. nd finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. td(off) RG Ciss In (VGG VGSP) 5

6 NTB9N, NTP9N PCKGE DIMENSIONS D PK CSE 8 ISSUE O T SETING PLNE B G S D PL. (.5) M T B M K C E V W W J NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y.5M, 98.. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MX MIN MX B C D E F G. BSC.5 BSC J K M.8 7. S V VRIBLE CONFIGURTION ZONE U STYLE : PIN. GTE. DRIN. SOURCE. DRIN M M M F F F VIEW WW VIEW WW VIEW WW SOLDERING FOOTPRINT* SCLE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6

7 NTB9N, NTP9N PCKGE DIMENSIONS TO CSE 9 ISSUE H Q Z L V G B N D K F T U S R J C T SETING PLNE NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y.5M, 98.. CONTROLLING DIMENSION: INCH.. DIMENSION Z DEFINES ZONE WHERE LL BODY ND LED IRREGULRITIES RE LLOWED. INCHES MILLIMETERS DIM MIN MX MIN MX B C D F G H J K L N Q...5. R S T U V.5.5 Z.8. STYLE 5: PIN. GTE. DRIN. SOURCE. DRIN 7

8 NTB9N, NTP9N ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 6, Phoenix, rizona 858 US Phone: or 886 Toll Free US/Canada Fax: or 8867 Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguroku, Tokyo, Japan 55 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NTB9N/D

NTMKB4895NT3G. Power MOSFET 30 V, 82 A, Single N Channel, ICEPAK

NTMKB4895NT3G. Power MOSFET 30 V, 82 A, Single N Channel, ICEPAK Power MOSFET V,, Single N Channel, Features Low Package Inductance Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses