E SC 521 Pattern Generation at the Nanoscale Wook Jun Nam The Pennsylvania State University

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Oscar Thornton
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1 E SC 521 Pattern Generation at the Nanoscale Wook Jun Nam

2 Unit 1 Lithography General Information Lecture 2B Layout Design II

3 Outline Layout Design Define Function Design Partition Design Simulation

4 Typical Lithography Process Steps Define Function Design Partition Mask/Reticle/ Mold Fabrication Exposure/ irradiation Wafer Processing Design Simulation Layout design Process steps for making physical masks Process steps for pattern transfer

5 Layout Design Draw patterns Generate design file format (e.g., GDSII (graphic data system), OASIS (open artwork system interchange standard), CIF (caltech interchange format), DXF (drawing exchange format)). Create job file & exposure Fracture the gds file (separate patterns) & create files which a writing tool (e.g., ebeam, laser writer) can understand- (e.g., CATS, Layout Beamer)

6 Layout Editors Commercial Code: Cadence Virtuoso Mentor Graphics IC Station Tanner EDA L-edit Freeware: Magic Layout editor

7 Why L-Edit? Includes curved features which option is available only in expensive graphics. License is less expensive the Cadence/Mentor Graphics. Runs on PC (not UNIX). Better than freeware (although Layout Editor looks pretty good!)

8 Launch L-edit toolbars areal view layer palette Drawing window

9 Layers Separate design for photomask fabrication Separate beams for electron beam lithography Each layer has its own name and corresponding layer number.

10 L-Edit : drawing the two patterns for the solar cell Layer 43 (green) active area Layer 46 (red) - poly

11 Another way of drawing object (-300, 80) (40, 80) (-300, 0) (-130, 40) (40, 0)

12 Alignment Margin (critical dimension tolerance) 2um 20um 16um 50um 46um 2um 2um of alignment margin between the layer 43 (green) and layer 46 (red)

Microchips, Moore s Law, and Cost Over time transistors became easier to make This all lead to reduced cost Transistor production became more common, making the equipment and techniques for

13 Microchips, Moore s Law, and Cost Over time transistors became easier to make This all lead to reduced cost Transistor production became more common, making the equipment and techniques for nanotechnology readily obtainable The price of a transistor is estimated to be the same or less than a single printed character (letter) on a newspaper!!! Pentium 4 Core 2 Duo

14 Cell Hierarchy Complete cell layout. More complex cells.. Sub cells Sub cells Sub cells.. unit cells unit cells unit cells.

15 Cell Instance sub cell Unit cell

16 Cell Hierarchy unit cells Sub cells

17 Cell Hierarchy More complex cells

18 Cell Hierarchy Complete cell layout (Top cell)

19 Layout Design Draw patterns Generate design file format (e.g., GDSII (graphic data system), OASIS (open artwork system interchange standard), CIF (caltech interchange format), DXF (drawing exchange format)). Create job file & exposure Fracture the gds file (separate patterns) & create files which a writing tool (e.g., ebeam, laser writer) can understand- (e.g., CATS, Layout Beamer)

20 Summary Layout Design step is for deciding a. device function b. device architectures (e.g., dimension) c. materials d. process techniques e. process conditions (e.g., temperature, alignment margin) f. design partition (e.g., number of masks) Layout Design step needs numerical modeling for optical proximity correction Optical proximity correction enables the transferred pattern is closer to the original design

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional