7th Annual International Wafer-Level Packaging Conference & Tabletop Exhibition 2010

Transcription

1 7th Annual International Wafer-Level Packaging Conference & Tabletop Exhibition 2010 (IWLPC 2010) Santa Clara, California, USA October 2010 ISBN:

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3 IWLPC 2010 TABLE OF CONTENTS Session 1 Technology Solutions for a Dynamic and Diverse WLCSP Market Ravi Chilukuri, Amkor Technology Effect of UBMs and Solders on the Electromigration Performance of WLCSP L. Nguyen and H. Nguyen, National Semiconductor and D. Choi, J.K. Han, T. Tian, and K.N. Tu, UCLA Session 2 Design Methods for 3D IC Integration Peter Schneider, Sven Reitz, Jörn Stolle, Roland Martin, Andy Heinig and Andreas Wilde, Fraunhofer IIS, Design Automation Division Single Sided Wafer Thinning for 3D Integration Ricardo Fuentes, Ph.D., Materials and Technologies, Corp. MEMS TRACK Session 3 The Encapsulation of MEMS/Sensors and the Realization of Molded Vias on Package Level and Wafer Level with Film Assisted Molding Ton van Weelden and Lingen Wang, Boschman Technologies B.V. Session 4 Cost Comparison for Flip Chip, Wire Bond, and Wafer Level Packaging Chet A. Palesko and Amy J. Palesko, SavanSys Solutions, LLC; and E. Jan Vardaman, TechSearch International, Inc. High Volume Manufacturing Solution for Wafer Level Lens Molding and Stacking Kien Mun Lau, Michael Kast, Gerald Kreindl, Markus Wimplinger, Dominik Treiblmayr, Robert Breyer and Thorsten Matthias, EV Group

4 Session 5 Integration of Electrografted Layers for the Metallization of Deep TSVs C. Truzzi, S. Lerner, F. Raynal, V. Mevellec, N. Frederich, D. Suhr, I. Bispo and B. Couturier, Alchimer SA Demonstration of Ultra-Thin Si Grinding Process Controlled by In-Situ Non-Contact Gauge for 3D Stacked IC (3D-SIC) Ming Zhao, Greet Verbinnen, Anne Jourdain, Eric Beyne, Bart Swinnen and Leonardus Leunissen, IMEC VZW; Shinji Yoshida and Susumu Hayakwa, DISCO Corporation; and Tomotaka Tabuchi, DISCO HI-TECH EUROPE GmbH Flip Chip Die Bonding: An Enabling Technology for 3DIC Integration Keith A. Cooper and Michael D. Stead, SET-North America; and Gilbert Lecarpentier and Jean-Stephane Mottet, SET-SAS MEMS TRACK Session 6 Wafer Bonding Process Selection E. Pabo, T. Tang, V. Dragoi and T. Matthias, EV Group, Inc. Miniaturized WLP for MEMS Risto Mutikainen, Ph.D., Sami Nurmi, Ph.D., Tapani Alander, Ph.D., Esko Sirén, Lic. Tech. and Heikki Kuisma, M.Sc., VTI Technologies Session 7 Microsprings for Integrated Test and Packaging Eugene M. Chow, Ph.D., Palo Alto Research Center (PARC) Scalable Interconnect Technology that Enables High Density, High Performance and Low Profile Connectivity for Board to Board, Package to Board and Board to Flex Applications Amit Varma, Ming Wu and Charlie Stevenson, High Connection Density, Inc. Wafer Bumping-The Low Cost Solution to Production Wafer Packaging John Mackay, Spheretek Session 8 Wafer Level Processing and Integration Techniques for CMOS Image Sensor Module Manufacturing Bioh Kim, Thorsten Matthias, Gerald Kreindl, Viorel Dragoi, Markus Wimplinger and Paul Linder, EV Group, Inc. 3D Wafer Level Packaging of Micro Camera Devices Martin Wilke, Kai Zoschke, Julia Röder, Veronika Glaw, Michael Töpper, Ingrid Kuna, Karin Samulewicz, Oswin Ehrmann, Klaus-Dieter Lang and Herbert Reichl, Fraunhofer IZM

5 MEMS TRACK Session 9 Wafer Level Packaging: A Foundry Perspective Michael Shillinger, Innovative Micro Technology The MEMS Approach for Making a Low Cost, High Sensitivity Magnetic Sensor Alan S. Edelstein and Greg A. Fischer, U.S. Army Research Laboratory; James E. Burnette and William F. Egelhoff, Jr., National Institute of Standards and Technology Cost Effective Wafer Level Encapsulation for MEMS and other Circuit Elements Jay Mitchell and Sangwoo Lee, epack, Inc.; Warren Welch, Intek Inc.; and Khalil Najafi, Center for Wireless Integrated Microsystems (WIMS), University of Michigan Session 10 Polymer Core Solder Balls as Interconnects to Enhance L. Nguyen, H. Nguyen, A. Prabhu and A. Poddar, National Semiconductor Corp. Cu Pillar Electroplating Process Control for Wafer Level Packaging Jim Zhang, Richard Hollman, Zhenqui Liu and Arthur Keigler, NEXX Systems, Inc. Session 11 Depth Measurement of Through Silicon Via by Using IR Confocal Microscope Deh-Ming Shyu, Wei-Te Hsu and Yi-Sha Ku, Industrial Technology Research Institute Mechanical Behavior Measurement of Si Water Po-Yi Chang and Yi-Sha Ku, Industrial Technology Research Institute Exploration of Migration and Stress Effects in PoPs Considering Inhomogeneous Temperature Distribution L. Meinshausen and K. Weide-Zaage, Information Technology Laboratory, Leibniz University Hannover Session 12 Development of Next Generation ewlb (Embedded Wafer Level BGA) Packaging Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu and Rajendra Pendse, STATS ChipPAC; and Ganesh V.P., Andreas Bahr and Thorsten Meyer, Infineon Technologies AG; and Yonggang Jin and Xavier Baraton, ST Microelectronics Wafer Level Embedded System in Package (WL-ESiP) for 3D SiP Solution In-Soo Kang, Gi-Jo Jung, Byoung-Yool Jeon, Jae-Hyouk Yoo and Byeung-Gee Kim, Nepes Corporation ewlb System in Package Possibilities and Requirements Thorsten Meyer, Gerald Ofner, Christian Geissler and Klaus Pressel, Infineon Technologies

6 Session 13 Near Infrared (NIR) Prototype Optics Experiments on an Existing Macro-Defect Inspection Platform Rolf Shervey, Rudolph Technologies, Inc.; and Andy Rudack, SEMATECH Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams (FIB) Richard J. Young, Chad Rue and Michael Schmidt, FEI Company; and Ruud Schampers and David Wall, FEI Company Enabling Comprehensive and Efficient Test of 3D Chips by Standardizing the Test Access Architecture Al Crouch, ASSET InterTech, Inc. Session 14 Electrical, Thermal and Mechanical Characterization of ewlb (Embedded Wafer Level BGA) Seung Wook Yoon, Meenakshi Prashant, Gaurav Sharma, Roger Emigh, Kai Liu, Sin Jae Lee, Ray Coronado, Yeong J. Lee and Rajendra Pendse, STATS ChipPAC Low Cost, High Density Chip-Layer Vias for Chips-First Stacked Packages James E. Kohl, Ph.D., Charles W. Eichelberger, S. Keith Phillips and Nancy G. Perkins, EPIC Technologies, Inc. Embedded Active Device Packaging Technology for Real DDR2 Memory Chips Yin-Po Hung, Tao-Chih Chang, Ching-Kuan Lee, Yuan-Chang Lee, Jing-Yao Chang, Chao-Kai Hsu, Shu-Man Li, Jui-Hsiung Huang, Fang-Jun Leu, Yu-Wei Huang, Ren-Shin Cheng and Tai-Hong Chen, Electronics and Optoelectronics Research Laboratories (EOL), Industrial Technology Research Institute (ITRI) Laminate Based Fan-Out Embedded Die Technologies: The Other Option Theodore Tessier, Mark Dhaenens and David Clark, FlipChip International LLC; and Tanja Karila and Tuomas Waris, Imbera Electronics, Inc. Session 15 3D Substrate Innovation for Very Fine Pitch Flip-Chip Applications Vern Solberg, STC-Madison; and Vage Oganesian, Tessera Development of and Eight-Die Nand LSOP Package Ke Xiao, Jungfeng Zhao, Lefei Zhang, Mao Guo, Yong She and Yinglong Song, Intel Corporation; and Eagle Lin, Dennis Chang and MJ Chen, Powertech Technology, Inc. (PTI) Fine Pitch 3D Dispensable Electrical Interconnects for System in Package Solutions Jeff S. Leal, Suzette K. Pangrle, Charles Whyte, Keith Barrie, Jeff Leff, Scott McGrath and Gerardo Ayala, Vertical Circuits, Inc. Reliability Analysis of 3D Dispensable Interconnects for a System in a Package Solution Suzette K. Pangrle, Jeff S. Leal, Scott McGrath, Grant Villavicencio, Keith Barrie, DeAnn Melcher, Sartaj Ajrawat, John Bray, Elizabeth Hankes, Jeff Leff, Elmer DelRosario, Marc Robinson and Sunil Kaul, Vertical Circuits, Inc.; and Ken Holcomb and Catherine Shearer, Ormet Circuits, Inc.; and Mark Kowalski and Anna Hall, Cabot Corporation

7 POSTER PRESENTATION Non-Destructive Characterization of Critical Failures in 3D Integrations Using Computed Tomography Gyujei Lee, Kang-won Lee, Hyun-joo Kim, Suk-woo Jeon and Kwang-yoo Byun, Hynix Semiconductor Inc.; and Hae-bong Park, SEC Co. Ltd.