SJEP120R125. Silicon Carbide. Normally-OFF Trench Silicon Carbide Power JFET. Product Summary

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1 NormallyOFF Trench Power JFET Features: Compatible with Standard PWM ICs Positive Temperature Coefficient for Ease of Paralleling Temperature Independent Switching Behavior 175 C Maximum Operating Temperature R DS(on)max of.125 Ω Voltage Controlled 4 Low Gate Charge Low Intrinsic Capacitance Product Summary BV DS 12 V R DS(ON)max.125 Ω Q g,typ 25 nc D(2,4) G(1) Applications: TO247 Solar Inverter SMPS S(3) Power Factor Correction Internal Schematic Induction Heating UPS Motor Drive MAXIMUM RATINGS, at T j = 25 C unless otherwise stated Parameter Symbol Conditions Value Unit Continuous Drain Current Pulsed Drain Current I D25 I D1 T C = 1 C I DM T C = 25 C Avalanche Energy, single pulse E AS I D = 6 A, V DD = 5V, TBD Avalanche Energy, repetitive E AR Tj < 175 C 2 Avalanche Current, repetitive 6 I AR t SC T C = 25 C Short Circuit Withstand Time V DD < 12 V, T j < 175 C Power Dissipation P D T C = 25 C DC GateSource Voltage V GS 15 to +3 AC GateSource Voltage V GS t P < 1ns to +15 A A mj A us W V V Operating and Storage Temperature T j, T j,stg 55 to +175 C October 28 Rev 1.6 1/18

2 THERMAL CHARACTERISTICS Parameter Thermal Resistance, junctioncase Thermal Resistance, junctionambient Symbol R th,jc R th,ja Conditions Min Value Typ Max Unit C / W STATIC CHARACTERISTICS, at T j = 25 C unless otherwise stated DrainSource Leakage Current Gate Threshold Voltage GateSource Leakage Current Gate Resistance Parameter DrainSource Blocking Voltage DrainSource Onresistance Symbol BV DS I DSS V GS(th) I GSS R DS(on) R G Conditions V GS = V, I D = 1 µa V DS = 12 V, V GS = V V DS = 12 V, V GS = 5 V V DS = 1 V, I D = 34 ma V GS = 3 V V GS = 15 V I D = 12 A, V GS = 3. V, T j = 25 C I D = 12 A, V GS = 3. V, T j = 15 C f = 1 MHz, opendrain Min Value Typ Max TBD Unit V ua 1.25 V ma Ω Ω DYNAMIC CHARACTERISTICS, at T j = 25 C unless otherwise stated Total Gate Charge GateSource Charge GateDrain Charge Turnon Delay (Resistive Load) Rise Time (Resistive Load) Turnoff Delay (Resistive Load) Fall Time (Resistive Load) Turnon Energy Turnoff Energy Total Switching Energy Input Capacitance Output Capacitance Parameter Symbol Conditions Reverse Transfer Capacitance Effective Output Capacitance, energy related Q g Q gs Q gd t on t r t off t f E on E off E ts C iss C oss C rss C o(er) V DS = 6 V, I D = 12 A, V GS = V to + 3 V V DS = 6 V, I D = 12 A, C BP = 33 nf, R CL = 22 Ω, Figure 9 V DS = V to 48 V, V GS = V Min V DS = 1 V Value Typ Max TBD TBD TBD Unit nc ns mj pf October 28 Rev 1.6 2/18

3 PRELIMINARY V I D, DrainSource Current (A) V 2. V I D, DrainSource Current (A) V 2. V 1V DS, DrainSource 2 3 Voltage 4 (V) 5 6 Figure 1. Typical Output Characteristics I D = f(v DS ); T j = 25 C; parameter: V GS 1V DS, DrainSource 2 3 Voltage 4 (V) 5 6 Figure 2. Typical Output Characteristics I D = f(v DS ); T j = 1 C; parameter: V GS 15 3V 3.5 I D, DrainSource Current (A) V 2. V 3. R DS(on), DrainSource Onresistance (Normalized) V DS, DrainSource 2 3 Voltage 4 (V) 5 6 Figure 3. Typical Output Characteristics I D = f(v DS ); T j = 175 C; parameter: V GS. 25 Tj, Junction 75 Temperature 125 ( C) 175 Figure 4. DrainSource Onresistance R DS(on) = f(t j ); V GS = 3. V, I D =.5 * I D25 October 28 Rev 1.6 3/18

4 14 35 P TOT, Total Power Dissipation (W) I D, DrainSource Current (A) T C, Case Temperature 1 15( C) 2 Figure 5. Power Dissipation P tot = f(t c ).5V GS, GateSource Voltage 2 (V) Figure 6. Typical Transfer Characteristics I D = f(v GS ); V DS = 5 V I GS, GateSource Current (A) 1.E1 1.E2 1.E3 1.E4 1.E5 2. V GS 2.25, GateSource 2.5 Voltage 2.75(V) 3. Figure 7. GateSource Current I GS = f(v GS ) R DS(on), DrainSource Onresistance (Ω) E4 I GS, GateSource 1.E3 Current 1.E2 (A) 1.E1 Figure 8. DrainSource Onresistance R DS(ON) = f(i GS ); I DS = 12 A October 28 Rev 1.6 4/18

5 R DS(on), DrainSource Onresistance (Ω) C, Capacitance (pf) C iss.8 2. V GS 2.25, GateSource 2.5 Voltage 2.75 (V) 3. Figure 9. DrainSource Onresistance R DS(ON) = f(v GS ); I DS = 12 A V2 DS, DrainSource 4 6 Voltage (V) 8 1 Figure 1. Typical Capacitance C = f(v DS ); V GS = V; f = 1 MHz R L C BP 22 uf V DD 15 V V R CL Figure 11. Resistive Load Switching Circuit October 28 Rev 1.6 5/18

6 1.E+1 Z th(jc), Transient Thermal Impedance ( C/W) 1.E+ 1.E1 1.E E3.2 1.E6 1.E5 1.E4 t P, Pulse Width (s) 1.E3 1.E2 1.E1 Figure 12. Transient Thermal Impedance Z th(jc) = f(t P ); parameter: Duty Ratio October 28 Rev 1.6 6/18

7 A. Device Overview The is an enhancementmode (EM) silicon carbide (SiC) Vertical Junction Field Effect Transistor (JFET) optimized for use in highvoltage, highpower, highfrequency power management applications. Due to the superior material properties of the SiC semiconductor and patented trench architecture, the delivers bestinclass performance in both hardswitching and softswitching applications. The is designed to be a replacement for MOSFETs and IGBTs and delivers the following performance advantages: the device and very high current densities are achieved. The does not have a pn junction between drainsource and therefore has no intrinsic body diode. The control methodology is similar to that of a BJT, but the switching performance is characteristic of a unipolar device because device there is no conductivity modulation in the channel. No saturation voltage: Due to unipolar conduction in the JFET structure (i.e. no conductivity modulation) there is not a saturation voltage to overcome before output current is available enabling lower conduction losses and higher systems efficiencies. No tailcurrent: No tail current is present at the turnoff transition enabling lower switching losses and higher practical switching frequencies. Low onresistance: Lowest specificonresistance of all 12Vclass semiconductor devices due to the SiC material enables reduced conduction losses and higher system efficiencies. Low Intrinsic Capacitance: Lower device capacitances allow for reduced gate charge requirements and highfrequency switching applications. Positive Temperature Coefficient: Allows multiple die to be paralleled easily and without concerns for unbalanced current sharing or thermal runaway. No Body Diode: There is not an intrinsic body diode in the JFET structure. A SiC SBD can be copacked as required by the application to enable the lowest possible switching losses. Figure 13. Equivalent Circuit of C. Gate Driver 1. Lowside Switching Applications: The is designed to be a direct replacement for MOSFETs and IGBTs in groundreferenced, lowside switching applications with only minor modifications to the gate drive circuitry. Figure 14 shows the recommended configuration using a V/+15V PWM/driver signal, which includes the addition of a resistor (R CL ) in parallel with a capacitor (C BP ) between the driver/pwm IC output and the gate resistor (R g ). These components serve four primary functions: B. Device Structure Figure 13 illustrates the simplified schematic representation of the. Much like a BJT, gatesource and gatedrain junctions are pn diodes. Like all threeterminal semiconductor devices, the gatesource, gatedrain, and drainsource junctions act as nonlinear, voltagedependent capacitances in the circuit. The is a based on a verticalchannel, trench structure, thus no current flows laterally in a. Fast delivery and removal of gate charge to the, thus improving the turnon and turnoff times. b. Levelshifting of the +15V output from the PWM/driver IC to V as selected by the user. c. Reflection of a negative voltage on the gatesource junction at the turnoff transition to improve the turnoff time and improve EMI immunity of the gatesource signal. d. Limit the continuous current sourced from the PWM/driver IC during the onstate. October 28 Rev 1.6 7/18

8 Figure 15 is a waveform showing the PWM/driver IC output and gatesource voltage obtained using this configuration. The selections of R CL and C BP are discussed in section C.3. Figure 14. Recommended Driver/IC Interface Figure 16. Recommended Driver/IC Interface for highside switching applications. Figure 15. Switching waveforms for /+15V PWM/driver IC level shifted to +3V. V DS (top, 2V/div), V GS (middle, 1V/div), and V O (bottom, 1V/div) 2. Highside Switching Applications In addition to the use of RCL and CBP as described in section C.1., the use of a negative voltage rail for the PWM/driver IC is recommended when the is used in a highside switching application. This configuration improves the EMI immunity of the gatesource voltage and prevents dv/dt induced turnon that could result from operation in a halfbridge or fullbridge configuration. Figure 16 shows the recommended configuration using a 12V/+5V PWM/driver output. Figure 17 is a waveform showing the PWM/driver IC output and gatesource voltage obtained using this configuration. The selections of R CL and C BP are discussed in section C.3. Figure 17. Switching waveforms for 12V/+5V PWM/driver IC level shifted to +3V. V DS (top, 2V/div), V GS (middle, 1V/div), and V O (bottom, 1V/div) 3. R CL and C BP Selection The appropriate C BP value is selected based on Q g of the and is independent PWM/driver IC supply rail voltages. Parasitic circuit effects can influence the selection of C BP, so one particular value is C BP is not necessarily appropriate for all applications. Rather a range of C BP values to be evaluated empirically is suggested to the user as defined by Equation 1: V 2 * Q cc g V gs C BP 4 * Q g V V cc gs, (1) October 28 Rev 1.6 8/18

9 where V cc is the PWM/driver IC output voltage and V gs is the desired gatesource voltage of the. R CL is used to limit the continuous current flowing from the PWM/driver IC through the gatesource diode (Figure 7) of the, thus setting the gatesource voltage. The maximum recommended gatesource current is 5mA. It is recommended that the maximum steadystate (DC) gate voltage be not exceed +3. V; however a gatesource voltage pulse to +15V may be applied during the turnon transition. The selection of R CL requires the following information: a. V O = Positive output voltage of the PWM/driver IC b. V gs = Desired gatesource voltage c. I gs = Gatesource diode current at the desired gatesource voltage. IGS can be estimated from Figure 7. Figure 19. Switching Waveforms. V DS (top, 15V/div), I D (middle, 3A/div), and V GS (bottom, 2V/div) The recommended value of R CL is defined by Equation 2: R V V O gs CL = (2) I gs (@Vgs) D. Resistive Load Switching Waveforms A simplified schematic of the resistive load switching circuit is show in Figure 18. The resulting switching waveforms are shown in Figures Figure 2. Rise time measurement. V DS (top, 15V/div), I D (middle, 3A/div), and V GS (bottom, 2V/div) Figure 18. Resistive Load Switching Circuit Figure 21. Fall time measurement. V DS (middle, 15V/div), I D (top, 3A/div), and V GS (bottom, 2V/div) October 28 Rev 1.6 9/18

10 Published by SemiSouth Laboratories, Inc. 21 Research Boulevard Starkville, MS USA SemiSouth Laboratories, Inc. 28 Information in this document supersedes and replaces all information previously supplied. Information in this document is provided solely in connection with SemiSouth products. SemiSouth Laboratories, Inc. reserves the right to make changes, corrections, modifications or improvements, to this document without notice. No license, express or implied to any intellectual property rights is granted under this document. Unless expressly approved in writing by an authorized representative of SemiSouth, SemiSouth products are not designed, authorized or warranted for use in military, aircraft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. October 28 Rev 1.6 1/18