Comparison of Adaptive Voltage/Frequency Scaling and Asynchronous Processor Architectures for Neural Spike Sorting

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1 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY Comparison of Adaptive Voltage/Frequency Scaling and Asynchronous Processor Architectures for Neural Spike Sorting Jackie Leverett, Rachel Hochman, Amanda Pratt Berkeley Wireless Research Center, University of California, Berkeley, CA {jleverett, rhochman, apratt}@eecs.berkeley.edu Abstract This paper investigates the tradeoffs between adaptive and asynchronous timing methods for spike sorting in neural signal processing. Using an asynchronous timing scheme has been proven to reduce the power consumed by a neural processor [1], yet no relevant comparison has been made with an adaptive timing scheme. Our work provides an evaluation of the power consumption of two spike-sorting circuits that perform the same processing, but differ in timing structure, simulated in 32nm predictive technology. Starting with Verilog descriptions of each module, we produced SPICE netlists from complete layouts and compared the energy/performance of each by simulating the modules under a wide range of supply and frequency conditions. Our findings indicate that adaptive synchronous timing results in lower energy than asynchronous timing for data rates below 1.5MHz. Index Terms action potential sorting, asynchronous processing, adaptive voltage and frequency scaling I. INTRODUCTION Technological advancements in low power circuit design have paved the way for emerging wireless, battery-operated brain machine interfaces (BMIs). However, power limitations are extremely stringent in such devices because excess heat can damage sensitive brain tissue and battery life must be long to avoid complex replacement surgeries. These BMIs often will have on-chip circuitry that detects neural action potentials (spikes) and subsequently aligns and sorts the spikes according to shape. Because action potential events are sparse in the time domain, fully synchronous, single clock architectures consume more power than desired. Thus, several techniques have been implemented which leverage the sparsity of these events, including an asynchronous neural processor [1] and a gated synchronous processor that uses an analog detection algorithm to turn on or off the ADC and processing elements [2]. II. BACKGROUND Several approaches for reducing power in BMIs have been proposed. An asynchronous neural signal processor has been constructed that demonstrates robust behavior in the subthreshold region down to 0.25V and consumes only 460nW in 0.03mm2 [1]. The processor receives data from an ADC front-end running at 20kHz and then converts the data with a synchronous-to-asynchronous interface composed of differential pre-charged dynamic logic buffers. The data processing thereafter is driven only by local handshaking events, which eliminates timing uncertainties such as skew and jitter due to clock distribution. Each block achieves a high performance that adapts to the changing operating conditions. The metrics achieved represent a 4.4X reduction in power compared to previous state-of-the-art. Another power saving architecture was reported in [2]. In this approach, the ADC and processor are not activated until an analog FIFO determines that a spike is occurring as the input voltage passes a predetermined threshold. This does save power, but when the processor is turned on, it is operating at a fixed frequency, which may be inefficient if the spike does not need to be processed quickly. Both previous approaches process the spike data in a defined period of time, consuming a set amount of power during a single spike s processing. In reality, the time between action potentials can vary significantly and in some cases, can be quite large. When the delay between spikes is large, the spike sorting could be spread over a larger amount of time than when the interspike delay is small. An illustration of this may be seen in Figure II. To spread the processing time, the voltage can be lowered and subsequently frequency reduced, resulting in reduced power. The concept of voltage scaling has been well established in [3]. In this project, we investigate the performance of neural spike processing logic with adaptive voltage and frequency scaling to leverage the sparse nature of the action potential trains. While adaptive synchronous methods have been used in other aspects of neural processing, including adaptive thresholding for detection [4], thus far to our knowledge, adaptive voltage and frequency scaling has not been utilized in spike sorting algorithms. Our analysis endeavors to determine the conditions under which asynchronous spike sorting sequential logic is most beneficial and those under which adaptive voltage and frequency scaling of the spike sorting sequential logic more benefitial. III. ARCHITECTURE A basic spike-sorting algorithm first finds the value and location of the maximum data point within each spike and then superimposes the spikes with their maxima aligned. For the scope of this project, we chose to implement just the maxfinding function. However, in order to design the max-finding function and makig a fair comparison between methodologies, one must have an understanding of the supporting architecture.

2 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY Fig. 1. A conceptual power and timing comparison between our adaptive voltage/frequency scaling methodology and an existing asynchronous approach. In this research, a neural processor architecture similar to that in [5] is assumed. A diagram of the architecture may be seen in Figure III. A spike detector is used to determine the presence of an incident spike and start sending the ADC data for that spike to the FIFO. the clock and data in order to ensure that the chip runs under all operating conditions and in all process corners (a factor in the lack of frequency scaling in recent years). This is especially true of designs operating in the subthreshold region. To minimize this guardband and to ensure the adaptive synchronous architecture is competitive with an asynchronous architecture, logic detecting the actual frequency of operation of a chip would be necessary to minimize clocking errors. Critical Path Monitoring (CPM), as implemented in [6], can determine the requisite clock frequency with a lower overhead and implementation effort than other techniques [6]. Fig. 2. Assumed processor architecture. Whereas the asynchronous circuitry will simply process the data at its intrinsic operating speed for a given supply voltage, the adaptive synchronous version requires two kinds of control logic to choose the right voltage/frequency pairs. A feed forward adaptive path tracks the input rate of the FIFO, and a critical path monitor tracks variations in process, voltage, and temperature (PVT). If the FIFO has a low input frequency, then the supply voltage is significantly lowered, and the clock frequency is reduced to account for subthreshold delays. However, if one or more additional spikes enter the FIFO in close succession, the voltage and frequency are scaled up and adapted every cycle, as seen in Figure II. In this way, we lower power when spikes are sparse and increase power to avoid buffer overflows when necessary. Additional power supply voltages will need to be added in order to support the adaptive voltage and frequency scaling at different incident spike frequencies. In a purely synchronous design, to compensate for the PVT dependence, a large guardband must be used between A. Clocked Spike Processing Logic A clocked version of this logic is shown in Figure 3. Eight bit data are input, along with their FIFO positions (6 bits) and the current spike count (2 bits). The outputs of this logic block are the spike count, a data ready flag, and the maximum data value along with its fifo position. The key to the spike function logic is the comparison of the current datum to the maximal previous datum in the spike, which is implemented using an 8-bit comparator. Data is latched if it exceeds the value of the previous maximal value in the spike. This clocked version of the logic was used to characterize the performance of the adaptive synchronous unit. B. Asynchronous Units and Handshaking The asynchronous version of the maximum value finding function used a similar methodology to the clocked function. It takes in an eight-bit datum, FIFO position, and spike count and outputs dataready, maximum datum from the spike, and the position of that maximum datum in the FIFO. In reality, it would also need to send a ready signal to the FIFO to request new data. However, this functionality was not implemented for the simulation, as data input rate was swept to find the intrinsic operating frequency of the asynchronous circuit. In an effort to compare similar technologies, and to continue to use the synthesis tools for place and route, the asynchronous

3 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY Fig. 3. Synchronous Spike Sorting Maximum Function module needed to use the same logic and standard cells as the synchronous module. Prior work in [5], used several different techniques to acheiver asynchronous logic. One of these methods is a glitch-free handshaking logic. There are several elements of this logic which make it effecient and effective, including an enabled sense amplifier, a C-element, and most notably, pass gate logic. In [5], pass gate logic is an inherently lower power solution that CMOS gates, and is a wise choice for low-power circuits. In addition, it provides an additional benefit in that this implementation can easily reset all internal nodes to ground if the driving signal is grounded. This reset functionality is benefitial to detecting the resolution of data values. The passgate logic implemented differential logic, which must resovle to non-identical values upon completion. Thus, if one resets the values of the driver between each piece of incoming data, as is done in [5], one is able to provide a signal to the next cell block that data is ready and request that the previous cell send new data. However, being restricted to the same standard cell library as the synchronous module, it was necessary to take a more traditional CMOS approach. Therefore, a complementary data path was manually implemented. Again, the comparison of the current datum to the maximal previous datum in the spike is the key logical element in this process. Once the comparason function is complete, new data present on the data line would not corrupt the analysis of the current data. Thus, the complementary data path indicates when the data had completed the comparison function. A representation of the implemented logic may be found in Figure 4. The path which indicates the new data is greater than the previous data and the path which resolves true when the new data is less than or equal to the current data both need to be initialized to a known value. In this case, both comparator paths resolve to a true value. Because these paths were initialized to the same value, the resolution of the data could be detected easily by detecting the time at which the two path outputs differ. The data through signal triggers the storage of the current position data, overwriting the data from the previous position. Once the new data is stored, a data request line is asserted and Fig. 4. Asynchronous Spike Sorting Maximum Function. the comparator is put into reset until new data is presented. In this way, a methodology similar to handshaking is created, but standard logic cells are used and the design was able to pass through the synthesis tools. C. Adaptive Frequency and Voltage Scaling Control Circuitry Assuming that the adaptive frequencies are less than the global clock, we can implement the change in frequency with a clock divider. This is an accurate assumption because lower Vdds should require a lower frequency. The clock divider would essentially just be a counter that counts a whole number of global clock cycles before it turns high. The voltage scaling circuitry would take the global supply and reduce it using one of many possible techniques. Linear regulators are good for small changes in supply voltage but are inefficient when switching between large voltages. A capacitive regulator could also be used, although it would result in voltage ripples. Finally, a magnetic regulator would offer the highest efficiency, but would require external components. We have not synthesized such circuitry, however, so this added overhead should be taken into account later. D. Alternative Critical Path Monitors 1) State-of-the-Art: Subthreshold Critical Path Monitors: Critical path monitors are scarce in recent sub-threshold work, which often cites their lack of ability to deal with local variation as a reason to use timing error detection instead [7]. Because current is exponentially dependent on V th in the subthreshold region, logic delay is extremely sensitive to PVT variation. Therefore, it is difficult to design a robust critical path replica delay line, and most find it easier to allow for and detect errors. The only apparent sub-threshold critical path monitoring circuitry in recent literature was implemented in an asynchronous system [8]. For these reasons we have not attempted to implement a critical path monitor in our adaptive system.

4 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY ) Energy Tracking Alternative: In order to avoid a critical path monitor that is constantly active, we could instead determine the speed of a chip on startup and then use parallel pathways to allow for a slower clock frequency and an equal energy. If the chip is fast, then perhaps only one logic block would be active and operating at some frequency Fs. If the chip is slow, then some number N identical logic blocks would operate at Fs/N. Since you are operating on N data packets at a time, processing N pieces of data would take the same amount of time. The major disadvantage to this technique, however, is that there is a large area overhead due to having N copies of the data path. There would also have to be power gating to the paths that weren t used in order to minimize leakage coming from them. A. Simulations IV. TEST METHODS After describing the logic paths in Verilog, we pushed each module through the EE241 toolflow, which uses a 28/32nm predictive technology. This included simulating in RTL, DC synthesis, and IC Compiler place and route. Once the posticc-par GDS and Verilog files were obtained, these were imported into Cadence Virtuoso as the layout and schematic, respectively, of our module. A transistor level netlist was generated after running LVS and StarRC extraction to include parasitics in our simulations. Figure 5 shows this process flow. Fig. 5. Project Tool Flow. To characterize the synchronous unit, we ran HSPICE simulations at different voltages between 0.2 and 1V, finding the maximum operating frequency at each voltage that resulted in no errors. The measured integrated current drawn from the power supplies, I int, was used to calculate total power over run time and energy per operation with the formula E= Iint V DD x, where x is the number of operations per simulation. We then simulated the asynchronous unit at each of these frequencies, finding the minimum corresponding voltage that gave no errors, and calculated energy per operation in the same manner. For all of these simulations, we swept frequency values only to the most significant digit and voltage values to two significant digits in order to reduce simulation time. We ensured a fair comparison between the asynchronous and synchronous units by simulating under the same conditions, with the same data being input in the form of a.vec test vector file. To make the simulation approximate the amount of switching that would occur with actual neural signals, we used simplified spike data (provided by Rikky Muller) as our test vectors. Additionally, we simulated each unit at body temperature (37 C) as our intended application is an implanted device and must operate within a degree of body temperature. Please note, simulations were only run at the TT corner. The goal of this research is to compare asynchronous and adaptive timing architectures, rather than fully characterize one or the other across all process variations. Process variation should have the same effect on each timing scheme and simply map each scheme to a different timing number. The relationship between the energy of the two should not change. Effectively, if one timing scheme is lower energy at TT, it will be lower energy at the slow and fast corners as well. B. MATLAB Power numbers for the adaptive synchronous technique were determined using a combination of SPICE and MAT- LAB. The logic for the finite state machine associated with the adaptive method was implemented in MATLAB to model the effects in an intuitive manner. In order to create a representative model, the power and energy per cycle required by a synchronous and an asynchronous circuit at various predetermined VDDs and frequencies were evaluated in SPICE, as mentioned above. For the adaptive synchronous method, the MATLAB model determines which VDD and frequency calculation is the most appropriate per cycle based on the fullness of the FIFO. Based on the selected clock frequency, the model removes an appropriate amount of data from the FIFO. This change in FIFO fullness further adjusts the chosen VDD and clock frequency. For both the asynchronous and the purely synchronous method, we selected the VDD that achieved an equal frequency to the maximum input data frequency in order to avoid FIFO overflows. The input data rate for each of the timing methods was varied over the same range, and the total energy required to process a set number of data packets (spikes) was recorded. A. SPICE Results V. RESULTS The maximum operating frequencies for the synchronous circuit at Vdds from 0.2V to 1V as well as the asynchronous Vdd that achieves the same frequency can be seen in Figure 6. The asynchronous circuit can perform at the same frequency as the synchronous circuit, but at a much lower Vdd. To analyze the effect of leakage, the static and dynamic current at each operating point is shown in Figure 7. As expected, the leakage (static) current expontentially increases with increasing Vdd, and the dynamic current increases with the square of Vdd. We can also see that leakage current dominates in this system. Figure 8 compares the energy per operation of the asynchronous and the synchronous circuits at specific frequencies. At high frequencies, the asynchronous circuit requires less

5 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY Fig. 6. For each frequency, the asynchronous circuit can operate at a lower Vdd. Fig. 7. Static and Dynamic Leakage Current vs Vdd. energy because it operates at a lower Vdd. This graph shows that the asynchronous circuit also requires less energy per operation at low frequencies. Thus, this displays no trade off. However, this does not align with the fact that the asynchronous Verilog code actually had more logic and overhead in it than the synchronous code. We would therefore expect the asynchronous to use more energy at low frequencies because it would likely have more gates whose leakage current is integrated for long periods. The key to this discrepancy is that even though there was more logic in the asynchronous Verilog code, Synopsis must have optimized it because the asynchronous netlist actually had 300 fewer mosfets and over 5,000 fewer resistors and capacitors, which significantly reduces leakage. B. Simulated MATLAB Results In the process of determining the maximum operating frequency of our synchronous circuits at various supply voltages in SPICE, we found that even at the lowest supply of 0.2V, the synchronous circuit was able to operate at 250KHz, and the asynchronous circuits was able to operate at 2MHz. Both of these are significantly higher than our ADC sampling rate of 20kHz. Because energy is not lowered if you operate at a slower frequency without scaling the supply, it is not logical to implement an adaptive frequency technique with our current neural spike sorting application. However, adaptive timing is still useful as long as the incoming data frequency is variable and the maximum data frequency is similar to the max circuit operating frequency at high supply voltages. Therefore, in our MATLAB simulations, we set the maximum data stream frequency equal to the synchronous frequency at 0.9V (250MHz). Now, there will be a trade off between faster processing time and lower energy. In order to avoid FIFO overflow in the purely synchronous case, we chose a synchronous frequency of 250MHz (0.9V). This same frequency was also chosen for the asynchronous simulation, but with a required supply voltage of 0.9V. Each packet of relevant data contained 40 8-bit numbers, and 11 packets were sent each simulation. The data event frequency was determined by adjusting the delay between packets. The maximum data event frequency occurs when there is no space between packets (6MHz). When an event is detected, the packet is sent into the FIFO to await processing. Figure 9 shows the total energy required by these three timing techniques and the average chosen processing supply voltage at data event frequencies from 0.2MHz to 5MHz. Fig. 9. MATLAB Results. Top: Total energy required to process 11 data events occuring at various frequencies. The Adaptive method achieves a minimum energy at 0.6MHz and is the lowest energy up to data rates around 1.5MHz. Bottom: Average processing supply voltage. To handle higher data frequencies, the adaptive voltage must increase. Fig. 8. Energy per Operation vs Frequency. Asynchronous is lower energy even at low frequencies. There are a few trends in this figure. First, for the methods that use a set Vdd and frequency, energy is reduced as frequency increases. This is because the circuits are operating at the same Vdd and frequency regardless of whether they are processing data. (The energy associated with lag time between data events was determined in SPICE and accounted for here.) Second, the asynchronous method is always lower energy than the pure synchronous because it requires a lower Vdd for the same frequency. Third, the adaptive method is the

6 EECS 241 PROCEEDINGS, VOL. 14, NO. 2, MAY lowest energy up to data rates around 1.5MHz. This is because at that frequency, the average Vdd needed by the adaptive circuit is greater than the constant Vdd of the asynchronous circuit. Finally, the adaptive method has a minimum energy point at 0.6MHz. This can be explained by examining Figure 10. Each of the graphs show the incoming data stream on top, the number of elements in the FIFO at each clock cycle, and the chosen Vdd based on the FIFO s current state. Spikes were chosen as the data packets here for illustrative purposes only since neurons are incapable of firing at such high frequencies. In the top graph, data coming in at the highest data rate of 5MHz quickly fills the FIFO, which causes the chosen Vdd and frequency to increase accordingly. In the middle graph at 0.6MHz, the circuit is always operating on data at a low Vdd, and there is no dead time spent burning energy while waiting for data to arrive. In the bottom graph at 0.5MHz, we can see that the FIFO is empty periodically, which is not energy efficient. The red indicates waiting time. This is why we see a minimum at 0.6MHz because at this frequency, the average operating voltage is about 0.5V, and there is no idle time. Higher than this frequency requires more energy to process faster data, and lower than this frequency burns more energy waiting for data to arrive. C. Known Approximations and Consequences As previously stated, we only used the TT corner during simulations, as relative energy between the two designs should not change significantly at different corners. Another simplification we made was to use test vector data designed to be representative of typical spike data, not the worse case scenario. Testing across a wide range of frequencies and voltages is an open problem. Finally, we did not take noise into account in our analysis. However, we assume that noise will degrade the performance of both circuits, and can therefore be ignored in a comparative evalutation. Fig. 10. Adaptive Timing MATLAB Simulations. Each of the graphs show the incoming data stream on top, the number of elements in the FIFO at each clock cycle in the middle, and the chosen Vdd based on the FIFO s current state on the bottom. 0.6MHz is optimal because it operates at the lowest Vdd without burning extra energy waiting for data to enter the FIFO. VI. CONCLUSION Our simulations suggest that despite asynchronous logic being able to operate at a lower voltage than adaptive at any one given frequency, adaptive logic actually provides energy savings at data rates below 1.5MHz due to a lower average operating voltage. However, for the speed of a neural processor, both circuits operate at the lowest supply voltage, and leakage current dominates in both. Also, at the minimum supply, there is no room to adapt the voltage any further. No such comparison has been done previously, yet there is still room for improvement. Future work should involve simulating more complex and architecturally complete systems, or an investigation into leakage suppression techniques. The work presented here provides a good first step in a systematic comparison of adaptive and asynchronous timing for neural processors. ACKNOWLEDGMENT The authors would like to thank Bora Nikolic for his patient guidance and mentorship; TT Liu for his willingness to share his research; Nathan Narevsky for answering our many questions about AP detection; Rikky Muller for supplying spike data; Jan Rabaey for insightful discussion and for directing us to several useful references; Stevo Bailey for miscellaneous help with the tool chain and digital logic; and Brian Zimmer for help with troubleshooting and answering our endless questions about the tools used here. REFERENCES [1] T.-T. Liu and J. Rabaey, A 0.25v 460nw asynchronous neural signal processor with inherent leakage suppression, in VLSI Circuits (VLSIC), 2012 Symposium on, June, pp [2] S. Mitra, J. Putzeys, F. Battaglia, C. M. Lopez, M. Welkenhuysen, C. Pennartz, V. Hoof, and R. F. Yazicioglu, 24 channel dual-band wireless neural recorder with activity dependent power consumption, in Solid-State Circuits Conference, ISSCC 13 60th International, Feb. 2013, pp [3] T. D. Burd, Energy-Efficient Processor System Design, Ph.D. dissertation, University of California, Berkeley, Spring [4] C.-C. Peng, P. Sabharwal, and R. Bashirullah, An adaptive neural spike detector with threshold-lock loop, in Circuits and Systems, ISCAS IEEE International Symposium on, May, pp [5] T.-T. Liu, Towards an ultra-low energy computation with asynchronous circuits, Ph.D. dissertation, University of California, Berkeley, 2012.

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