This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and

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1 This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier s archiving and manuscript policies are encouraged to visit:

2 Solid-State Electronics 53 (2009) Contents lists available at ScienceDirect Solid-State Electronics journal homepage: Mobility extraction in SOI MOSFETs with sub 1 nm body thickness M. Schmidt a, *, M.C. Lemme b, H.D.B. Gottlob a, F. Driussi c, L. Selmi c, H. Kurz a a Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Otto-Blumenthal-Str. 25, Aachen, Germany b Department of Physics, Harvard University, 11 Oxford St., Cambridge, MA 02138, USA c DIEGM, University of Udine IU.NET, via delle Scienze 208, Udine, Italy article info abstract Article history: Received 2 June 2009 Received in revised form 9 September 2009 Accepted 10 September 2009 Available online 9 October 2009 The review of this paper was arranged by Prof. S. Mantl Keywords: SOI MOSFET Mobility Fully depleted Ultra thin body In this work we discuss limitations of the split-cv method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-cv measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB- SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-cv measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility. Ó 2009 Elsevier Ltd. All rights reserved. 1. Introduction Scaling of CMOS technology beyond the 32 nm node seems questionable using bulk silicon technology. Fully depleted channel transistors such as Fin-field effect transistors (FinFETs) or ultra thin body silicon-on-insulator (UTB-SOI) MOSFETs are considered promising candidates for future CMOS applications. Their advantages are high short-channel-effect (SCE) immunity, nearly ideal subthreshold swing, enhanced current drive, higher I On /I Off ratios and better control of threshold voltages V th [1 4]. A major concern with fully depleted MOSFETs as the silicon film thickness decreases below 10 nm is their high parasitic source and drain series resistance. While this inherent feature may eventually be solved by selective epitaxy and/or silicided source drain leads [5 7], there is an urgent need to extract reliable device parameters even from test devices available today. Inversion channel mobility, in particular, can not be extracted accurately from standard split- C/V [8] and drain current measurements due to the high parasitic * Corresponding author. Tel.: ; fax: address: schmidt@amo.de (M. Schmidt). source and drain resistance of such MOSFETs, unless specific structures are implemented [9]. For UTB-SOI MOSFETs, a mobility extraction test structure has been proposed that includes additional contacts to the inversion layer [9]. These allow four-point probe measurements of the intrinsic voltage drop across the channel (compare Fig. 1a) and thus eliminate access series resistance. While this mobility test structure has been applied to SOI and strained SOI devices [10,11], it has not yet been tested for ultimately thin channels of a few atomic layers. In addition, the split-cv method requires measuring the gate to channel capacitance. Here, the combination of large access and channel resistance may lead to frequency dispersion effects, similar to the well known effect in conventional MOS capacitors [12]. This must be taken into account when correctly extracting carrier mobility with the split-cv method. In this article, we demonstrate frequency dispersion during mobility extraction with the split-cv method and discuss its effects for UTB-SOI MOSFETs below 10 nm channel thickness by comparing UTB-SOI, recessed-gate UTB and conventional SOI MOSFETs (compare Fig. 1). We further verify a 4-point probe method for mobility extraction to avoid access resistance issues in UTB devices. Finally, we present mobility data extracted with the 4-point probe method and taking into account frequency dispersion from UTB-SOI n-mosfets down to 0.9 nm SOI thickness /$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi: /j.sse

3 M. Schmidt et al. / Solid-State Electronics 53 (2009) conventional SOI MOSFETs, called reference from here on, where the source and drain leads and the silicon channel are 50 nm thick, UTB-SOI MOSFETs, with constant silicon thicknesses below t Si =20nm(Fig. 1b), recessed-gate UTB-SOI MOSFETs, with channels below t Si =30nm, but t Si = 50 nm source/drain leads (Fig. 1c). Fig. 1. (a) Schematic top-view of a 4-point probe SOI MOSFET with two additional contacts to the channel (V L/R ). (b) Schematic cross section of an UTB-SOI MOSFET with a constant silicon thickness across the source, drain and channel. Note that the reference devices are fabricated in a similar manner with a thicker silicon thickness of 50 nm. (c) Schematic cross section of a recessed-gate UTB-SOI MOSFET. 2. Experimental 2.1. Mobility extraction The effective mobility (l eff ) of a MOSFET is defined in l eff ¼ L I DS ðv G Þ ð1þ W V DS Q inv ðv G Þ where L and W are the given gate length and gate width and I DS is the measured drain to source current (as a function of gate voltage V G ). Key for the correct extraction of l eff, however, is the precise knowledge of the internal voltage drop V DS_int across the channel and the measurement of the inversion charge density Q inv. Both V DS and Q inv are strongly affected by high access resistance. Esseni et al. have therefore proposed a specific large area MOSFET with additional contacts to the active channel region [9], as shown schematically in Fig. 1a. For the transistors investigated in this work, we have chosen gate lengths of L = 100 lm and various channel widths of W = 15, 30 and 40 lm. These rather large dimensions minimize the influence of parasitic capacitances. The additional contacts V L and V R are spaced 75 lm and enable the currentless measurement of the voltage drop across L L/R. This voltage can then be extrapolated to the full voltage drop V DS_int between the physical source and drain with their distance of L = 100 lm. The inversion charge Q inv can be determined from the inversion charge density N inv by integrating the gate to channel capacitance C GC measured between the shorted source and drain contacts and the gate as (q is the elementary charge) [8]. Q inv ¼ qn inv ¼ Z V G 1 C GC ðv G ÞdV G In the case of a single gate UTB-SOI MOSFET, the effective vertical electric field E eff can be deduced from Q inv according to [13]: E eff ¼ Q inv 2e Si 2.2. Device fabrication Three different types of devices with intrinsically different access resistances have been fabricated: ð2þ ð3þ Note that the source/drain leads have the same thickness as the channel in both reference devices and UTB-SOI MOSFETs. In the case of recessed-gate UTB-SOI devices, however, the leads are thicker than the channel, which leads to reduced access resistances. The starting material for all devices was UNIBOND SOI substrate with a Si(1 0 0) active silicon layer and a buried oxide (BOX) thickness of 100 nm. All devices are n-mos type with a boron channel doping level of 1e15/cm 3, i.e. virtually undoped and in (1 0 0) orientation. Initial silicon thicknesses of 50, 20 and 10 nm have been used to fabricate the reference and UTB-SOI MOSFETs (Fig. 1b). For recessed-gate SOI MOSFETs (Fig. 1c), the starting material was SOI substrate with a silicon thickness of 50 nm. For these devices, a LO- COS process with a silicon nitride (Si 3 N 4 ) mask has been used to reduce the thickness of the silicon channel areas only. Repeated thermal oxidation and wet chemical oxide removal has been carried out to realize different silicon thicknesses down to 0.9 nm. Standard lithography and reactive ion etching (RIE) have been used for mesa isolation of the devices. A gate oxide of t Ox = 8.4 nm has been thermally grown followed by low pressure chemical vapor deposition of 150 nm poly silicon as gate electrode material. The gates have been patterned in a highly anisotropic HBr/O 2 - based RIE process with high selectivity to the underlying gate oxide [15,16]. Finally, self aligned arsenic ion implantation has been carried out to form the source, drain and gate regions as well as the contacts to the inversion channel (compare Fig. 1a). The dopants have been activated by rapid thermal annealing at 980 C for 45 s in nitrogen ambient. Finally a forming gas annealing step has been applied to passivate interface states and oxide charges and to improve device characteristics. 3. Results and discussion 3.1. Body thickness evaluation The body thickness has been evaluated using CV measurements and transmission electron microscope (TEM) analysis. The CV method, which has been proposed by Chen et al. [17], relies on the accurate decoupling of the gate and silicon capacitances from the buried oxide capacitance. CV measurements between the gate and source/drain contacts for reference and UTB-SOI MOSFETs with nm top silicon thickness are shown in Fig. 2a. Without a back gate voltage (V BG = 0 V), the measured inversion capacitance is modulated by the front gate voltage V G between 4 mf/m 2 and a very low value (due to scale: 0 F/m 2 ), which corresponds to the oxide capacitance of the 8 nm thick gate oxide (4 mf/m 2 ) and to the series of gate-, silicon- and BOX capacitance. However to extract the silicon film thickness from the CV measurement, the gate and silicon capacitances must be decoupled from the BOX. To this end, a back gate voltage has been applied to form an inversion layer at the back interface. The minimum inversion capacitance C inv, i.e. the series capacitance of gate oxide and silicon film, has then been used to extract the respective silicon thickness t Si (for details see e.g. [17]). The resulting body thicknesses t Si have been plotted versus ellipsometry data measured before gate oxide growth (Fig. 2b). The mismatch of 5 nm between electrical and ellipsometric thickness corresponds to the silicon loss during device processing such as wet cleaning and gate oxide growth. The resulting silicon thickness in case of the 10 nm UTB-SOI MOSFET is

4 1248 M. Schmidt et al. / Solid-State Electronics 53 (2009) Fig. 3. Transmission electron microscope cross sectional view of a four atomic layer thin silicon channel, imaged after taking electrical measurements of the recessedgate UTB-SOI n-mosfet (schematic inset). below), and matches the trend of film thicknesses as measured by TEM Gate capacitance measurements Fig. 2. (a) Measured inversion capacitance C inv plotted versus gate voltage for different top silicon thicknesses. The bottom curve (hollow squares) shows a measurement without applying a back gate voltage, and hence includes the BOX capacitance in the measurements. The filled symbols represent measurements where a back gate voltage was applied to deplete the BOX-silicon interface, which is necessary to extract t Si. (b) Calculated body thickness from C inv plotted versus measured body thickness by ellipsometry. The offset is caused by the gate oxidation process. 4.3 nm. For very thin silicon films below 4.3 nm, the capacitance modulation with V G decreases as the oxide capacitance becomes dominant and the CV method fails (not shown). Hence, HRTEM analysis has been used for thickness extraction of films thinner than 4.3 nm. A cross sectional TEM image of a 0.9 nm recessedgate channel, equivalent to four atomic layers (AL), is shown in Fig. 3. Please note that thickness fluctuations of the SOI films in our work have been carefully weighed when interpreting the data. When taking TEM images for the 0.9 nm film, we scanned across almost the entire width of the device. We found thickness fluctuations to be of island type, several 100 nm apart, and only several nanometers in diameter. The thickest island found was 1.7 nm. Considering the symmetry of the silicon crystal the same film characteristics are expected perpendicular to the TEM cross section i.e. along the transport direction. The majority of the film can therefore be regarded as 0.9 nm thin, which dominates the electrical transport. We further conclude from measured gate to channel capacitances (C GC ), that even the thinnest films investigated were indeed continuous. The values obtained from thin films match those of thicker films, with oxide thickness values matching TEM images. If the SOI films were discontinued, we would expect to measure a lower C GC because of a reduced device area (i.e. the discontinuous transistor channels). Finally, our data for threshold voltages, drain currents and effective mobilities is consistent (see A gate to channel capacitance (C GC ) measurement is required for extracting the inversion charge Q inv when determining carrier mobility by the split-cv method (Eq. (2), [7,11,12]). Thus, CV measurements have been performed using the gate and shorted source and drain contacts with frequencies between 1 and 1 MHz for all three available transistor types, reference, UTB-SOI and recessedgate UTB-SOI. Fig. 4a shows the measured gate to channel capacitance C GC vs. gate voltage V G for an UTB-SOI transistor with 4.3 nm silicon thickness. The plot clearly shows a severe drop in inversion capacitance for high frequencies, which can be attributed to the large access and channel resistance in the UTB-SOI device. This frequency dispersion effect is similar to the well known effect in conventional MOS capacitors [12,18]. Fig. 4b compares the inversion capacitance of three different devices at a gate voltage of V G = 3 V. The dispersion effect is evident in the clear drop of C GC for high frequencies. It is least severe for the reference device with its moderate access and channel resistance. Furthermore, the effect is weaker for the 4.3 nm recessed-gate device when compared to the 4.3 nm UTB-SOI device, even though they are equal in channel thickness. The difference can therefore be attributed to the lower access resistance in the recessed-gate UTB-SOI MOSFET. Since according to Eq. (1) the mobility will be overestimated when the measured inversion charge is too small due to frequency dispersion, the measurement frequency must be carefully chosen. In the example in Fig. 4b, a suitable frequency would have to be smaller than 50 khz. The capacitance equivalent oxide thickness extracted from C GC in strong inversion at low frequencies (V G = 3 V) was CET = 8.4 nm for the reference and UTB- SOI MOSFETs and CET = 8.8 nm for the recessed-gate UTB-SOI MOSFETs. This is in good agreement with ellipsometry data taken after thermal dry oxidation and confirms the accuracy of the method at low frequencies Mobility extraction The second crucial part for calculating carrier mobility next to correct C GC extraction is the accurate knowledge of the intrinsic conductance I DS /V DS. While the drain current can be measured straight forward, the effective channel voltage drop V DS_int (Fig. 1a) needs special attention in UTB-SOI devices. High access resistances lead to an overestimation of the voltage drop and - in line with Eq. (1) to an underestimation of the mobility. The electron mobilities of a UTB-SOI device with t Si = 4.3 nm extracted

5 M. Schmidt et al. / Solid-State Electronics 53 (2009) Fig. 4. (a) Gate to channel capacitance C GC plotted versus gate voltage V G of a 4.3 nm UTB-SOI MOSFET as defined in Fig. 1b for different measurement frequencies. (b) Comparison of gate to channel capacitance versus measurement frequency (at V G = 3 V) of a reference MOSFET (red squares), a 4.3 nm recessed-gate UTB-SOI MOSFET (blue dots) and a 4.3 nm UTB-SOI MOSFET (black triangles). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) by 2- and 4-point probe measurements are compared in Fig. 5a. The 2-point measurements (solid symbols) include access resistances and lead to significantly lower mobility values compared to 4-point measurements (open symbols), where the access resistance is eliminated. In addition, Fig. 5a shows mobility extraction errors due to frequency dispersion by plotting both the values for f = 5 khz and f = 100 khz (squares and circles). The resultant underestimation of N inv and hence overestimation of mobility is larger at low E eff, where the channel resistance is largest. The error in mobility caused by access resistance using the 2-point technique, on the other hand, is highest for high E eff. It is nonetheless significant for the peak mobility at low fields, namely 37% for the sample investigated at low frequency (5 khz). We conclude that the 2-point measurement is largely insufficient to obtain the correct mobility for UTB-SOI devices even for very long gate lengths (100 lm) as those used in this work. In addition, the frequency for the split-cv measurement has to be chosen carefully to avoid frequency dispersion. Fig. 5b shows the effective mobility plotted against E eff for a reference MOSFET, an UTB-SOI and a recessed-gate UTB-SOI device (both with t si = 4.3 nm). In this case, all values have been extracted with the 4-point technique and the CV measurements have been carried out at 5 khz, i.e. sufficiently low to suppress dispersion effect (compare Fig. 4b). The reference device shows typical values for silicon MOSFETs and hence the high quality of the fabrication Fig. 5. (a) Electron mobility versus effective vertical electric field E eff measured by 2-point probe (filled symbols) and by 4-point probe techniques (open symbols). In addition, two different CV measurement frequencies are plotted: 5 khz (squares) and 100 khz (circles). (b) Electron mobility plotted versus E eff for a reference MOSFET (red squares), a 4.3 nm recessed UTB-SOI MOSFET (blue dots) and a 4.3 nm UTB-SOI MOSFET (black triangles). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) process. Furthermore, the difference in mobility between the 4.3 nm UTB-SOI and the 4.3 nm recessed-gate UTB-SOI MOSFETs is negligible, which demonstrates that the 4-point technique compensates completely for the influence of high access resistance. The peak mobility of the 4.3 nm UTB-SOI and recessed-gate UTB-SOI MOSFETs is l peak = 450 cm 2 /Vs, in agreement with published data for similar t si [19,20] Fundamental limits of (100) UTB n-mosfets To explore experimentally the ultimate thickness limits of SOI transistors, a series of recessed-gate SOI n-mosfets with body thicknesses down to 0.9 nm has been fabricated and characterized. The measured output and transfer characteristics show fully functional devices with an excellent sub-threshold swing of 70 mv/dec and an I On /I Off ratio of more than six orders of magnitude at 0.9 nm silicon thickness (Fig. 6a and b). The mobility extraction method introduced above, including 4- point probe geometry in combination with a moderate measurement frequency of 5 khz, has been used to evaluate the effective mobility l eff of a number of recessed-gate devices. Mobility data for recessed-gate SOI n-mosfets with silicon body thicknesses ranging from 30 nm down to 0.9 nm is compared to the reference SOI device in Fig. 7. For silicon thicknesses ranging down to 3.6 nm mobility values on the order of several 100 cm 2 /Vs are obtained. Note that mobility values for different transistor widths W coincide

6 1250 M. Schmidt et al. / Solid-State Electronics 53 (2009) Fig. 8. Measured MOSFET threshold voltages V th plotted versus the silicon channel thickness of the transistors showing a severe increase in threshold voltage as the silicon thickness is reduced below 5 nm (open circles). The measured values are compared to a quantum mechanical model (black triangles) described in detail in [22]. Fig. 6. (a) Output characteristics (drain current I DS versus source drain voltage V DS ) and (b) transfer characteristics (drain current I DS versus gate voltage V G ) of a 0.9 nm thick recessed-gate UTB-SOI n-mosfet. for each thickness demonstrating that lateral geometrical variations do not influence the extraction procedure. For recessed-gate UTB-SOI devices with a silicon thickness down to 10.5 nm, the maximum mobility is reached at low inversion channel densities. Devices with silicon body thickness between 4.3 nm and 3.6 nm have their peak mobility at slightly higher N Inv. Furthermore, their mobility is reduced for low inversion charge densities, but reaches values similar to thicker devices for high charge densities. As Coulomb scattering has been reported to reduce carrier mobility [13], we attribute this decrease in the low inversion charge regime to the vicinity of the back interface in these ultrathin SOI devices (compare [20] for t Si = 5 nm devices). Even thinner body thicknesses results in a significant mobility reduction over the whole range of N Inv. A reduction on the order of a decade is observed for thicknesses decreasing from 2 nm down to 0.9 nm, i.e. from 7 to 4 atomic layers. The small l eff dependence on N inv suggests a negligible impact of coulombic centers/interface states in the mobility degradation. Moreover, the l eff reduction follows a t 6 si dependence, which is typical for mobility limitation by t si fluctuation [20]. We therefore attribute it on thickness variations/ surface roughness, which might have been enhanced during the thinning process. In addition, enhanced phonon scattering due to quantization effects has been predicted for layers below 2 nm thickness [14] and is likely to contribute. The observed mobilities on the order of several 10 cm 2 /Vs in silicon films of a few atomic layers confirm the data previously reported by Uchida et al. [20]. It has been reported in literature that carrier confinement not only affects the mobility severely, but it also raises the threshold voltage V th rapidly as the silicon channel gets very thin [21]. This drastic increase of the measured threshold voltage is shown in Fig. 8 (open circles). The divergence is comparable to that observed in [20]. After taking the experimental data, numerical simulations were performed with a Schroedinger Poisson solver described in [22] by assuming a quantization effective mass independent of the t Si value [23]. Furthermore, wave-function penetration into the dielectric was neglected, which is a reasonable approximation for fairly large oxide thicknesses such as used in this experiment. The results of the numerical simulations (black triangles) are consistent with the experimental data. 4. Conclusions Fig. 7. Electron mobility plotted versus inversion carrier density N inv for body thicknesses from t Si = 50 nm down to 0.9 nm (universal mobility after Takagi [13] included for reference). For t si below 3 nm, electron mobility strongly decreases. In this paper, a suitable procedure for the extraction of effective mobility in ultra thin body SOI transistors has been suggested. The

7 M. Schmidt et al. / Solid-State Electronics 53 (2009) influence of access resistances inherent in such thin silicon film thicknesses has been investigated by comparing conventional thick SOI MOSFETs to both UTB-SOI and recessed-gate UTB-SOI MOS- FETs. Standard split-cv measurements using a 2-point probe technique and typical CV frequencies of 100 khz have been shown to be affected severely by high access resistances. In UTB devices, this standard measurement results in erroneous estimation of both the effective source drain voltage and the inversion charge density, and in turn to unreliable mobility data. While deviations in the effective source drain voltage lead to errors at high effective fields, the error caused by frequency dispersion in CV measurements is more pronounced at low effective fields. We have implemented a 4-point probe test structure and combined it with low frequency CV measurements to circumvent the demonstrated difficulties. The measurements have been carefully calibrated by comparing data with conventional SOI transistors with a silicon thickness of 50 nm. In combination with a recessed-gate technology, we have demonstrated mobility extraction for devices with a silicon thickness of less than 1 nm. Finally, a drastic increase in threshold voltage is shown for body thicknesses below 3 nm due to charge quantization effects. This is accompanied by a severe decrease in mobility. This experimentally observed interdependency requires further theoretical consideration to explore the ultimate limit of SOI MOSFETs in general, as the substantial experimental data presented here indicates that the charge transport in UTB-SOI n-mosfets is heavily affected by quantum phenomena and thickness variations for thicknesses below 3 nm. Acknowledgements The authors thank M. Bückins, T.E. Weirich, F. Dorn and J. Mayer of the Central Facility for Electron Microscopy (GFE), RWTH Aachen, for TEM images. This work has been partially supported in the frame of the European Network of Excellence Nanosil (IST ). M.C. Lemme gratefully acknowledges the support of the Alexander von Humboldt foundation through a Feodor Lynen Research Fellowship. References [1] Liu Y et al. A highly threshold voltage-controllable 4T FinFET with an 8.5-nmthick Si-Fin channel. IEEE Electron Dev Lett 2004;25(7): [2] Lindert N et al. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process. IEEE Electron Dev Lett 2001;22(10): [3] Lemme MC et al. Subthreshold behavior of triple-gate MOSFETs on SOI material. Solid-State Electron 2004;48: [4] Doris B, et al. Extreme Scaling with Ultra-Thin Si Channel MOSFETs, In: IEDM Tech Dig; p [5] Choi Y-K, Asano K, Lindert N, Subramanian V, King T-J, Bokor J, et al. Ultrathinbody SOI MOSFET for deep-sub-tenth micron era. IEEE Electron Dev Lett 2000;21(5). [6] Chau R et al. A 50 nm depleted-substrate CMOS transistor (DST). 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