Design and Simulation of a DDS-PLL Hybrid Based Fast Settling Wideband Frequency Synthesiser for Frequency Hopping Radios

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1 Design and Simulation of a DDS-PLL Hybrid Based Fast Settling Wideband Frequency Synthesiser for Frequency Hopping Radios R. Vishnu Broadcast and Communication Group, Centre for Development of Advanced Technology (CDAC), Trivandrum, India vishnur@cdac.in ABSTRACT: Modern software defined spread spectrum radios call for a wideband front-end coupled with an agile frequency synthesizer. In this paper, the design and simulation of a single wideband synthesizer is explained based on a translation loop architecture. This design uses a Direct Digital Synthesis (DDS) and two PLLs in conjunction with a frequency mixer. The main highlights of this design include fast switching speed and narrow channel spacing advantages of the DDS combined with the very low phase noise and spurious performance of PLL. The simulation was done in NI AWR Visual System Simulator (VSS). Analog Devices, ADISimPLL, simulation tool was used for designing loop filters. The method relies on the PLL s ability to switch frequencies in less than 50μs when the step size is >0MHz. The coarse tuning of 0MHz steps will be done in the PLL while fine resolution will be achieved through the DDS. A wideband synthesizer operating in the 00-5MHz frequency range, with a settling time <50μs and phase noise better than -0dBc/Hz is proposed. Spurious performance was better than -75dBc. The paper gives emphasis on the settling time relationship between the two PLLs, which must be taken care in the design or else the loop fails to attain lock. KEYWORDS: Frequency Hopping Synthesizer; DDS-PLL Hybrid architecture; Spread Spectrum; Translation loop; Software Defined Radio CONCLUSION: The simulation work has saved a lot of time and cost for the architecture design. This was done for the design of frequency hopping synthesiser module intended for use in frequency hopping radios. Prototype testing with evaluation board hookups was done and the hardware development is in progress. Quick Response Code Paper URL: ISSN: 0-67 Access this article online Citation Vishnu R, Design and Simulation of a DDS-PLL Hybrid Based Fast Settling Wideband Frequency Synthesiser for Frequency Hopping Radios, International Journal of Research in Wireless Systems (IJRWS), Vol. 4, No., pp. 0-4, December, 05 International Journal of Research in Wireless Systems (IJRWS), Volume 4, Issue, December (05) 0

2 Design and simulation of a DDS-PLL hybrid based fast settling wideband frequency synthesiser for frequency hopping radios R. Vishnu Broadcast and Communication Group Centre for Development of Advanced Technology (CDAC) Trivandrum, India Abstract Modern software defined spread spectrum radios call for a wideband front-end coupled with an agile frequency synthesizer. In this paper, the design and simulation of a single wideband synthesizer is explained based on a translation loop architecture. This design uses a Direct Digital Synthesis (DDS) and two PLLs in conjunction with a frequency mixer. The main highlights of this design include fast switching speed and narrow channel spacing advantages of the DDS combined with the very low phase noise and spurious performance of PLL. The simulation was done in NI AWR Visual System Simulator (VSS). Analog Devices, ADISimPLL, simulation tool was used for designing loop filters. The method relies on the PLL s ability to switch frequencies in less than 50µs when the step size is >0MHz. The coarse tuning of 0MHz steps will be done in the PLL while fine resolution will be achieved through the DDS. A wideband synthesizer operating in the 00-5MHz frequency range, with a settling time <50µs and phase noise better than - 0dBc/Hz is proposed. Spurious performance was better than - 75dBc. The paper gives emphasis on the settling time relationship between the two PLLs, which must be taken care in the design or else the loop fails to attain lock. Keywords Frequency Hopping Synthesizer; DDS-PLL Hybrid architecture; Spread Spectrum; Translation loop; Software Defined Radio I. INTRODUCTION The DDS has the advantage of very low tuning resolution and fast hopping speed but poor wideband spurious performance and the maximum frequency generated can be low. On the other hand, PLL has very good spurious performance, phase noise performance and high frequency generation but the loop dynamics takes finite settling time and the tuning resolution is quite poor. Several architectures evolved using DDS and PLL taking advantage of the merits of both the technologies and trying to avoid the pitfalls [4], [5], [6], [7], [8], and [9]. The performances of various architectures was studied by the evaluation board hook-up and the translation loop based architecture was chosen. The circuit translates the DDS output to a high frequency and hence the name translation loop. Some attractive features of this architecture are: () Frequency translation is used and not division, hence the loop doesn t augment the spurious and phase noise of the DDS within its loop bandwidth, () A spur free region can be identified for the DDS operation as it needs to work within a small bandwidth () The PLL acts as a tracking filter, removing spurious components coming outside its loop bandwidth, (4) The PLL requires coarse tuning thus the integer spurs are far off allowing the loop bandwidth to be widened for increasing the tuning speed, (5) Spurious sources are integer boundary spurs which can be avoided by careful frequency planning. The paper does a system level analysis of the translation loop. DDS is not included in the simulation and a tunable frequency source is used in place of that. The architecture comprises multi-loop PLL using two PLLs in conjunction with a mixer. The overall settling time of the loop is dependent on the settling times of both the PLLs. Moreover the settling time of one must be a factor greater than the other to maintain loop stability. The design inputs for the loop filters of both the PLLs are based on these settling time figures. II. FREQUENCY PLANNING AND ARCHITECTURE Figure shows the frequency plan of the RF front-end which converts the RF frequency range to the fixed IF of 70MHz using a high side LO configuration. The 70-58Mhz is the hopping frequency range of the LO MHz Figure : Front-end frequency plan International Journal of Research in Wireless Systems (IJRWS), Volume 4, Issue, December (05)

3 Figure : Frequency synthesizer block diagram A. ARCHITECTURE The block diagram of the frequency hopping synthesizer is shown in Figure. The major blocks of this synthesizer are:. DDS and its clock synthesizer. The DDS output is fed as a reference to PLL.. PLL generates the fundamental output. Frequency Mixer 4. PLL feeds the LO to the mixer 5. Reference Oscillator 6. Frequency divider which divides the fundamental output to the main output frequency The circuit translates the DDS output frequency to a high frequency signal, which is divided down by the divider to the required LO. The mixer translates the high frequency output of PLL to a low IF frequency which is fed to the feedback input of PLL. Once the loop is locked, this feedback signal frequency will be equal to the DDS output frequency. The O/P frequency will be fout= (fpll±fdds)/div () The polarity in equation () will be decided by the phase detector polarity set in PLL. In the present design, we have used the positive polarity, therefore, fpll=fpll+fdds () Output frequency of the DDS, fdds = FTW x fclk / ^, () where FTW Frequency Tuning Word of DDS and fclk DDS Clock frequency fpll = N x fref, (4) where fref = 0MHz reference, N N counter of PLL So PLL will be tuned to a coarse frequency at 0MHz and a fine tuning of 0.Hz will be done in the DDS. B. FREQUENCY PLAN TABLE : Design Frequency Plan Divider Start Freq Stop Freq (MHz) (MHz) The present frequency plan of the synthesizer is given in Table. PLL operates between 0MHz and 750MHz. By using divisions from to 9, the final LO with the frequency range can be synthesized. III. PHASE NOISE ANALYSIS PLL N=R=7, PFD = varies from 7.8MHz to.4mhz (DDS O/P from 50 MHz to 80MHz) PLL FOM = -dbc/hz Phase noise of PLL = PLL FOM + 0log (PFD) +0log (N) = - + 0log (0e6) + 0log (7) = -5dBc/Hz () PLL R=, PFD=0MHz, PLL FOM = -dbc/hz Max N = 74 Phase noise of PLL = PLL FOM + 0log (PFD) +0log (N) = - + 0log (0e6) + 0log (74) = -08dBc/Hz () DDS CLK PLL Ø noise of DDS CLK PLL = PLL FOM + 0log (PFD) +0log (N) = -0+0log (5e6) + 0log (6) = -08dBc/Hz () DDS Output The highest O/P frequency of DDS=70MHz Phase noise at DDS O/P = Phase noise of DDS CLK+0log (fdds/fclk) = log (70/655.6) = -7dBc/Hz (4) These calculations were for the highest LO frequency where the N counter will be largest thus possessing the least phase noise. From the aforementioned results it can be deduced that the output phase noise of the PLL at the divider input will be approximately -08dBc/Hz influenced mainly by PLL. Here the output divider will be (which is the lowest), hence a phase noise advantage of 9.5dB. International Journal of Research in Wireless Systems (IJRWS), Volume 4, Issue, December (05)

4 ID=VCO5 FRQ=0 MHz PWR=0 dbm K50e6 ID=VCO FRQ=0 MHz PWR=0 dbm K50e6 ID=R ID=V ID=R ID=V PFDCP ID=C4 IUP=5 ma IDN=5 ma ILEAK=0 ma DELAY= us R V PFD DLY_SMP ID=A DLY= IVAL=0 PFDCP ID=C IUP=5 ma IDN=5 ma ILEAK=0 ma ID=Current DELAY= us R V PFD DLY_SMP ID=A DLY= IVAL=0 ID=Current ID=aftDIV ID=aftDIV RD_PASS ID=LP C=000 pf C=800 pf C=90 pf R=47 Ohm R=49 Ohm RD_PASS ID=LP C=80 pf C=000 pf C=4700 pf R=00 Ohm R=00 Ohm DIVIDER ID=C N=Div VP= DIVIDER ID=C N=Div VP= ID=Vcont PHASENS ID=A5 PNMASK="Phmask" ID=Vcont PHASENS ID=A6 PNMASK="Phmask" ID=preDIV ID=preDIV ID=VCO4 FRQ=500 MHz PWR=7 dbm K60e6 ID=VCO FRQ=400 MHz PWR=0 dbm K60e6 LPFB ID=F LOSS=0 db N= FP=80 MHz NOISE=Auto ID=OUT ID=FirstLO MIXER_B ID=A MODE=DIFF GCON-6.5 db N6.5 db NOISE=Auto ID=MIX_OUT Design and Simulation of a DDS-PLL Hybrid Based Fast Settling Wideband Frequency Synthesiser for Frequency Hopping Radios IV. SIMULATION RESULTS AND MEASUREMENTS Translation loop PLL section is used for simulation. The divider is excluded and the DDS is replaced with a tunable frequency source. The overall loop settling time is decided by the settling time of PLL as well as PLL. System Simulation of the translation loop synthesiser was done in NI AWR VSS and the loop filter designs were done using Analog Devices, ADISimPLL. The system requirements call for a settling time <50µs and phase noise better than -0dBc/Hz. Based on these initial requirements, PLL was designed for a settling time of 50µs, which corresponds to a loop bandwidth of 85kHz. After simulation it was found that the PLL settling time should be a factor lower than the PLL settling time to guarantee a lock. The settling time of PLL was found out empirically by reducing it from 50µs until a value was reached that supported stable operation. This is a cyclic procedure where the loop filter for a particular settling time is designed in Analog Devices, ADISimPLL and the values were entered in NI AWR VSS and checked for stability. If the design was not stable, the loop filter was redesigned and applied where a marginal value was chosen and the loop filter fixed. The simulation showed that the PLL settling time has to be <5µs for the loop to lock correctly. But this would be a different value for the PLL loop filter. The simulation circuit is shown in Figure and the simulation result for the 50µs settling time design is shown in Figure 4. Figure 4: Simulation result of the designed 50µs settling time Figure 5 demonstrates unstable conditions observed when the settling times of the PLLs are not configured properly. The instability is caused when the loop bandwidth of PLL was increased to 00kHz (settling time to 0µs). The PLL loop filter should thus be widened to reduce its settling time to achieve stability. R IN OUT C R C C Loop BW=00kHz LO Figure 5: Simulation showing the instability condition Div=7 N Figure 6 shows the frequency spectrum at PLL output, PLL output and the mixer IF output. This was for the PLL output of 740MHz, in which case the PLL is operating at 670MHz and the DDS tuned to 70MHz. R C R C C Loop BW=00kHz N Div=67 Figure : Simulation in NI AWR VSS Figure 6: Frequency spectrum at various nodes of the simulation International Journal of Research in Wireless Systems (IJRWS), Volume 4, Issue, December (05)

5 V. CONCLUSION The simulation work has saved a lot of time and cost for the architecture design. This was done for the design of frequency hopping synthesiser module intended for use in frequency hopping radios. Prototype testing with evaluation board hookups was done and the hardware development is in progress. REFERENCES [] David Crook, Hybrid Synthesizer Tutorial, Microwave Journal, February, 00 [] Dean Banerjee, PLL performance,simulation and design, Dog Ear Publishing, LLC, 00, Second Edition, pp [] National Instruments (NI) AWR Design Environment (AWRDE) help documentation [4] Meng Hu; Ling Wang; Xiaohong Tang, "A low spurious and small step frequency synthesizer based on PLL-DDS-PLL architecture," ICCS 008. th IEEE Singapore International Conference on Communication Systems, 008., vol., no., pp.47,474, 9- Nov. 008 [5] Li YongKe, "The design of wide BW frequency synthesizer based on the DDS&PLL hybrid method," ICEMI '09. 9th International Conference on Electronic Measurement & Instruments, 009., vol., no., pp.-689,-69, 6-9 Aug. 009 [6] Bonfanti, A.; Amorosa, F.; Samori, C.; Lacaita, A.L., "A DDSbased PLL for.4-ghz frequency synthesis," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no., pp.007,00, Dec. 00 [7] Longjun Zhai; Yonghua Jiang; Xiang Ling; Weilang Gao, "DDS-driven PLL frequency synthesizer for X-band radar signal simulation," ISSCAA 006. st International Symposium on Systems and Control in Aerospace and Astronautics, 006, vol., no., pp. pp., 46, 9- Jan. 006 [8] Jaehung Choi; Minsu Kim; Seungha Shin; Youngoo Yang, "Low phase noise S-band PLL frequency synthesizer using DDS and offset mixing techniques," Microwave Conference, 009. APMC 009. Asia Pacific, vol., no., pp.409, 4, 7-0 Dec. 009 [9] Zhao, Z.Y.; Li, X.Y.; Chang, W.G., "LFM-CW signal generator based on hybrid DDS-PLL structure," Electronics Letters, vol.49, no.6, pp., March 4 0 International Journal of Research in Wireless Systems (IJRWS), Volume 4, Issue, December (05) 4