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1 Scholars' Mine Masters Theses Student Research & Creative Works Fall 2012 Computation of power plane pair inductance, measurement of multiple switching current components and switching current measurement for multiple ICs with an island structure Liang Li Follow this and additional works at: Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Li, Liang, "Computation of power plane pair inductance, measurement of multiple switching current components and switching current measurement for multiple ICs with an island structure" (2012). Masters Theses This Thesis - Open Access is brought to you for free and open access by Scholars' Mine. It has been accepted for inclusion in Masters Theses by an authorized administrator of Scholars' Mine. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact scholarsmine@mst.edu.

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3 COMPUTATION OF POWER PLANE PAIR INDUCTANCE, MEASUREMENT OF MULTIPLE SWITCHING CURRENT COMPONENTS AND SWITCHING CURRENT MEASUREMENT FOR MULTIPLE ICs WITH AN ISLAND STRUCTURE by LIANG LI A THESIS Presented to the Faculty of the Graduate School of the MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY In Partial Fulfillment of the Requirements for the Degree MASTER OF SCIENCE IN ELECTRICAL ENGINEERING 2012 Approved by Jun Fan, Advisor Albert E. Ruehli Daryl Beetner

4 2012 LIANG LI All Rights Reserved

5 iii PUBLICATION THESIS OPTION This thesis consists of the following three articles that have been formatted according to the university s spec of thesis, and published as follows: Pages 3 62 have been accepted to be published in 2012 Electrical Performance of Electronic Packaging and Systems (EPEPS), Tempe, AZ. Pages have been published in 2011 IEEE International Symposium on Electromagnetic Compatibility, Long Beach, CA. Pages have been published in 2012 IEEE International Symposium on Electromagnetic Compatibility, Pittsburgh, PA.

6 iv ABSTRACT The first part of the thesis presents the computation of power / ground plane pair inductance based on Partial Element Equivalent Circuit (PEEC) method in power distribution network (PDN) design. An efficient approach for the inductance computation is investigated. Speed-up techniques are employed include using the faster decay of mutual coupling due to the differential currents (same magnitude but opposite directions) in the two planes. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density. The second part presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post dataprocessing procedure is introduced to separate and obtain the parameters of multiple current components. The third part proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure. Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island. Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated. The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage.

7 v ACKNOWLEDGMENTS I would like to express my sincere gratitude to my advisor, Dr. Jun Fan, for his constant encouragement, support and guidance throughout my master degree program. I want to thank Dr. Albert Ruehli, Dr. James Drewniak, Dr. David Pommerenke and Dr. Daryl Beetner for their guidance on my research work. I also want to thank all the EMC Lab students for their help. I would like to thank my wife, Lei Hua, for her love and support throughout these years. I would also like to thank my family for their endless love and unconditional support during my study in US.

8 vi TABLE OF CONTENTS Page PUBLICATION THESIS OPTION... iii ABSTRACT... iv ACKNOWLEDGMENTS... v LIST OF ILLUSTRATIONS... viii SECTION PAPER 1. INTRODUCTION...1 I. ACCURATE AND EFFICIENT COMPUTATION OF POWER PLANE PAIR INDUCTANCE ABSTRACT INTRODUCTION THEORY AND FORMULATION CONCEPTS OF PARTIAL INDUCTANCE PEEC METHOD MODIFIED NODAL ANALYSIS (MNA) THE PPP APPROACH UNIFORM AND NON-UNIFORM MESH ASSEMBLY OF MNA BOOKKEEPING OF NODES COMPUTATION SPEED-UP COMPUTE TIME ANALYSIS NUMERICAL EXPERIMENT MULTIPLE CONTACTS NON-UNIFORM MESH NUMERICAL EXPERIMENT FOR NON-UNIFORM MESH CLOSE VIAS DETERMINE SUB-MESH REGION VALIDATION OF SUB-MESH METHOD... 45

9 vii CURRENT DISTRIBUTION ANALYSIS EFFICIENCY OF SUB-MESH METHOD VIA INDUCTANCE PLANE INDUCTANCE WITH DIFFERENT SHORT LOCATIONS APPLICATION IN PDN DESIGN CONCLUSION BIBLIOGRAPHY II. MEASUREMENT OF MULTIPLE SWITCHING CURRENT COMPONENTS THROUGH A BULK DECOUPLING CAPACITOR 63 ABSTRACT INTRODUCTION PROPOSED CURRENT PROBE SEPARATION AND CHARACTERIZATION OF MULTIPLE CURRENT COMPONENTS CONCLUSION BIBLIOGRAPHY III. SWITCHING CURRENT MEASUREMENT FOR MULTIPLE ICs SHARING A COMMON POWER ISLAND STRUCTURE 77 SECTION ABSTRACT INTRODUCTION THEORY AND MEASUREMENT SETUPS RESULTS AND DISCUSSIONS CONCLUSION BIBLIOGRAPHY CONCLUSIONS...93 APENDEX. 95 VITA..97

10 viii LIST OF ILLUSTRATIONS Paper I Page Figure 2.1 Division of conductors into segments Figure 2.2 Power/Ground plane pair with IC and decoupling capacitors Figure 2.3 Current distribution on power and ground planes Figure 2.4 Plane subdivision Figure 2.5 Partial inductance evaluation Figure 2.6 Two parallel thin conductors Figure 2.7 i-th and j-th section Figure 2.8 The corresponding equivalent circuit of i-th and j-th section Figure 2.9 Partial-mutual inductance between two sections calculated by the closed-form formula and approximated method Figure 2.10 Relative error between the closed-form formula and approximation Figure 2.11 Normalized to partial-self inductance Figure 2.12 Criteria to apply the approximation formula Figure 2.13 Schematic of criteria determination when err = 3% Figure 3.1 Example with the smallest structure. (a) Mesh in x and y direction. (b) Partial inductance in x and y direction Figure 3.2 Equivalent circuit of the example with the smallest structure Figure 3.3 Bookkeeping of the nodes Figure 3.4 Example for partial-self and partial-mutual inductance calculation Figure 3.5 Total compute time vs. unknowns Figure 3.6 Time for stamping MNA matrix vs. unknowns Figure 3.7 Time for solving MNA matrix vs. unknowns Figure 3.8 Test geometry Figure 3.9 PWR/GND pair with multiple vias Figure 3.10 Test geometry with 10 contacts Figure 3.11 Test geometry for multiple shorts Figure 3.12 Compute time comparison for multiple contacts. (a) PPP approach. (b) Cavity model

11 ix Figure 3.13 Non-uniform mesh. (a) Sub-mesh near the port region. (b) Zoom-in of the interface in x direction. (c) Zoom-in of the interface in y direction Figure 3.14 Transition between mesh density Figure 3.15 Sub-mesh around the vias Figure 3.16 Close vias covered by one sub-mesh region Figure 3.17 Define the sub-mesh region around the vias Figure 3.18 Current distribution on the plane. (a) x direction; (b) y direction Figure 3.19 Test geometry for the inductance calculation [8]. (a) Variables are spacing between two vias, l, and separation between two planes, d. (b) Port condition Figure 3.20 Current distribution in x direction on the plane with d = 1mm and l = 1.5 mm. (a) Total current distribution in x direction. (b) Current vector in x direction at the source and short Figure 3.21 Current distribution in y direction on the plane with d = 1mm and l = 1.5 mm. (a) Total current distribution in y direction. (b) Current vector in y direction at the source and short Figure 3.22 Zoom-in of current vector at source and short on the plane with d = 1mm and l = 1.5 mm Figure 3.23 Current distribution in x direction on the plane with d = 1mm and l = 25.5 mm. (a) Total current distribution in x direction. (b) Current vector in x direction at the source port. (c) Current vector in x direction at the short Figure 3.24 Current distribution in y direction on the plane with d = 1mm and l = 25.5 mm. (a) Total current distribution in y direction. (b) Current vector in y direction at the source. (c) Current vector in y direction at the short Figure 3.25 Current vector on the plane with d = 1mm and l = 25.5 mm. (a) Zoom-in of the current vector between source and short. (b) Current vector at the source port. (c) Current vector at the short Figure 3.26 Via constructed with 4 metal sheets Figure 3.27 Zero thickness conductors at 90 deg angle Figure 3.28 Source via and short via Figure 3.29 Geometry for board inductance test. (a) Source fed at center. (b) Source fed at a corner Figure D plot for inductance with the source fed at center and the short placed at different locations on the board Figure D plot for inductance (ph) with the source fed at center and the short placed at different locations on the board

12 x Figure D plot for inductance (ph) with the source fed at corner and the short placed at different locations on the board Figure D plot for inductance (ph) with the source fed at corner and the short placed at different locations on the board Paper II Figure 2.1 Structure of the proposed low-cost probe Figure 2.2 Measurement setup for current probe calibration Figure 2.3 Equivalent circuit of the measurement setup shown in Figure Figure 2.4 Figure 3.1 Figure 3.2 Figure 3.3 Transfer coefficient of the lab-made current probe for a specific bulk capacitor package Experimental setup of the bulk capacitor current measurement using the lab-made current probe Induced voltage and corresponding current. (a) Measured induced voltage in the current probe; (b) Current calculated from Eq. (1) Measured current component that results in the induced voltage peaks using the triggered averaging technique Figure 3.4 The proposed post data-processing procedure Figure 3.5 Post data processing to obtain the highest peak for current components with slow (a) and fast (b) transient time Figure 3.6 Averaged current waveforms for (a) slower and (b) faster current components when the bulk capacitor value is 10 F Paper III Figure 2.1 Figure 2.2 A picture of the functioning board under study: three ICs sharing a common power island structure Same board with (a) three ICs removed (top layer) and (b) port locations (bottom layer) Figure 2.3 A simple four-port network describing the behaviour of the power island.. 82 Figure 2.4 Setup of multiport S-parameter measurement Figure 2.5 Setup of oscilloscope measurement Figure 3.1 Figure 3.2 Magnitude spectra of the noise voltages at the IC ports (Ports 1-3) in the frequency range of 10 MHz to 1 GHz: without the 10 F decoupling capacitor placed at Port Magnitude spectra of the noise voltages at the IC ports (Ports 1-3) in the frequency range of 10 MHz to 1 GHz: with the 10 F decoupling capacitor placed at Port

13 xi Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Magnitudes of the calculated equivalent switching current drawn by IC 1 for both cases of with and without the decoupling capacitor at Port Magnitudes of the calculated equivalent switching current drawn by IC 2 for both cases of with and without the decoupling capacitor at Port Magnitudes of the calculated equivalent switching current drawn by IC 3 for both cases of with and without the decoupling capacitor at Port Magnitude comparison between the calculated and the measured noise voltages at Port 4, without the decoupling capacitor placed at Port Magnitude comparison between the calculated and the measured noise voltages at Port 4, with the decoupling capacitor placed at Port

14 xii LIST OF TABLES Page Paper I Table 2.1 Minimum section distance to satisfy 3 % err, plane spacing = 0.5 mm Table 3.1 Branch number and corresponding nodes at the ends Table 3.2 Branch voltage Table 3.3 Node current Table 3.4 Bookkeeping of the nodes Table 3.5 Compute time with different plane sizes Table 3.6 Calculation results with different methods Table 3.7 Plane pair inductance with 10 shorts Table 3.8 Multiple shorts Table 3.9 Weighted KCL matrix Table 3.10 Inductance calculated using uniform mesh and sub-mesh methods Table 3.11 Plane net inductances from the hybrid, PEEC solver and PPP methods Table 3.12 Comparison between sub- and uniform mesh methods Table 3.13 Partial inductance of the source via, ph, d = 0.2 mm, l = 1.5 mm Table 3.14 Comparison of partial inductance of via and total inductance Table 3.15 Code performance for large geometry... 58

15 1. INTRODUCTION A power distribution network (PDN) is used to deliver power to the core logic and input / output (I / O) circuits on multilayer printed circuit boards (PCBs). Nowadays, the internal clock frequency of modern electronic devices has been more than several GHz, and the switching current is up to tens of amperes. With silicon technology going to nanometer feature dimension, the increasing number of I/Os in simultaneous transmission demand significant amount of transient current in PDN. With faster switching speed, higher circuit density, lower supply voltages and smaller feature size in integrated circuits (ICs) design, the voltage noise become a serious issue, affecting power and signal integrity (PI & SI) as well as causing electromagnetic interference (EMI) problems in high speed electronic devices. It is well known that the power / ground (PWR / GND) noise should be sufficiently suppressed, such as simultaneous switching noise (SSN) which is one of the main sources for many SI, PI and EMI issues. Decoupling capacitors in PWR and GND planes are widely used to stabilize the supply voltage levels in multilayer packages and PCB structures by supplying the charge needed for the switching current. However, the parasitic inductances due to the current loop in the power delivery and return path impede the current supplied to the chip, limiting the effectiveness of the decoupling capacitors to rapidly provide charge. Therefore, quantifying the parasitic inductance of PWR and GND planes is critical for problems associated with PDN design. Full-wave simulation methods have been used to model the PWR / GND layer pair to determine the impedance of the PDN, including the parasitic inductance. However, the full-wave methods may require long compute time and huge memory resources. An efficient approach based on partial element equivalent circuit (PEEC) is proposed for fast impedance calculation of parallel planes. To evaluate the performance of a PDN, target impedance is a widely used guideline for PDN design. It is a reverse problem of PDN noise analysis to establish the target impedance specification for PDN design. In PDN noise analysis, the maximum noise voltage induced by IC switching currents can be simulated or calculated using an appropriate PDN model and switching currents. Conversely, target impedance for PDN design is obtained from the knowledge of switching currents and the maximum PDN

16 2 noise tolerance. Therefore, the waveform of IC switching currents in time domain is necessary to develop the target impedance. In some real-world hardware measurements, it is found that multiple current components could exist in the time-varying current flowing through a decoupling capacitor. Further, when the current through a bulk decoupling capacitor is of interest, it needs to be measured at the frequencies as low as a few hundred KHz. A lab-made low-cost current probe is developed with very small in size, suitable for dense-pcb applications and sensitive enough for low-frequency measurements. A post data-processing procedure is developed to separate the effects of different current components, and to obtain the parameters important for target impedance. In some PDN designs, there are multiple ICs sharing a common power island structure. When detailed IC information is available, chip-level modeling is an effective way to obtain the switching current information. However, IC information is proprietary and usually unavailable for most PCB designers. A measurement-based method is developed to handle the situation where multiple ICs share a common power island and IC information is not available. The measured time-domain noise-voltage waveforms are converted into the frequency domain through the Fourier transform. Together with the S- parameter measurement of the multi-port power-island structure, equivalent switching currents including both magnitude and phase are obtained, which is important for optimized PDN design (such as target impedance).

17 3 I PAPER ACCURATE AND EFFICIENT COMPUTATION OF POWER PLANE PAIR INDUCTANCE Liang Li, Albert E. Ruehli, Jun Fan Missouri University of Science and Technology, Rolla, MO, 65401, USA llh9b@mst.edu, albert.ruehli@gmail.com, jfan@mst.edu ABSTRACT Computation of power-plane inductance for multiple ports is an important part of power distribution network (PDN) design. In this paper, we present an efficient approach for the inductance computation. Since this PEEC approach is based on partial inductance computations, vias and other discontinuities can be accurately taken into account. Speedup techniques are employed like the faster decay of mutual coupling due to the differential currents (same magnitude but opposite directions) in the two planes. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density.

18 4 1. INTRODUCTION The internal clock frequency and input-output (IO) speed in modern high speed digital devices increase dramatically, and the current density becomes higher, which results in increased current demand from the PDN of the board. When numerous logic gates and buffers inside integrated circuits (ICs) switch simultaneously, they induce significant voltage drops or ripples in the PDN, resulting in critical power integrity issues and electromagnetic (EM) interference problems [1]. The power noise in the supply voltage can further couple to the signal traces transitioning through the power and reference (often denoted as ground ) planes and result in signal integrity problems [2]. On-chip and off-chip decoupling capacitors are used to provide the needed charge for the switching current. Within the frequency range from megahertz to hundreds of megahertz, the off-chip decoupling capacitors in the power and ground planes are widely used to make the supply voltage stable in the printed circuit board (PCB) by achieving low power supply impedance [3]. However, the parasitic inductances due to the current loop in the power delivery and return path impede the current supplied to the chip, limiting the effectiveness of the decoupling capacitors to rapidly provide charge. Therefore, quantifying the parasitic inductance of the power and ground planes is critical for the problems associated with PDN design. Many techniques are available today to determine the PDN impedance, including the parasitic inductance between power and ground planes. Full-wave electromagnetic modeling methods have been widely used to model the power/ground layer pair problem, such as finite-difference time domain (FDTD) [4], the finite-element method (FEM) [5] and the method of moments (MOM) [6]. However, full-wave methods require significant computing time and resources for complicated hierarchical PDN structures. Other approaches such as transmission-line methods [7] and the resonant cavity model [8] are usually much faster than full-wave numerical methods and can be easily included into circuit simulations, but the accurate computation of the inductances for power/ground plane pair with multiple decoupling capacitor placements can still be very time consuming.

19 5 In this paper, an efficient Plane Pair PEEC (PPP) approach is proposed. The decoupling capacitors can be modeled by single-lumped inductance macromodels assuming that the capacitive impedance is small at the frequencies of interest. The portions of the inductances associated with the parallel planes are calculated using the proposed PPP approach, and the remaining portions associated with the package of the capacitors, bonding pads and vias can be easily added with very little extra computation time. In the PPP approach, the inductive coupling between different cells decays very fast, which is used to obtain a sparsification of the partial mutual inductance evaluation. Speed-up techniques are employed to save the computational time and memory usage. Both uniform and non-uniform mesh methods were investigated and validated. Our model is flexible to choose ports and change decoupling capacitor locations. Change of the plane pair inductance due to the change of decoupling capacitor locations can be easily calculated which provides useful guidelines for PDN designs.

20 6 2. THEORY AND FORMULATION 2.1. CONCEPTS OF PARTIAL INDUCTANCE The definition of the inductance for a system of N loops is given as, ij Lij for Ik 0 if k j (1) I j where ij is the magnetic flux in loop i due to the current I j in loop j. The magnetic vector potential A at any observation point r generated by the current I j is [9], I dl da A (2) j j j 4 a j aj j r where r r r j, dl j is the element of conductor j with the direction along the axis of the conductor and a j is the conductor cross section perpendicular to the current flow. A uniform current density is assumed in conductor j with a constant cross section a j along the loop. The average magnetic flux as, ij in loop i can be related to the vector potential A j 1 A dl da ij a i a j i i (3) i i where a i represents the constant cross section of conductor i. The mutual inductance for the loops i and j can be expressed as [9]. L 1 dl dl da da a a (4) i j ij 4 i a i j i j a j i j r ij

21 7 Relations for the inductance between the parts of circuits can be further developed from Eq. (4). The integrations over the lengths can be expressed as summations over the straight loop segments and all segments are allowed to have a different cross section as show in Eq. (5) [9], L 1 K M ck cm k m ij dakda 1 14 a m k am bk bm k m akam rkm dl dl (5) where the ith loop is divided into K segments while jth loop is consist of M segments. The starting points b k, b m and the ending points c k, c m are the limits in the integrals. Partial inductance is defined as the argument of the double summation in Eq. (6) for the conductor segments as [9], Lp 1 4 a a ck cm dlk dlm da da r. (6) km ak a k m m bk bm k m km The sign of Lp km is accounted for by a factor S km as Eq. (7), K M Lp S Lp. (7) ij km km k1 m1 S km represents the sign (±1) associated with the particular partial inductance, which is positive by definition. S km depends on the direction of current flow in the conductors. Partial self-inductance is evaluated from the definition of partial inductance in Eq. (6), where integration i and integration j are both over the same conductor, Lp 1 dl dl l l' i i' ii da ' 4 i i' 0 0 ida a a i aiai ' rii '. (8)

22 PEEC METHOD The Partial Element Equivalent Circuit (PEEC) was developed by A. Ruehli in the 1970s and 1980s [10]. The PEEC method is used for numerical modeling of electromagnetic (EM) problems. It models electric-field interactions as capacitances and magnetic-field interactions as inductances. Using the PEEC method, problem under study is transferred from the EM domain to the circuit domain where the conventional SPICElike circuit solvers can be employed to analyze the equivalent circuit. By applying the PEEC method, all electrical components e.g. passive components, sources, non-linear elements, ground, etc. can be easily integrated together. Moreover, by using the PEEC method it is easy to separate the resistive, capacitive or inductive effects. To apply the PEEC method, all of the conductors in the problem must first be subdivided into N canonical primitive structures, such as rectangular bars, for which formulas for resistance, partial self-inductances, and partial mutual-inductances are known. For example, Figure 2.1 shows an interconnect with two signal traces and a plane return path. The conductors are subdivided to rectangular bars. The small, generically shaped conductors in Figure 2.1 are called branches. The resistances and inductances are then assembled into a complete circuit and solved with a circuit simulator. The accuracy improves with finer-grained subdivision of the original geometry [11]. Figure 2.1. Division of conductors into segments. Assume the current is uniform across the cross section of the branches. Then relatively simple DC resistance and static inductance formulas are applicable. The resistance and partial self-inductance of each branch is computed along with the partial

23 9 mutual-inductance between each pair of branches. Assemble the results into a diagonal N N resistance matrix and an N N partial inductance matrix. The voltage drops across the branches are, V b ( R jl) I b Z p I b (9) where I b are the branch currents MODIFIED NODAL ANALYSIS (MNA) The branches are connected together at a number of nodes. The number of the nodes, M, depends on the subdivision used. By satisfying Kirchhoff s voltage (KVL) and current laws (KCL), a dedicated solver for the PEEC method can be constructed. Each branch voltage is defined by the difference of the two node voltages at the ends of the branch. It can be shown, V b AV n (10) where A is the incident matrix, and stores all of the connection information in an N M matrix, where N is the number of the branches. A is constructed by setting Abi 1and A 1when the current flows from node i to node j through branch b. bj The total currents into the nodes are given by, I n T A I b (11) where I n are the currents driven into the nodes by external sources, and I b are the branch currents. In general, most of the I n are zero since current is externally supplied only at the ports.

24 10 The Modified Nodal Analysis (MNA) is easy to implement algorithmically on a computer which is a substantial advantage for automated solution. There are two main aspects to be considered when choosing algorithms: accuracy and speed. The MNA has been proved to accomplish these. The MNA applied to a circuit with passive elements, independent current and voltage sources and active elements results in a matrix equation of the form, [ A][ x] [ z]. (12) For a circuit with M nodes and N independent voltage sources (branches), the A matrix is (N+M) (N+M) in size, and consists only of known quantities. The A matrix is developed as the combination of 4 smaller matrices, B, C, D and G, B D A C G (13). The B matrix is N N in size and is zero if only independent sources are considered. The C matrix is N M in size with only 0, 1 and -1 elements and is determined by the connection of the voltage sources (branches). The D matrix is M N in size and is equal to the transposed C matrix. The G matrix is M M in size and is determined by the interconnections between the circuit elements. The x vector is (N + M) 1 in size, which holds the unknown quantities and is developed as the combination of two smaller vectors, v and i, v x i (14). The v vector is M 1 in size and holds the unknown voltages. The i vector is N 1 in size and holds the unknown currents through the voltage sources (branches).

25 11 The z vector is also (N + M) 1 in size, which is developed as the combination of two smaller vectors p and q, p z q (15). The p vector is M 1 in size with each element of the vector corresponding to a particular node. The value of each element of p is determined by the sum of current sources into the corresponding node. If there are no current sources connected to the node, the value is zero. The q vector is N 1 in size with each element of the vector equal to the corresponding independent voltage source. If there is no independent voltage source, the value is zero THE PPP APPROACH In the power distribution network of a multilayer printed circuit board, the inductance formed by two parallel planes and IC/decoupling capacitor vias (Figure 2.2) can be separated into two parts: the vertical via barrel inductance and plane pair inductance due to the changes of the horizontal plane current distribution adjacent to the vias (Figure 2.3). IC Decoupling capacitors GND PWR Figure 2.2. Power/Ground plane pair with IC and decoupling capacitors.

26 12 k J IC k J Decoupling Capacitor Figure 2.3. Current distribution on power and ground planes. The power and ground planes are subdivided into commensurate cells using conventional PEEC meshing method [12] as shown in Figure 2.4. Non-orthogonal cells are avoided with rectangular mesh size, which makes coupling terms minimal. For example, Figure 2.4 shows a 4 4 plane subdivided into 16 squares with 1 1 size. The currents flowing on the plane are divided into the x and y directions. Thus, the plane is also subdivided into cells in the x and y directions, respectively. The width of the cells on the edges is half of the cells inside so that by connecting the nodes in Figure 2.4, the equivalent circuit using partial inductances can be created as shown in Figure 2.5. This allows the subdivided plane sections to be connected in a systematic way. The same subdivisions are applied for both power and ground planes to make them symmetric.

27 13 Iy Ix n j Ix m y x i Cells on the edge Figure 2.4. Plane subdivision Figure 2.5. Partial inductance evaluation.

28 D z D x D y 14 The closed-form formulation for mutual inductance between two parallel thin conductors as shown in Figure 2.6 is given in Eq. (16), which is called the thin tape tape (TT) algorithm [9]. z y w 2 l 2 2 l 1 1 w 1 x Figure 2.6. Two parallel thin conductors b - D a - D L (-1) [ a ln( a ) b ln( b ) i j j z i z p12 i i j j 4 ww 1 2 i1 j i j - ( bj - 2 Dz ai ) - bjdzai tan ] 6 Dz i j z ( a b D ) l1 l2 l1 l2 a1 Dx, a2 Dx l1 l2 l1 l2 a3 Dx, a4 Dx w1 w2 w1 w2 b1 Dy, b2 Dy w1 w2 w1 w2 b3 Dy, b4 Dy ab (16)

29 15 For power/ground plane pair with opposing currents, two cells located on the top and bottom planes with the same x and y coordinates can be united to a cell pair called section [12] as shown in Figure 2.7. Due to the cancelling effect of the opposing currents in a cell pair (Figure 2.8), the inductive coupling between sections decays much faster with increasing distance [13]. i + I i + + I j + j - -I i - i - -I j - j Figure 2.7. i-th and j-th section I i Lp ii Lp jj I j I i Lp i i' -I j Lp j j' Figure 2.8. The corresponding equivalent circuit of i-th and j-th section It has been shown that the mutual inductance between the i-th section and j-th section, Ls ij can be expressed with the partial-mutual inductances of the cells, in which symmetry of the cells is applied to reduce by a factor of two in the number of the partial inductance evaluations [12]. Briefly, the voltage drop in the i-th section caused by the current in the j-th section can be expressed as, Vsi si j ( Lpij Lpij ' Lpi ' j' Lpi ' j ). ( 17)

30 16 Because of the symmetry of the cells, we have Lp ij = Lp i j and Lp ij = Lp i j. The partial-mutual inductance between the i-th section and the j-th section can be expressed as, Vs Ls 2( Lp Lp ) i ij ij ij ' si j. (18) Similarly, the partial-self inductance of the i-th section can be expressed as, Lsii 2( Lpii Lpii '). (19) The orthogonal cells are used in the PPP approach, which reduces the coupling a lot since only the coupling in the x direction or the y direction will be calculated. Nonorthogonal mesh can result in the mutual coupling between the x and y directed cells which is costly in computation. A special case for the inductance of thin filamentary circuits i and j is given by the Neumann formula [9], Lp ij dli dl j 4. (20) i j r ij When the distance between two cells, r ij is sufficiently large, the partial-mutual inductance between two cells can be approximated as, Lp ij ll 4 r i j ij. (21)

31 17 Define q h r, where h is the plane to plane spacing, and r ij is the distance / ij between two sections. When the distance r ij between two sections >> the size of the sections, the partial-mutual inductance between the sections shown in Figure 2.7 can be approximated as, Ls 2( Lp Lp ) 0.2 xx(1/ r 1/ r ), H (22) ij ij ij ' ij ij ' where r r h r q. The square root can be expanded in a Taylor series as, ij ' ij ij q q q 2 8. (23) When q << 1, q 2 q. Eq. (22) can be expressed as, 2 Ls x xq r (24) ij / ij, μh where r i x j y 2 2 ij ( ) ( ) (Figure 2.4). For uniform mesh subdivision, the cell is square with x y, and Eq. (24) can be written as Eq. (25). Thus, the coupling between sections decays very fast, which is proportional to (1/ ) 2 r ij. Ls xq i j ij 0.1 /, μh (25) Applying the approximation formula can speed up calculation of the mutual inductance coupling between sections, which is related to the section length, distance between sections and the plane pair spacing only. The relative error of the mutual inductance between sections obtained by the original closed-form expression and the approximation formula is given by Eq. (26).

32 Mutual Inductance,pH 18 err Ls Ls ij ij( apprx) 100% (26) Ls ij To find out the criteria for the application of the approximation formula, the defined error was set as 3% to achieve enough accuracy. Different plane pair spacing was applied. Here we show an example of 0.5mm 0.5mm cell size and 0.2mm plane spacing. The partial-mutual inductance between two sections with various distances is calculated using the closed-form expression and the approximation formula, and the results are shown in Figure 2.9. The relative error calculated by Eq. (26) is shown in Figure Closed-form Approximation Section Distance,mm Figure 2.9. Partial-mutual inductance between two sections calculated by the closed-form formula and the approximated method.

33 Error, % Section Distance, mm Figure Relative error between the closed-form formula and approximation. The relative error criteria is set as 3 %. It can be seen that when the section distance is larger than 2.5mm, which is 5 times of the cell size, the relative error is already less than 3 %. Normalize the partial-mutual inductance between two sections to the partial-self inductance of the section, Ls / Ls as shown in Figure It is obviously that the ij ii partial-mutual inductance decays very fast. When the distance between two sections is 5mm, which is 10 times of the cell size, the coupling is already less than 10-4 of the partial-self inductance. Therefore, the coupling can be approximated as zero when the distance between two sections is large enough.

34 Normalized to partial-self inductance Section Distance,mm Figure Normalized to partial-self inductance. Vary the plane pair spacing from 0.1mm to 2mm. For each spacing value, the section length was changed from 0.1mm to 2mm, and the minimum section distance at which the relative error is no more than 3% was recorded as shown in Figure The minimum section distance to satisfy the relative error criteria requirement can be related to either section size or plane spacing, whichever is larger, by multiplying a factor. Here we use the section with 0.5mm plane pair spacing as an example. Table 2.1 shows the section size, and the corresponding minimum section distance at which the relative error is less than 3 %. If section size is smaller than the plane spacing, the minimum section distance is roughly 5 times of the plane spacing. If section size is larger than the plane spacing, similar relationship can be found between the minimum section distance and section size. When section size is equal to the plane spacing, the minimum section distance is only 2 times of section size or the plane spacing. However, we can still set the minimum section distance equal to 5 times of section size or plane spacing. We will show that this estimated relationship gives high enough accuracy later.

35 21 Table 2.1 Minimum section distance to satisfy 3 % err, plane spacing = 0.5 mm Section Size, mm Minimum Section Distance, mm It has been found that if the distance between sections is less than 5 times of the larger value of section length and plane spacing, called ds, the relative error is higher than 3 % and the closed-form expression needs to be applied to calculate the mutual inductance between two sections. If the distance between sections is larger than ds, the approximation formula can be applied with the relative error less than 3 %. If the distance between sections is larger than 2ds, the mutual inductance can be estimated as zero. Figure 2.13 shows the schematic of how to determine the calculation formulation for the mutual coupling. Applying the approximation criteria can speed up computations [12], which will be shown in an example later, and make the partial inductance matrix sparse due to the zero terms.

36 Section Distance, mm Section Size, mm Plane Spacing 0.1mm 0.2mm 0.5mm 1mm 2mm Figure Criteria to apply the approximation formula ds = max(section length, plane spacing) < 5ds > 10ds Section distance else Closed-form Approximation Zero Figure Schematic of criteria determination when err = 3%.

37 23 3. UNIFORM AND NON-UNIFORM MESH 3.1. ASSEMBLY OF MNA By stamping in the appropriate contribution circuit element in a conventional Modified Nodal Analysis (MNA) method, the circuit matrix can be set up to model the plane pair [12]. Briefly, the MNA matrix is composed by KVL, KCL and partial inductance matrices. By solving the matrix, the voltage at each node and the current in each branch can be obtained. Thus, all desired inductances like the inductance of the plane pair can be calculated. Figure 3.1 shows an example with the smallest structure. Subdividing the example with the conventional PEEC mesh (Figure 3.1 (a)), the corresponding partial inductance evaluation in x and y direction is shown in Figure 3.1 (b). Since the geometry shown here is subdivided with the least amount of mesh, the cells in both x and y directions are cells on the edge. It is worth to note that the currents we are talking here, Ix and Iy are differential currents as shown in Figure 2.8. Ix Iy (a) (b) Figure 3.1. Example with the smallest structure. (a) Mesh in x and y direction. (b) Partial inductance in x and y direction. The corresponding equivalent circuit for the example in Figure 3.1 is shown in Figure 3.2. Node 1 is defined as the current source with the current, Is injected into. Node 4 is defined as the short connected to ground, which is the datum node with the voltage of zero. The branch number and corresponding nodes at two ends are listed in Table 3.1.

38 Ix 2 Iy 1 Iy 2 Is 1 Ix 1 2 Figure 3.2. Equivalent circuit of the example with the smallest structure. Table 3.1 Branch number and corresponding nodes at the ends Branch No. Beginning Node End Node Table 3.2 Branch voltage Branch Voltage Node Voltage V N1 V N2 V N3 V N4 V V V V

39 25 According to Eq. (10), the voltage drop on the branch is determined by the voltage of the nodes at the ends as shown in Table 3.2. The incident matrix of voltage, V can be expressed as, V (27) Table 3.3 Node current Branch Current Ix 1 Ix 2 Iy 1 Iy 2 Node Node Node Node The current flowing through each node is calculated by KCL as shown in Table 3.3. Define the current flowing out of the node as + and the current flowing into the node as -. The incident matrix of current is, I (28)

40 26 Same as Eq. (11), we have I V T. The source current injected into node 1 and the short current at node 4 are not included in I, and they will be included in the final assembled MNA matrix. Since the cell is orthogonal, the coupling is only in x or y direction. The partial inductance matrix, L is expressed as, Lpx Lpx Lpx Lpx L Lpy Lpy Lpy Lpy (29) Assemble V, I and L with an all-zero 4 4 matrix to form A matrix as shown in Eq. (12). The circuit equation for the smallest structure is shown in Eq. (30). A column and a row are added into A matrix as the last column and row, which are used for the stamping of short current and voltage, respectively. Is in the right-hand-side of Eq. (30) represents the source current injected into node 1. By solving Eq. (30), the voltage of each node and the current on each branch can be obtained. Therefore, the impedance of the smallest structure is give by L / 11 V 1 sis. All other inductance like L 21, L 31 can also be calculated. N VN1 sis V N VN VN Lpx11 Lpx six Lpx21 Lpx sIx Lpy33 Lpy34 0 siy Lpy43 Lpy44 0sIy si sh 0 (30)

41 27 It is important that for much larger and more realistic geometry, the structure of the MNA matrix is similar as that in Eq. (30). The source current can be injected into any node(s) we want to calculate the inductance at, and the short(s) can be placed at any node(s) where the capacitors are located BOOKKEEPING OF NODES In the previous work, the port was represented with a single node in the model [12]. Here, we included the port dimension into the model to make it more general for the real case. Firstly, subdivide the plane to commensurate cells as shown in Figure 2.4, and label each node with a global number. The nodes in the corresponding port region are treated as one node. Then use bookkeeping to assign a local number for each node. An example is shown in Figure 3.3. Nodes with the global number of 1,2,5 and 6 form the port of short, and nodes with the global number of 11,12,15 and 16 form the port of source. Assign the local number of 1 to the nodes on the port of short and the local number of 2 to the nodes on the port of source. Then assign a local number to other nodes in sequence to build the node system. Table 3.4 shows the global number and the local number of each node Short Source 16 Figure 3.3. Bookkeeping of the nodes.

42 28 Table 3.4 Bookkeeping of the nodes Global Node No. Local Node No. Node Property 1 1 short 2 1 short short 6 1 short source 12 2 source source 16 2 source 3.3. COMPUTATION SPEED-UP. Although the approximated formulation is helpful to speed up computation, the model may still be time consuming since a huge number of partial-self and partial-mutual inductance need to be calculated if the plane size is large or the mesh is very dense. Due to the symmetry of the uniform mesh subdivision, we can only calculate the partial-self and partial-mutual inductance of one section, and the partial-self and partial-mutual inductance of other sections can be obtained directly from the results of the section we calculate. Figure 3.4 shows an example of the smallest circuit to calculate the partial-self and partial-mutual inductance in x direction.

43 29 Lp3 Lp4 y Lp1 Lp2 x Figure 3.4. Example for partial-self and partial-mutual inductance calculation. The partial-self inductance of section 1, Lp 11 and the partial-mutual inductance Lp 12, Lp 13 and Lpx 14 can be calculated using the formulations in Eq. (16) and Eq. (25). It s noticed that for section 2, we have Lp 21 =Lp 12, Lp 22 =Lp 11, Lp 23 =Lp 14 and Lp 24 =Lp 13. The partial-self and partial-mutual inductance of section 2 can be obtained from the results of section 1 by building a transfer matrix shown in Eq. (31). For more realistic case with many partial inductance components, the transfer matrix can be built with similar structure. Lp Lp Lp11 Lp12 Lp13 Lp 14 Lp Lp (31)

44 COMPUTE TIME ANALYSIS The total compute time to solve the MNA matrix is determined by the number of unknowns in Eq. (30), which are V Ni, Ix i and Iy i. To find the relationship between the number of unknowns and compute time, we can increase the problem size by keeping the same mesh size while increasing the geometry size. The plane size is changed from 20mm 20mm to 140mm 140mm with the plane spacing of 0.2mm while the mesh size is kept as 1mm 1mm. The total compute time, time for stamping MNA matrix and time for solving MNA matrix are recorded and listed in Table 3.5. It is obviously that the total compute time is determined by the time for stamping and solving MNA matrix, and most time is spent on stamping MNA matrix. Table 3.5 Compute time with different plane sizes Plane size, mm mm Unknowns Total Time, sec Stamp MNA, sec Solve MNA, sec Figure 3.5, Figure 3.6 and Figure 3.7 show the total compute time, time for stamping MNA matrix and time for solving MNA matrix vs. the number of unknowns,

45 Time for stamping MNA, sec Total Compute Time, sec 31 respectively. In all three figures, the exponential is around 1.5, which agrees with our expectation y = 1E-05x Unknowns Figure 3.5. Total compute time vs. unknowns y = 3E-06x Unknowns Figure 3.6. Time for stamping MNA matrix vs. unknowns

46 Time for Solving MNA, sec y = 4E-06x Unknowns Figure 3.7. Time for solving MNA matrix vs. unknowns 3.5. NUMERICAL EXPERIMENT Here we give the results for a plane pair with 20mm 20mm plane size and 0.8mm plane spacing as shown in Figure 3.8. The short center is located at (x=5mm, y=5mm), and the source center is located at (x=13mm, y=13mm). The port size for both short and source is 2mm 2mm. The mesh size is set as 0.5mm 0.5mm. The software of PowerPEEC from IBM [14] is used to validate the results. The calculated results are listed in Table 3.6. The results from PPP approach agree well with the result using PowerPEEC, and the relative error is less than 0.5 %.

47 33 y z 0.8mm 20mm x 20mm Figure 3.8. Test geometry Table 3.6 Calculation results with different methods Unknowns Inductance Time w/o Apporx ph 31.3 sec w/ Approx ph 7.5 sec PowerPEEC ph 85.4 sec The calculated plane pair inductance using the PPP approach matches well with PowerPEEC. The result obtained with the approximation criteria applied is very close to that calculated using closed-form expression, and err is less than 0.5 %. The total compute time with approximation applied is reduced to about a quarter of the total time using closed-form expression with losing the accuracy, which is very helpful when plane size is large.

48 50mm MULTIPLE CONTACTS In real PDN design, multiple decoupling capacitors are placed between power and ground plane (Figure 3.9). In PPP approach, these decoupling capacitors are represented using short vias. Here, we show an example with 10 shorts shown in Figure The plane pair is 50mm 50mm with the plane spacing of 0.2mm. The via size is 2mm 2mm, and mesh size is 1mm 1mm. The locations of the source and 10 shorts are shown in Figure GND PWR Figure 3.9. PWR/GND pair with multiple vias. Shorts (15,40) (20,40) (25,40) (30,40) (35,40) (15,30) (20,30) (25,30) (30,30) (35,30) (25,10) Source 50mm Figure Test geometry with 10 contacts.

49 35 The inductance of the plane pair structure shown in Figure 3.10 is calculated using the PPP approach and compared to PowerPEEC (Table 3.7). The PPP approach shows enough accuracy, and the relative error between two methods is only 2.4 %. Table 3.7 Plane pair inductance with 10 shorts Plane Pair Inductance Relative error PPP Approach PowerPEEC ph ph 2.4 % Next, we show that the PPP approach is very efficient taking multiple vias into account compared to other methods, like cavity model [8]. We use the test geometry shown in Figure 3.11 to test the compute time of PPP approach and the cavity model. The plane pair is 50mm 50mm with plane spacing 0.2mm. The source port is fixed at a location, and multiple shorts are spread on the board around the port. 50mm Source 50mm Figure Test geometry for multiple shorts

50 36 The number of increased unknowns due to the increasing of vias is a small portion compared to the total amount of unknowns in the MNA matrix, which determines the total computational time. For example, when the number of shorts is increased from 10 to 20, the number of unknowns increases 10 which is only 0.13 % of the total amount of unknowns (Table 3.8). Thus, the total compute time of the PPP approach will not increase much by increasing the number of shorts. Table 3.8 Multiple shorts Contact No. Unknowns Increased portion % As shown in Figure 3.12, for the same geometry, the running time for the PPP approach is almost linear to the contact number. However, the running time for cavity model is exponential to the contact number. It is apparently that the PPP approach is more efficient to handle the case with multiple contacts.

51 Time, sec Time, sec Contact Number (a) Contact Number (b) Figure Compute time comparison for multiple contacts. (a) PPP approach. (b) Cavity model.

52 NON-UNIFORM MESH Since the current distribution is concentrated near the port region, non-uniform mesh may be applied to reduce the size of MNA matrix and increase calculation speed. Sub-mesh is applied to the region near the ports. For the region away from the ports, sparse mesh is used (Figure 3.13 (a)). The zoom-in of the interface currents in both x and y directions is also shown in Figure 3.13 (b) and (c), respectively. i k m j n Iy Ix (a) i j i k n j A B C k m n k m n i j (b) (c) Figure Non-uniform mesh. (a) Sub-mesh near the port region. (b) Zoom-in of the interface in x direction. (c) Zoom-in of the interface in y direction.

53 39 The size of the dense mesh is set as half of the size of the sparse mesh (Figure 3.13). The incident matrix of the voltage is similar as that of the uniform mesh. The incident matrix of the current is changed due to the re-distribution of the current at the interface between sparse mesh region and sub-mesh region. To generate incident matrix of current, I for the interface, we assume that the current flows uniformly through the cell. Figure Transition between mesh density.

54 40 Figure 3.14 shows the equivalent circuit for the transition between mesh density as shown in Figure There are three types of nodes that are of importance for the transition between the two regions. Type I node is the corner node between the transition regions, i.e., node A in Figure 3.13 or node ([G 4, S 1 ]) in Figure Type II node is the nodes next to the corner nodes occur only in the reduced size mesh, i.e., node B in Figure 3.13 or node S 3 in Figure Type III node is different from the side node and there is a direct connection to the coarse mesh, i.e., node C in Figure 3.13 or node ([G 9, S 5 ]) in Figure Based on the ratio of the corresponding cross section length, the weighted KCL equations for the three types of nodes can be obtained. For node A, the cross section that current Ix k flows out is 75% of that current Ix i flows in. For node B, the cross section Ix m flows out is 25% of the cross sections Ix i and Ix j flows in. For node C, the cross section Ix n flows out is 50% of that Ix j flows in. All coarse-fine mesh nodes are handled same way. Eq. (32) shows the weighted KCL equations for the three types of nodes in the equivalent circuit shown in Figure Stamping the coefficients in Eq. (32) into to I generate a new weighted KCL matrix as shown in Table 3.9. Again, the current we talk about here is the differential current as shown in Figure 2.8. Type I Node: 0.75I I I 0.75I 0 G,23 S,1 S,2 G,3 Type II Node: 0.25I 0.25I I I I 0 G,23 G,25 S,4 S,5 S,2 (32) Type III Node: 0.5I I I I 0 G,25 S,7 S,8 S,5 Table 3.9 Weighted KCL matrix I G,23 I G,25 I S,1 I S,4 I S,7 I G,3 I S,2 I S,5 I S,8 [G 4, S 1 ] S [G 9, S 5 ]

55 NUMERICAL EXPERIMENT FOR NON-UNIFORM MESH A test geometry of 20mm 20mm plane size with 0.2mm plane pair distance is used to check the performance of the non-uniform mesh approach. The source center is located at (14.5mm, 14.5mm), and the short center is located at (5.5mm, 5.5mm). The via size is 1mm 1mm. Two uniform mesh sizes, 1mm and 0.5mm, are applied in uniform mesh method, respectively. For non-uniform mesh approach, the sub-mesh size is 0.5mm and the sparse mesh size is 1mm. The convergence of the sub-mesh method is tested by increasing the sub-mesh area around the source via and short via as shown in Figure (a) (b) (c) Figure Sub-mesh around the vias.

56 42 The inductance obtained using both uniform mesh and sub-mesh methods are shown in Table The sub-mesh method shows enough accuracy compared to the uniform mesh method. The amount of unknowns of sub-mesh method is much less than the unknowns of uniform mesh approach without losing the accuracy, which leads to much smaller MNA matrix size and benefits total compute time. By increasing the area of sub-mesh region, the result is convergent. Table 3.10 Inductance calculated using uniform mesh and sub-mesh methods Uniform Mesh Size Sub-mesh Size 0.5mm 1mm 0.5mm Sub-mesh area 3mm 3mm 5mm 5mm 7mm 7mm Unknowns Inductance ph ph ph ph ph 3.9. CLOSE VIAS When the vias are very close, we can use only one sub-mesh region to cover all the vias (Figure 3.16), so that there are enough meshes between the vias to increase the accuracy. Figure Close vias covered by one sub-mesh region.

57 43 Figure Define the sub-mesh region around the vias. Define X mx and Y n y, where X and Y are the distance between two vias in x and y direction, respectively, and x and y are the uniform cell length in x and y direction, respectively. Usually we have x = y. The sub-mesh area for close vias is defined as (m + k)(n + k) x y, k = 2, 4, 6, (Figure 3.17) DETERMINE SUB-MESH REGION To apply sub-mesh method, we need to know how large the sub-mesh region we should use. Figure 3.18 shows the current distribution on the plane where uniform mesh is applied. It is clearly that the current distribution is concentrated in the region close to the source via and short via in both x and y directions. The current decays very fast in the region away from the vias. From Figure 3.18, it can be seen that most of the current in x direction is concentrated within 6 uniform cells around the via, 3 cells on the left side and 3 cells on the right side (Figure 3.18 (a)). Same phenomena can be observed for the current distribution in y direction. Since the decay of the coupling between the sections is proportional to 2 1/r from Eq. (25). For the 4 th section away from the via, the coupling to the via decays to 1/16 of the coupling between the via and the 1 st section next to the via.

58 44 Thus, the area of the sub-mesh region should be 6 x 6 y, which will give enough accuracy. 20 Current Distribution (x direction) (a) 20 Current Distribution (y direction) (b) Figure Current distribution on the plane. (a) x direction; (b) y direction.

59 VALIDATION OF SUB-MESH METHOD A test geometry in reference [8] is used for the inductance calculation with submesh method and changing several geometrical factors is shown in Figure 3.19 (a). The square parallel planes with the size of 50mm 50mm and two rectangular vias with the size of 0.5mm 0.5mm are shown in Figure Two values for the spacing between two planes, d, 0.2mm and 1mm, are tested. Two values for the spacing between two vias, l, 1.5mm and 25.5mm are tested as two extreme cases. The locations of two vias are symmetrical along the y-axis in the test geometry, i.e., (25, 25-l/2) mm and (25, 25+l/2) mm. The calculated plane net inductances (Table 3.11) are compared to the values obtained using hybrid method and PEEC solver (PowerPEEC) in reference [8]. The comparison in Table 3.11 shows that the results obtained using PPP approach agrees with hybrid method and PowerPEEC. Figure Test geometry for the inductance calculation [8]. (a) Variables are spacing between two vias, l, and separation between two planes, d. (b) Port condition.

60 46 Table 3.11 Plane net inductances from the hybrid, PEEC solver and PPP methods d (mm) L planei l (mm) Hybrid [8] (ph) PEEC PPP Diff. to Hybrid Diff. to PEEC Solver Solver [8] Approach % 1.8 % % 10.9 % % 2.5 % % 2.4 % CURRENT DISTRIBUTION ANALYSIS The current flowing on each branch can be calculated from MNA matrix. Here we use the geometry shown in Figure 3.19 as the example. The plane spacing, d is set as 1mm, and the via distance, l is set as 1.5mm and 25.5mm, respectively Current Distribution (x direction) Current Distribution (x direction) (a) 21 (b) Figure Current distribution in x direction on the plane with d = 1mm and l = 1.5 mm. (a) Total current distribution in x direction. (b) Current vector in x direction at the source and short.

61 47 50 Current Distribution (y direction) Current Distribution (y direction) (a) 22 (b) Figure Current distribution in y direction on the plane with d = 1mm and l = 1.5 mm. (a) Total current distribution in y direction. (b) Current vector in y direction at the source and short Figure Zoom-in of current vector at source and short on the plane with d = 1mm and l = 1.5 mm.

62 Current Distribution (x direction) (a) Current Distribution (x direction) Current Distribution (x direction) (b) (c) Figure Current distribution in x direction on the plane with d = 1mm and l = 25.5 mm. (a) Total current distribution in x direction. (b) Current vector in x direction at the source port. (c) Current vector in x direction at the short.

63 49 50 Current Distribution (y direction) (a) 44 Current Distribution (y direction) Current Distribution (y direction) (b) (c) Figure Current distribution in y direction on the plane with d = 1mm and l = 25.5 mm. (a) Total current distribution in y direction. (b) Current vector in y direction at the source. (c) Current vector in y direction at the short.

64 (a) (b) (c) Figure Current vector on the plane with d = 1mm and l = 25.5 mm. (a) Zoom-in of the current vector between source and short. (b) Current vector at the source port. (c) Current vector at the short.

65 51 The current distribution is plotted in x and y direction separately, and current vector is also plotted to show the direction that current flows to. For both close via (Figure Figure 3.22) and far via (Figure Figure 3.25) examples, the current vector clearly shows that the current flows out of the source and flows into the short. The current density is high in the region near the source and short, and low in the region far away from the source and short EFFICIENCY OF SUB-MESH METHOD We use a larger plane pair with 100mm 100mm plane size and 0.2mm plane spacing as the test geometry. The short center is located at (x = 20.5mm, y = 20.5mm), and the source center is located at (x = 50.5mm, y = 50.5mm). The port size for both short and source is 1mm 1mm. For the sub-mesh method, the area of the sub-mesh region is 3mm 3mm with 0.5mm sub-mesh size, and the sparse mesh size is 1mm. For the uniform mesh method, the mesh size is 0.5mm. The comparison between two approaches is shown in Table Table 3.12 Comparison between sub- and uniform mesh methods Unknowns Inductance Time Sub-mesh ph 87 sec Uni-mesh ph 6384 sec With the sub-mesh method, the number of unknowns is significantly reduced, resulting much less running time, and the result is very close to that obtained using uniform mesh approach (difference < 0.2%). The sub-mesh approach is also memory usage saving due to the much smaller size of the MNA matrix compared to uniform mesh approach. It s worth to note that all results are from the Matlab program which is slower than C++.

66 VIA INDUCTANCE The side walls of a via can be represented using 4 zero-thickness metal sheets shown in Figure The partial inductance of the parallel sheets can be calculated using Eq. (16), and the partial inductance of the orthogonal sheets as shown in Figure 3.27 is given as Eq. (33) [15]. d Figure Via constructed with 4 metal sheets. ze 2 z xe 2 2 xs 2 zs 2 xe 1 xs 1 y 2 ys 1 ye 1 1 y z 1 x Figure Zero thickness conductors at 90 deg angle.

67 53 1 a c L (-1) [( ) c ln( b ) lmk 1 k l p12 l m 4 ( ye1 ys1 )( ze2 zs2) k 1 m1 l a b b c a b c +( ) ln( )+ ln( ) tan k m m l k -1 m l bm cl akbmcl ak ak 2 2 bmak -1 akcl akcl -1 akbm tan tan ] 2 b 2 c a xs xe, a xe xe m a xe xs, a xs xs b y ys, b y ye c ze z, c zs z ze zs Z z1, ak bm Z l (33) Figure 3.28 shows the current flows through source via and short via, respectively. The height of via, d, and the distance between the vias, l, are chosen as the values listed in Table For example, with d = 0.2 mm and l = 1.5 mm, the partial inductances of the sheets of source via are calculated and listed in Table Figure Source via and short via

68 54 Table 3.13 Partial inductance of the source via, ph, d = 0.2 mm, l = 1.5 mm Lp11 Lp12 Lp15 Lp16 Lp13 Lp14 Lp17 Lp18 Lp Lp22 Lp21 Lp25 Lp26 Lp23 Lp24 Lp27 Lp28 Lp Lp33 Lp34 Lp37 Lp38 Lp31 Lp32 Lp35 Lp36 Lp Lp44 Lp43 Lp47 Lp48 Lp41 Lp42 Lp45 Lp46 Lp The partial inductance of sheet 1 is calculated using Eq. (34), and the partial inductances of other sheets can be calculated using the similar formula. Lp1 Lp11 Lp12 Lp13 Lp14 Lp15 Lp16 Lp17 Lp18 (34) The partial inductance of the via is obtained using Eq. (35). The total inductance of the plane pair is obtained by adding the partial inductances of the plane and via together as shown in Table Lpvia Lp1 Lp2 Lp3 Lp4 (35) Comparing to the partial inductance of via and total inductance obtained using other methods [8], the PPP approach shows agreement with hybrid method and PEEC solver. When via length is long, i.e., 1 mm, and vias are close, i.e., 1.5 mm, some difference is found between the values of via inductance obtained using closed-form expression (Eq. (33)) and other two methods. Eq. (35) shows that the 4 sheets on the via sides are connected in parallel. Thus, the top and bottom of the via are shorted in this method and the current is assumed to flow uniformly on the sheet, which causes the difference compared to other methods.

69 55 Table 3.14 Comparison of partial inductance of via and total inductance d, mm l, mm PPP Approach L via i [8] L total [8] L plane i L via i L total Hybrid PEEC solver Hybrid PEEC solver PLANE INDUCTANCE WITH DIFFERENT SHORT LOCATIONS The plane inductance changes when the decoupling capacitor is placed at different locations on the board. When the decoupling capacitor is placed at different locations on the whole board, the entire information of the board inductance can be easily obtained by applying the PPP approach, which is helpful in PDN design. Figure 3.29 shows the geometry for board inductance test. The plane size is 50 mm 50 mm with the spacing of 0.2 mm. The via size is 0.5 mm 0.5 mm. The source current is fed at the center of the plane and at a corner of the plane, respectively. The short via is placed around the source from as close as 1 mm to the edge of the board. 0.5 mm short short 50 mm source (25, 25) 50 mm source (5, 5) 50 mm 50 mm Figure Geometry for board inductance test. (a) Source fed at center. (b) Source fed at a corner.

70 mm ph mm mm Figure D plot for inductance with the source fed at center and the short placed at different locations on the board mm Figure D plot for inductance (ph) with the source fed at center and the short placed at different locations on the board.

71 mm ph mm mm Figure D plot for inductance (ph) with the source fed at corner and the short placed at different locations on the board mm Figure D plot for inductance (ph) with the source fed at corner and the short placed at different locations on the board.

72 58 Figure 3.30 and Figure 3.31 show the plane inductances with the source fed at center and the short at different locations plotted in 3D and 2D, respectively. Figure 3.32 and Figure 3.33 show the plane inductances with the source fed at a corner plotted in 3D and 2D, respectively. The plane inductance increases with increasing distance between the source and short. The largest inductances occur when short is at the corners of the board. When the source location is fixed, the plane inductance at any location on the board can be easily obtained from the plotted inductance figure. In PDN design, the information of inductance is helpful for designer to determine where to place the decoupling capacitor on the board APPLICATION IN PDN DESIGN The PPP approach can be applied in PDN design to determine the portion of the inductance in plane. However, we need to consider the limitation of memory usage and simulation time. The capability of the code performance is tested on the computer with 32 GB memory and 2 processors (Intel(R) Xeon(R) CPU 3.00 GHz 2.99GHz). The largest plane size that can be handled is found to be 150 mm 150 mm when sub-mesh method is applied with 1mm uniform cell size. The total simulation time to get the inductance value is 1400 sec, and peak memory usage is 99 % (Table 3.15). If plane size is larger, it s not efficient in either simulation time or memory usage to apply the PPP approach. Table 3.15 Code performance for large geometry Plane Size Unknowns Memory Usage Time 150mm 150 mm GB 1400 sec The inductance of a pair of PWR/GND planes can be separated as the via partial inductance and plane partial inductance as shown in Table When the plane pair spacing is small, i.e., 0.2 mm, the plane partial inductance is more dominant than the via partial inductance no matter two vias are close or far. Both plane partial inductance and

73 59 via partial inductance increase with increasing plane pair spacing, i.e., 1mm. However, the via partial inductance is more dominant than plane partial inductance when plane pair spacing is large and two vias are close. The plane partial inductance increases as the distance between two vias increasing. If the distance between two vias is sufficiently large, the plane partial inductance is less affected with an additional increase of the distance between two vias. The above observation gives the proper limitation to apply the PPP approach, and also gives insights and design guide lines in PDN design for the placement of vias in PWR/GND planes.

74 60 4. CONCLUSION An accurate and efficient approach to fast calculate the plane pair inductance is proposed base on the PPP approach. The approximation criterion is studied to speed up calculation without loss of the accuracy. Compute time analysis shows that most time is spent on stamping MNA matrix and solving it. The total compute time is proportional to the number of unknowns with the exponential of 1.5. Compared to cavity model, the PPP approach shows much higher efficiency to calculate plane inductance when multiple contacts exist. Non-uniform mesh method is studied to reduce the size of MNA matrix. The minimum area of sub-mesh region to get enough accuracy is investigated. By plotting the current vector on the plane, it can be clearly seen that the current flows out of the source and flows into the short. With applying sub-mesh near the via region, the calculation is much faster and memory usage saving with enough accuracy.

75 61 BIBLIOGRAPHY [1] K-J. Song, J. Kim, J. Yoo, W. Nah, J. Lee and H. Sim, Low Power Noise Multilayer PCB with Discrete Decoupling Capacitor Inside, 10 th Electronics Packaging Technology Conference (EPTC), Singapore, [2] J. Kim, M. D. Rotaru, S. Baek, J. Park, M. K. Iyer and J. Kim, Analysis of Noise Coupling from a Power Distribution Network to Signal Traces in High-speed Multilayer Printed Circuit Boards, IEEE Trans. Electromagn. Compat., vol. 48, no. 2, pp , May [3] L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc and T. Roy, Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology, IEEE Trans. Adv. Packag., vol. 22, no. 3, pp , Aug [4] I. Erdin and M. Nakhla, Mixed Circuit/Electromagnetic Analysis of Field Coupling to High Speed Interconnects in Inhomogeneous Medium, Proc. IEEE Int. Symp. Electromagn. Compat., vol. 1, pp , Aug [5] M. Feliziani and F. Maradei, Circuit-Oriented FEM: Solution of Circuit-Field Coupled Problems by Circuit Equations, IEEE Trans. Magn., vol. 38, no. 2, pp , Mar [6] E. Liu, X. Wei, Z. Z. Oo, E. Li and L. Li, Modeling of Advanced Multilayered Packages with Multiple Vias and Finite Ground Planes, Electrical Performance of Electronic Packaging (EPEP), Atlanta, GA, [7] C. Christopoulos, The Transmission-Line Modeling Method: TLM, Piscataway, NJ: IEEE Press, [8] J-G. Kim, J. Fan, A. E. Ruehli, J-H. Kim, J. L. Drewniak, Inductance Calculation for Plane-Pair Area Fills with Vias in a Power Distribution Network Using a Cavity Model and Partial Inductances, IEEE Trans. Microw. Theory Tech., vol. 59, no. 8, Aug [9] A. E. Ruehli, Inductance Calculations in a Complex Integrated Circuit Environment, IBM J. RES.DEVELOP., Vol. 16, no.5, pp , Sep [10] A. E. Ruehli, Equivalent Circuit Models for Three Dimensional Multiconductor Systems, IEEE Trans. on Microwave Theory and Tech., vol. 22, no. 3, pp , Mar [11] B. Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Prentice Hall PTR, 2001.

76 62 [12] F. Zhou, A. E. Ruehli, J. Fan, Efficient Mid-Frequency Plane Inductance Computation, in Proc. of the IEEE Int. Symp. on Electromagnetic Compatibility, Fort Lauderdale, FL, [13] A. E. Ruehli, C. Paul and J. Garrett, Inductance Calculations Using Partial Inductances and Macromodels, in Proc. Of the IEEE Int. Symp. On Electromagnetic Compatibility, Atlanta, GA, [14] PowerPEEC, provided by IBM, Raleigh, NC. [15] A. E. Ruehli, P. A. Brennan, Efficient Capacitance Calculations for Three- Dimensional Multiconductor Systems, IEEE Trans. on Microwave Theory and Tech, vol. MTT-21, no. 2, pp 76 82, Feb

77 63 II MEASUREMENT OF MULTIPLE SWITCHING CURRENT COMPONENTS THROUGH A BULK DECOUPLING CAPACITOR Liang Li #1, Jingook Kim #2, Hanfeng Wang #3, Songping Wu #4, Yuzo Takita *5, Hayato Takeuchi *6, Kenji Araki *7, Jun Fan #8 # Missouri University of Science and Technology, Rolla, MO, 65401, USA * Sony Corporation 1-7-1Konan, Minato-ku, Tokyo, , Japan 1 llh9b@mail.mst.edu, 5 Yuzou.Takita@jp.sony.com, 7 kenji.araki@jp.sony.com, 8 jfan@mst.edu ABSTRACT This paper presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post data-processing procedure is introduced to separate and obtain the parameters of multiple current components. The results obtained by the proposed method are validated with other approaches.

78 64 1. INTRODUCTION Modern digital integrated circuits (ICs) can operate at an internal clock frequency of more than several GHz and consume a current of up to tens of amperes. A large portion of the total current is time-varying, which inevitably generates voltage fluctuations in the power distribution network (PDN) [1][2][3]. With faster switching speed, higher circuit density, lower supply voltages and smaller feature size in IC design, the voltage fluctuations become a serious issue, affecting power and signal integrity (PI & SI) as well as causing electromagnetic interference (EMI) problems [4], [5]. To counter the effect of the PDN noise, decoupling capacitors can be added near the ICs [6][7][8], which act as local sources of charge for switching circuits and reduce the voltage fluctuations in the PDN. Other solutions may include the usage of a thin power/ground plane pair, multiple vias for decoupling capacitor connections, etc., to decrease the impedance of the PDN. An optimal design for power integrity highly depends on the accurate model of the PDN and the knowledge of the switching current drawn from the PDN by ICs. For most printed circuit board (PCB) designers, the switching current information is usually unavailable. This makes measurement techniques more attractive for practical power integrity designs. In consumer electronic products, usually power traces are used for supplying voltage. In this case, the switching current of an IC can be approximately obtained by measuring the current flowing through the decoupling capacitors placed adjacent to the IC [9]. However, in some real-world hardware measurements, it is found that multiple current components could exist in the time-varying current flowing through a decoupling capacitor. This challenging issue of measuring multiple current components was not addressed in [9]. In this paper, a post data-processing procedure is developed to separate the effects of different current components, and to obtain the parameters important for power integrity studies. Further, when the current through a bulk decoupling capacitor is of interest, it needs to be measured at the frequencies as low as a few hundred KHz. Usually simple loop probes do not work well when frequency is below a few tens of MHz, due to their poor sensitivity. Typical commercial low-frequency current probe uses the Rogowski coil

79 65 structure, and the current under measurement needs to flow through the probe. In other words, to measure the current through a decoupling capacitor, a wire needs to be added in series with the decoupling capacitor and the wire has to go through the probe. The added wire can introduce unwanted parasitic inductance. Furthermore, in compact consumer electronic products, components on PCB are typically very dense. In some cases, it is very difficult to modify the PCB and add the required wire for current measurement using a Rogowski-coil current probe. In this paper, a lab-made low-cost current probe is developed to deal with these difficulties. The simple probe is very small in size, suitable for dense-pcb applications. In addition, it is sensitive enough for low-frequency measurements, and it does not require any modifications in PCB.

80 66 2. PROPOSED CURRENT PROBE The time-varying current through a bulk decoupling capacitor has frequency components usually ranging from a few hundred KHz to a few MHz. As mentioned earlier, a simple loop probe does not have enough sensitivity at these low frequencies with a small size. In this paper, a current probe is proposed based on a surface mount common-mode choke. Although the size is very small, the ferrite core in the choke can significantly increase the sensitivity of the proposed probe. As shown in Figure 2.1, the common-mode choke has a bottom ferrite shield and two sets of copper-wire coils at opposite directions. To modify the choke to a loop probe, the bottom ferrite shield needs to be removed and only one coil needs to be used, as sketched in Figure 2.1. Figure 2.1. Structure of the proposed low-cost probe. To calibrate the lab-made low-frequency probe for bulk-capacitor current measurement, it was first characterized using the experimental setup as shown in Figure 2.2. A bulk capacitor with the same package size as the one used in the real product was soldered in a 50 ohm trace. One end of the 50 ohm trace was connected to port 1 of a network analyzer and the other end was terminated with a 50 ohm load. The current probe was placed above the bulk capacitor with the coil perpendicular to the direction of

81 67 the current flow. Port 2 of the network analyzer was connected to the probe output, and the S 21 parameter was measured. The equivalent circuit of this measurement setup is shown in Figure 2.3. From the S 21 measurement, the transfer coefficient between the induced voltage at the probe output and the current flowing through the bulk capacitor can be calculated. As shown in Figure 2.4, this transfer coefficient can be well characterized using a mutual inductance of 12.5 nh in the frequency range from 100 KHz to 10 MHz. Figure 2.2. Measurement setup for current probe calibration. Figure 2.3. Equivalent circuit of the measurement setup shown in Figure 2.2.

82 Amplitude [db] New probe measurement data 12.5nH approximation Frequency [Hz] Figure 2.4. Transfer coefficient of the lab-made current probe for a specific bulk capacitor package.

83 69 3. SEPARATION AND CHARACTERIZATION OF MULTIPLE CURRENT COMPONENTS When using the lab-made current probe to measure the time-varying current flowing through the bulk decoupling capacitor, the current can be obtained from the measured voltage at the probe output as Eq. (1), I 1 Vdt (1) M where M is the mutual inductance obtained in Figure 2.4, and V is the induced voltage in the probe as a function of time that can be measured using an oscilloscope. In this paper, as shown in Figure 3.1 the current flowing through a 10 F bulk decoupling capacitor in a functioning hardware of a real electronic device was measured using the lab-made current probe. The bulk decoupling capacitor has the same package size as the one used in the calibration and the mutual inductance was found to be 12.5 nh. Oscilloscope IC Current probe Bulk capacitor Figure 3.1. Experimental setup of the bulk capacitor current measurement using the labmade current probe. The voltage induced in the current probe and the current calculated from Eq. (1) are shown in Figure 3.2 (a) and (b), respectively. It is found that the peaks in Figure 3.2 (a) have a pulse width of approximately 50 ns. On the other hand, the higher peaks in Figure 3.2 (b) have a transition time of approximately 1 s. The current pulses with a 50 ns transition time can also be observed in Figure 3.2 (b), but with lower magnitudes. In

84 Current (by integ ration) [ma] Current (by integ ration) [ma] mv mv 70 other words, there are two current components, with the transition times of 50 ns and 1 s, respectively. The fast component results in the induced voltage peaks due to the inductive nature of the current probe, even though its magnitude is lower usec usec (a) Time [us] Time [us] (b) Figure 3.2. Induced voltage and corresponding current. (a) Measured induced voltage in the current probe; (b) Current calculated from Eq. (1).

85 mv mv 71 It is very difficult, if not impossible, to extract the accurate information about the multiple current components directly from Figure 3.2 (b), although the information of the current component that contributes to the induced voltage peak (50 ns in this case) can be obtained relatively easily. The highest peak in Figure 3.2 (a) can be triggered, and multiple measurements can be performed. Then, by averaging the multiple measured results, a clear voltage waveform can be obtained as shown in Figure 3.3. In this waveform, only the portion related to the 50 ns current component exists. Random noise and other current components that are not synchronized are mostly eliminated through this procedure. Unfortunately, only one current component can be measured using this method usec ns usec Figure 3.3. Measured current component that results in the induced voltage peaks using the triggered averaging technique. In this paper, a post data-processing procedure is developed to separate the different current components from the induced voltage measurement in Figure 3.2 (a). First of all, as shown in Figure 3.4, a digital signal processing (DSP) low-pass filter with

86 72 a cut-off frequency of 5 MHz is applied to the induced voltage data to obtain the portion due to the slower current component. Secondly, subtract the portion due to the slower current component from the original induced voltage data to get the remaining portion due to the faster current component. Then, the current waveform for each component is calculated by integrating the corresponding voltage waveform as in Eq. (1). The procedure is performed for multiple measurements. Finally, using the previously mentioned triggered-averaging technique, a clear waveform for each current component is obtained with random noise eliminated. Through this procedure, different current components are thus separated, and their peaks as well as transition times are accurately measured. Induced voltage DSP Current waveform of each component Integration Induced current for each component from one measurement Average multiple measurements Current waveforms with random noise eliminated Figure 3.4. The proposed post data-processing procedure. An example of applying the proposed post data-processing procedure is shown in Figure 3.5, where two current components are separated and their corresponding current waveforms are obtained. Then the highest peak in each waveform is identified and triggered. This same procedure is performed for multiple measurements, and then multiple current waveforms for each current component are shifted according to the triggered peak and averaged. The final results for the slower and faster components are shown in Figure 3.6 (a) and (b), respectively. The peak current and transition time values can be further obtained from Figure 3.6. The slower and faster current components have the peak values of 250 ma and 140 ma, respectively. Their corresponding transition time values are 0.7 s and 40 ns. The parameters for the faster current component are approximately close to those calculated from Figure 3.3 (114 ma and 50 ns).

87 ma ma mv mv ma ma mv mv Raw data 6 Slow component usec trigger usec DSP: low pass filter Zoom (a) usec Integration usec 30 Raw data 30 Fast component Subtract slow component trigger usec usec Integration Zoom usec (b) usec Figure 3.5. Post data processing to obtain the highest peak for current components with slow (a) and fast (b) transient time.

88 ma ma 74 The parameters of the slower current component were validated using a commercial current probe, Tektronix CT-2, with a transfer coefficient of 1mV/1mA. Because this probe has a flat frequency response in its working band, the peak induced voltage in this probe is due to the slower current component since it has a higher magnitude. Then, using the same triggered-averaging technique, the peak current and transition time for the slower component were found to be 225 ma and 0.9 s, respectively, which again are very close to the results obtained from the proposed dataprocessing procedure with the lab-made current probe (a) (b) Figure 3.6. Averaged current waveforms for (a) slower and (b) faster current components when the bulk capacitor value is 10 F.

89 75 4. CONCLUSION In PDN design, IC switching current needs to be accurately characterized for power integrity studies. A lab-made low-cost current probe is proposed and fabricated from an off-the-shelf surface mount common-mode choke. It is very small in size, suitable for dense PCB applications. The frequency range of the developed current probe is from 100 KHz to 10 MHz. In addition, a post data-processing procedure is proposed to separate multiple current components that may exist in the switching current. This procedure relies on a low-pass DSP filter to separate the slower current component from the faster one. Triggering and averaging are also used to eliminate random noise for better measurements. The proposed procedure is validated with other measurement methods that require multiple current probes, demonstrating its effectiveness and efficiency in bulk-capacitor current measurements.

90 76 BIBLIOGRAPHY [1] M. D. Pant, P. Pant and D.S. Wills, On-chip decoupling capacitor optimization using architectural level prediction, IEEE Transactions on very large scale integration (VLSI) systems, vol. 10, no. 3, pp , June [2] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, [3] Y. S. Chang, S. K. Gupa, and M. A. Breuer, Analysis of ground bounce in deep sub-micron circuits, in Proc. VLSI Test Symp., 1997, pp [4] L. D. Smith, R.E. Anderson, D. W. Forehand, etc, Power distribution system design methodology and capacitor selection for modern CMOS technology, IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp , Aug [5] V. Tiwari, D. Singh, S. Rajagopal, G. Mehta, R. Patel and F. Baez, Reducing power in high-performance microprocessors, in Proc. Design Automation Conf., June 1998, pp [6] G. A. Katopis, Delta-I noise specification for a high-performance computing machine, IEEE Proc., vol. 73. no. 9, pp , Sept [7] R. Senthinathan and J. L. Prince, Simultaneous Switching Noise of COMS Devices and Systems. Boston, MA: Kluwer, [8] Microelectronics Packaging Handbook, 2 nd ed., vol. I, Chapman & Hall, London, U.K, [9] J. Kim, S. Wu, H. Wang, Y. Takita, H. Takeuchi, K. Araki, G. Feng, and J. Fan, Improved Target Impedance and IC Transient Current Measurement for Power Distribution Network Design, in Proc. of 2010 IEEE International Symposium on Electromagnetic Compatibility, pp , July 2010.

91 77 III SWITCHING CURRENT MEASUREMENT FOR MULTIPLE ICs SHARING A COMMON POWER ISLAND STRUCTURE Liang Li #1, Chulsoon Hwang &2, Tao Wang #3, Yuzo Takita *4, Hayato Takeuchi *5, Kenji Araki *6, and Jun Fan #7 # Missouri University of Science and Technology, Rolla, MO, 65401, USA & Korea Advanced Institute of Science and Technology, , Republic of Korea * Sony Corporation 1-7-1Konan, Minato-ku, Tokyo, , Japan 1 llh9b@mst.edu, 4 Yuzou.Takita@jp.sony.com, 6 kenji.araki@jp.sony.com, 7 jfan@mst.edu ABSTRACT Switching currents in active integrated circuits (ICs) generate noise in the power distribution network (PDN), which is one of the main sources for many signal/power integrity and electromagnetic interference issues in high-speed electronic devices. Accurate knowledge of the switching currents is the key to ensure a good PDN design. This paper proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure. Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island. Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated. The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage.

92 78 1. INTRODUCTION Modern high-speed digital systems have an increased number of integrated circuits (ICs) in printed circuit board (PCB). They could operate at an internal clock frequency up to several GHz and draw a large amount of switching current with a fast di/dt ramping rate from the power distribution network (PDN) of the board. When multiple logic gates in ICs switch simultaneously, they induce a voltage drop in the PDN. This momentary voltage drop, when seen by the active circuits in an IC, could affect the normal operations of the IC. Further, the voltage disturbance can easily propagate in the PDN, resulting in various noise coupling and interference issues. As the ultimate source of the PDN noise, switching currents in active devices are a key factor in PDN design. Without the accurate information, meaningful design criterions such as target impedance cannot be well defined. Further, analysis and comodeling of signal/power integrity and interference issues become inadequate without the exact information of the potential noise sources. When detailed IC information is available, chip-level modeling has proven to be an effective way to obtain the switching current information [1], [2]. Unfortunately, IC information is proprietary and usually unavailable for most PCB designers. Measurement-based methods thus are desirable in this case for practical engineering applications. Switching currents can be directly measured using the zero-ohm method [3], using a magnetic loop probe [4], [5], or a giant magneto-impedance (GMI) probe [6]. These direct methods can only measure the current of a single power or ground pin of the IC under study. Alternatively, switching currents can be obtained indirectly, such as based on near-field scanning [7], or by examining the silicon function status of the IC [8]. The indirect methods are usually complicated and still require a certain amount of IC information. In this paper, a measurement-based method is developed to handle the situation where multiple ICs share a common power island and IC information is not available. Since many power pins are connected to the same power net and the ball grid array (BGA) type package does not allow access to most of these pins, direct current measurement for individual pins is impossible. However, an equivalent total switching current of each IC, instead of the exact pin currents, can still be obtained, which could effectively provide the necessary information for PDN design in the PCB level.

93 79 This work is an extension of the approach reported in [9] and [10], where the equivalent switching currents (magnitudes only) of a Field Programmable Gate Array (FPGA) associated with both the core and I/O PDNs were obtained through S-parameter and spectrum analyzer measurements. The lack of the phase information in the obtained equivalent switching currents, due to the spectrum analyzer limitation, could result in issues for optimized PDN (such as target impedance) design [4]. To address the phase issue, time-domain oscilloscope measurements are used in this work. The measured timedomain noise-voltage waveforms are then converted into the frequency domain through the Fourier transform. Together with the S-parameter measurement of the multi-port power-island structure, equivalent switching currents including both magnitude and phase are obtained.

94 80 2. THEORY AND MEASUREMENT SETUPS According to the statistical study in [11], the total effect of multiple switching currents of an IC can be equivalently described by a single switching current located at the center of the IC footprint with acceptable accuracy, if frequency is small enough such that d/λ < 0.2, where d is the diagonal dimension of the IC package and λ is the corresponding wavelength in the PCB dielectric media. In this work, the frequency range of interest is 10 MHz to 1 GHz, which satisfies the condition. In other words, for the multiple ICs connected to the same power island structure, a single equivalent switching current can be used to describe the behavior of each IC and the current is located somewhere close to the center of the IC Figure 2.1. A picture of the functioning board under study: three ICs sharing a common power island structure. A portion of the functioning PCB under study is shown in Figure 2.1, where three ICs are connected to a 1.5 V power island. The corresponding board with the ICs removed is shown in Figure 2.2. Ports 1-3 between the 1.5 V power island and the ground plane were selected for ICs 1-3, respectively, located near the centers of their footprints. Port 4 was selected at a location relatively far away from all the ICs, again between the 1.5 V power island and the ground. The fourth port is used for the validation of the proposed methodology.

95 (a) (b) Figure 2.2. Same board with (a) three ICs removed (top layer) and (b) port locations (bottom layer). As discussed earlier, each IC is assumed to draw an equivalent switching current at its corresponding port. Then, the power island under study can be modeled using a simple four-port network as shown in Figure 2.3. The Z-parameter matrix of the network can be obtained from frequency-domain S-parameter measurements. In this work, the internal impedance between the 1.5 V and ground of each IC looking into its corresponding port is assumed to be much higher than the impedances of the power island in the board. In other words, ideal current sources I S1 -I S3 are used in Figure 2.3 to approximately model the equivalent switching currents at Ports 1-3. The S- parameters among the four ports can be measured using a board with the ICs removed, as shown in Figure 2.2. Four probes made from semi-rigid cable and SMA connector with approximately the same length were soldered to the ports, as shown in Figure 2.4. A four-port vector network analyzer (Agilent N5245A) was used to take the S-parameter

96 82 measurement. To eliminate the effects of the test fixture (probes), port extensions were performed to rotate the reference planes right to the ports. Port 1 Is1 Port 2 Is2 Z Port 4 Port 3 Is3 Figure 2.3. A simple four-port network describing the behaviour of the power island. Figure 2.4. Setup of multiport S-parameter measurement.

97 83 In the equivalent network shown in Figure 2.3, the port voltages and currents are related as Eq. (1), Z11 Z12 Z13 Z14 IS1 V1 Z21 Z22 Z23 Z 24 I S 2 V 2 Z31 Z32 Z33 Z 34 I S 3 V 3 Z41 Z42 Z43 Z44 0 V4 (1) where the impedance matrix [ Z ] is obtained from the measured S-parameter matrix [ S] as Eq. (2). [ ] [ I] [ S] [ ] [ ] Z Z0 I S (2) [ I] is the 4 4 identity matrix, and Z0 50 is the port impedance. It can be easily shown from Eq. (1) that, 1 IS1 Z11 Z12 Z13 V1 I Z Z Z V S I S 3 Z31 Z32 Z 33 V 3 (3) and I V Z Z Z I I S S 2 S 3. (4) In other words, the equivalent switching currents drawn by the three ICs can be easily calculated from the port voltages, which can be obtained from measurements. A 4-

98 84 channel oscilloscope (Agilent MSO8104A) was used in this work. The time-domain voltages at the four ports were simultaneously measured and recorded, when the device under study was active under the normal operation. Both the magnitudes and phases of the noise voltages can be obtained from the time-domain oscilloscope measurement through the Fourier transform. As a result, the phase information of the equivalent switching currents can also be obtained, which provides unique advantages in PDN design as discussed earlier. The setup of the oscilloscope measurement is shown in Figure 2.5. To reduce the setup effect for time-domain measurement, the input impedance of the oscilloscope is 50 ohm to avoid reflection, and cables with same length and the same length semi-rigid probes with SMA connectors were used for all 4 ports. Figure 2.5. Setup of oscilloscope measurement. To test the effectiveness of the proposed methodology, two different board conditions were studied. In the first case, a 10 F capacitor was located at Port 4, while the capacitor was removed in the second case. The effect of the capacitor was included in the S-parameter measurement, when it was present in the board. Thus, the same equations of Eq. (3) and (4) were used for both cases, except that the Z-parameters were different.