MCP6291/2/3/4/ ma, 10 MHz Rail-to-Rail Op Amp. Description. Features. Applications. Available Tools. Package Types. Typical Application MCP6295

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1 1. m, 1 MHz RailtoRail Op mp Features Gain andwidth Product: 1 MHz (typ.) Supply Current: I Q = 1. m Supply Voltage:.4V to 5.5V RailtoRail Input/Output Extended Temperature Range: 4 C to +15 C vailable in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP693) Dual with Chip Select (CS) (MCP695) pplications utomotive Portable Equipment Photo Diode Preamps nalog Filters Notebooks and PDs atterypowered Systems vailable Tools SPICE Macro Model (at FilterLab Software (at Typical pplication V IN R R 4 R 3 C 1 3 R 1 C R5 MCP695 5 CS C 3 7 SecondOrder SallenKey LowPass Filter with an Extra PoleZero Pair and a Chip Select. 1 6 Description The Microchip Technology Inc. MCP691//3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 1 MHz gain bandwidth product (GWP) and a 65 phase margin. This family also operates from a single supply voltage as low as.4v, while drawing 1 m (typ.) quiescent current. In addition, the MCP691//3/4/5 supports railtorail input and output swing, with a common mode input voltage range of V DD +3mV to V SS 3 mv. This family of operational amplifiers is designed with Microchip s advanced CMOS process. The MCP695 has a chip select input (CS) for dual op amps in an 8pin package. This device is manufactured by cascading the two op amps, with the output of op amp being connected to the noninverting input of op amp. The chip select input puts the device in a Low Power mode. The MCP691//3/4/5 family operates in the Extended Temperature Range of 4 C to +15 C. It also has a power supply range of.4v to 5.5V. Package Types MCP691 PDIP, SOIC, MSOP NC 1 _ V IN V IN + 3 V SS 4 + MCP693 PDIP, SOIC, MSOP NC 1 8 CS V IN _ V IN + V SS MCP69 PDIP, SOIC, MSOP 8 NC 1 8 V DD 7 V _ DD V IN V IN _ V IN 5 NC V SS 4 5 V IN V DD NC MCP694 PDIP, SOIC, TSSOP _ V IN D 13 _ V IND V IN + V DD V IN + V _ IN V IND + 11 V SS V INC + _ V INC C MCP695 PDIP, SOIC, MSOP / V IN V DD V _ IN + 7 V IN + V SS V _ IN CS 4 Microchip Technology Inc. DS181Cpage 1

2 1. ELECTRICL CHRCTERISTICS bsolute Maximum Ratings V DD V SS...7.V ll Inputs and Outputs... V SS.3V to V DD +.3V Difference Input Voltage... V DD V SS Output Short Circuit Current...continuous Current at Input Pins...± m Current at Output and Supply Pins...±3 m Storage Temperature...65 C to +15 C Junction Temperature (T J ) C ESD Protection On ll Pins (HM/MM)... 4 kv/4v Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TLE Name V IN +, V IN +, V IN +, V INC +, V IND + V _ IN, V _ IN, V _ IN, V INC, V IND V DD V SS,,, C, D NC CS / V IN + Function Noninverting Inputs Inverting Inputs Positive Power Supply Negative Power Supply Outputs No Internal Connection Chip Select Output of op amp and noninverting input of op amp (MCP695) DC ELECTRICL SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, R L = 1 kω to V DD / and V DD /. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V OS mv V CM = V SS (Note 1) Input Offset Voltage (Extended Temperature) V OS mv T = 4 C to +15 C, V CM = V SS (Note 1) Input Offset Temperature Drift V OS / T ±1.7 µv/ C T = 4 C to +15 C, V CM = V SS (Note 1) Power Supply Rejection PSRR 7 9 d V CM = V SS (Note 1) Input ias, Input Offset Current and Impedance Input ias Current I ±1. p Note t Temperature I 5 p T = +85 C (Note ) t Temperature I 5 n T = +15 C (Note ) Input Offset Current I OS ±1. p Note 3 Common Mode Input Impedance Z CM Ω pf Note 3 Differential Input Impedance Z DIFF Ω pf Note 3 Common Mode (Note 4) Common Mode Input Range V CMR V SS.3 V DD +.3 V Common Mode Rejection Ratio CMRR 7 85 d V CM =.3V to.5v, V DD = 5V Common Mode Rejection Ratio CMRR 65 8 d V CM =.3V to 5.3V, V DD = 5V OpenLoop Gain DC OpenLoop Gain (large signal) OL 9 11 d =.V to V DD.V, V CM =V SS (Note 1) Note 1: The MCP695 s V CM for op amp (pins /V IN + and V IN ) is V SS + 1 mv. : The current at the MCP695 s V IN pin is specified by I only. 3: This specification does not apply to the MCP695 s /V IN + pin. 4: The MCP695 s V IN pin (op amp ) has a common mode range (V CMR ) of V SS + 1 mv to V DD 1 mv. The MCP695 s /V IN + pin (op amp ) has a voltage range specified by V OH and V OL. DS181Cpage 4 Microchip Technology Inc.

3 DC ELECTRICL SPECIFICTIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, R L = 1 kω to V DD / and V DD /. Parameters Sym Min Typ Max Units Conditions Output Maximum Output Voltage Swing V OL, V OH V SS + 15 V DD 15 mv Output ShortCircuit Current I SC ±5 m Power Supply Supply Voltage V DD V T = 4 C to +15 C Quiescent Current per mplifier I Q m I O = Note 1: The MCP695 s V CM for op amp (pins /V IN + and V IN ) is V SS + 1 mv. : The current at the MCP695 s V IN pin is specified by I only. 3: This specification does not apply to the MCP695 s /V IN + pin. 4: The MCP695 s V IN pin (op amp ) has a common mode range (V CMR ) of V SS + 1 mv to V DD 1 mv. The MCP695 s /V IN + pin (op amp ) has a voltage range specified by V OH and V OL. C ELECTRICL SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions C Response Gain andwidth Product GWP 1. MHz Phase Margin at UnityGain PM 65 Slew Rate SR 7 V/µs Noise Input Noise Voltage E ni 3.5 µvpp f =.1 Hz to 1 Hz Input Noise Voltage Density e ni 8.7 nv/ Hz f = 1 khz Input Noise Current Density i ni 3 f/ Hz f = 1 khz TEMPERTURE SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, V DD = +.4V to +5.5V and V SS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T C Note Storage Temperature Range T C Thermal Package Resistances Thermal Resistance, 8LPDIP θ J 85 C/W Thermal Resistance, 8LSOIC θ J 163 C/W Thermal Resistance, 8LMSOP θ J 6 C/W Thermal Resistance, 14LPDIP θ J 7 C/W Thermal Resistance, 14LSOIC θ J 1 C/W Thermal Resistance, 14LTSSOP θ J 1 C/W Note: The Junction Temperature (T J ) must not exceed the bsolute Maximum specification of +15 C. 4 Microchip Technology Inc. DS181Cpage 3

4 MCP693/MCP695 CHIP SELECT (CS) SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V IL V SS. V DD V CS Input Current, Low I CSL.1 µ CS = V SS CS High Specifications CS Logic Threshold, High V IH.8 V DD V DD V CS Input Current, High I CSH.7 µ CS = V DD GND Current I Q.7 µ CS = V DD mplifier Output Leakage.1 µ CS = V DD Dynamic Specifications (Note 1) CS Low to Valid mplifier Output, Turnon Time CS High to mplifier Output HighZ t ON 4 1 µs CS Low. V DD, G = +1 V/V, V IN = V DD /, =.9 V DD /, V DD = 5.V t OFF.1 µs CS High.8 V DD, G = +1 V/V, V IN = V DD /, =.1 V DD / Hysteresis V HYST.6 V V DD = 5V Note 1: The input condition (V IN ) specified applies to both op amp and of the MCP695. The dynamic specification is tested at the output of op amp ( ). DS181Cpage 4 4 Microchip Technology Inc.

5 . TYPICL PERFORMNCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Percentage of Occurrences 1% 11% 1% 9% 8% 7% 6% 5% 4% 3% % 1% % 84 Samples V CM = V SS Input Offset Voltage (mv)..4.8 Percentage of Occurrences 5% % 15% 1% 5% % 84 Samples V CM = V SS T = 4 C to +15 C Input Offset Voltage Drift (µv/ C) 8 1 FIGURE 1: Input Offset Voltage. FIGURE 4: Input Offset Voltage Drift. Percentage of Occurrences 4% 35% 3% 5% % 15% 1% 5% % FIGURE : T = +85 C. 1 Samples T = 85 C Input ias Current (p) Input ias Current with Percentage of Occurrences 3% 5% % 15% 1% 5% % 1 Samples T = +15 C FIGURE 5: T = +15 C Input ias Current (p) Input ias Current with Input Offset Voltage (µv) V DD =.4 V T = 4 C T = +5 C T = +85 C T = +15 C Common Mode Input Voltage (V) FIGURE 3: Input Offset Voltage vs. Common Mode Input Voltage with V DD =.4V. Input Offset Voltage (µv) V DD = 5.5 V T = +15 C T = +85 C T = +5 C T = 4 C Common Mode Input Voltage (V) FIGURE 6: Input Offset Voltage vs. Common Mode Input Voltage with V DD = 5.5V. 4 Microchip Technology Inc. DS181Cpage 5

6 1.E+ 1.E+1 1.E+ 1.E+3 1.E+4 1.E+5 1.E+6 MCP691//3/4/5 Note: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Input Offset Voltage (µv) V DD = 5.5V V DD =.4V Output Voltage (V) V CM = V SS Representative Part Input ias, Offset Currents (p) 1, 1, V CM = V DD V DD = 5.5V Input ias Current Input Offset Current mbient Temperature ( C) FIGURE 7: Output Voltage. Input Offset Voltage vs. FIGURE 1: Input ias, Input Offset Currents vs. mbient Temperature V DD = 5.5V. CMRR, PSRR (d) 11 V DD = 5.V 1 9 CMRR 8 PSRR 7 PSRR k 1k 1k 1M Frequency (Hz) PSRR, CMRR (d) CMRR PSRR V CM = V SS mbient Temperature ( C) FIGURE 8: Frequency. CMRR, PSRR vs. FIGURE 11: Temperature. CMRR, PSRR vs. mbient Input ias, Offset Currents (p) T = +85 C V DD = 5.5V Input ias Current Input Offset Current Common Mode Input Voltage (V) FIGURE 9: Input ias, Input Offset Currents vs. Common Mode Input Voltage with T = +85 C. Input ias, Offset Currents (n) T = +15 C V DD = 5.5V Input ias Current Input Offset Current Common Mode Input Voltage (V) FIGURE 1: Input ias, Input Offset Currents vs. Common Mode Input Voltage with T = +15 C. DS181Cpage 6 4 Microchip Technology Inc.

7 Note: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Quiescent Current (m/mplifier) Power Supply Voltage (V) T = +15 C T = +85 C T = +5 C T = 4 C FIGURE 13: Quiescent Current vs. Power Supply Voltage. Ouput Voltage Headroom (mv) V OL V SS V DD V OH Output Current Magnitude (m) FIGURE 16: Output Voltage Headroom vs. Output Current Magnitude OpenLoop Gain (d) 1 3 Gain 8 6 Phase k 1k 1k 1M 1M 1M 1.E1 1.E+ 1.E+1 1.E+ 1.E+3 Frequency (Hz) 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 OpenLoop Phase ( ) Gain andwidth Product (MHz) GWP, V DD = 5.5V GWP, V DD =.4V PM, V DD = 5.5V PM, V DD =.4V mbient Temperature ( C) Phase Margin ( ) FIGURE 14: Frequency. OpenLoop Gain, Phase vs. FIGURE 17: Gain andwidth Product, Phase Margin vs. mbient Temperature. 1 1 Maximum Output Voltage Swing (V PP ) 1 V DD = 5.5V V DD =.4V Slew Rate (V/µs) Falling Edge, V DD = 5.5V V DD =.4V Rising Edge, V DD = 5.5V V DD =.4V.1 1k 1k 1k 1M 1M Frequency (Hz) 1.E+3 1.E+4 1.E+5 1.E+6 1.E mbient Temperature ( C) FIGURE 15: Maximum Output Voltage Swing vs. Frequency. FIGURE 18: Temperature. Slew Rate vs. mbient 4 Microchip Technology Inc. DS181Cpage 7

8 1.E1 1.E+ 1.E+1 1.E+ 1.E+3 1.E+4 1.E+5 1.E+6 MCP691//3/4/5 Note: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Input Noise Voltage Density (nv/ Hz) 1, k 1k 1k Frequency (Hz) 1M Input Noise Voltage Density (nv/ Hz) f = 1 khz Common Mode Input Voltage (V) FIGURE 19: vs. Frequency. Input Noise Voltage Density FIGURE : Input Noise Voltage Density vs. Common Mode Input Voltage at 1 khz. Ouptut Short Circuit Current (m) T = +15 C T = +85 C T = +5 C T = 4 C Power Supply Voltage (V) ChanneltoChannel Separation (d) Frequency (khz) FIGURE : Output ShortCircuit Current vs. Power Supply Voltage. FIGURE 3: ChanneltoChannel Separation vs. Frequency (MCP69, MCP694 and MCP695 only). Quiescent Current (m) Opmp shuts off here Opmp turns on here CS swept high to low Chip Select Voltage (V) Hysteresis CS swept low to high V DD =.4V FIGURE 1: Quiescent Current vs. Chip Select (CS) Voltage with V DD =.4V (MCP693 and MCP695 only). Quiescent Current (m) Op mp shuts off Op mp turns on CS swept high to low Hysteresis CS swept low to high Chip Select Voltage (V) V DD = 5.5V FIGURE 4: Quiescent Current vs. Chip Select (CS) Voltage with V DD = 5.5V (MCP693 and MCP695 only). DS181Cpage 8 4 Microchip Technology Inc.

9 .E+ 1.E6.E6 3.E6 4.E6 5.E6 6.E6 7.E6 8.E6 9.E6 1.E5.E+ 1.E6.E6 3.E6 4.E6 5.E6 6.E6 7.E6 8.E6 9.E6 1.E5.E+ 5.E6 1.E5.E5.E5 3.E5 3.E5 4.E5 4.E5 5.E5 5.E5 MCP691//3/4/5 Note: Unless otherwise indicated, T = +5 C, V DD = +.4V to +5.5V, V SS = GND, V CM = V DD /, V DD /, R L = 1 kω to V DD / and C L = 6 pf. Output Voltage (V) Time (1 µs/div) G = +1V/V V DD = 5.V Output Voltage (V) G = 1V/V V DD = 5.V Time (1 µs/div) FIGURE 5: Pulse Response. Large Signal Noninverting FIGURE 8: Response. Large Signal Inverting Pulse G = +1V/V G = 1V/V Output Voltage (1 mv/div) Output Voltage (1 mv/div) Time ( ns/div) Time ( ns/div) FIGURE 6: Pulse Response. Small Signal Noninverting FIGURE 9: Response. Small Signal Inverting Pulse Chip Select, Output Voltage (V) CS Voltage Output HighZ V DD =.4V G = +1V/V V IN = V SS Output On.E+ 5.E6 1.E5.E5.E5 3.E5 3.E5 4.E5 4.E5 5.E5 5.E5 Time (5 µs/div) Chip Select, Output Voltage (V) CS Voltage Output HighZ Time (5 µs/div) V DD = 5.5V G = +1V/V V IN = V SS Output On FIGURE 7: Chip Select (CS) to mplifier Output Response Time with V DD =.4V (MCP693 and MCP695 only). FIGURE 3: Chip Select (CS) to mplifier Output Response Time with V DD = 5.5V (MCP693 and MCP695 only). 4 Microchip Technology Inc. DS181Cpage 9

10 MCP691//3/4/5 3. PPLICTION INFORMTION The MCP691//3/4/5 family of op amps is manufactured using Microchip s stateoftheart CMOS process, specifically designed for lowcost, lowpower and generalpurpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP691//3/4/5 ideal for batterypowered applications. 3.1 RailtoRail Input The MCP691//3/4/5 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 31 shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltage (V) V IN Time (1 ms/div) V DD = 5.V G = +V/V FIGURE 31: The MCP691//3/4/5 Show No Phase Reversal. The input stage of the MCP691//3/4/5 op amp uses two differential input stages in parallel. One operates at low common mode input voltage (V CM ), while the other operates at high V CM. With this topology, the device operates with V CM up to 3 mv above V DD and 3 mv below V SS. The Input Offset Voltage is measured at V CM =V SS 3 mv and V DD +3mV to ensure proper operation. Input voltages that exceed the input voltage range (V SS.3V to V DD +.3V at 5 C) can cause excessive current to flow into or out of the input pins. Current beyond ± m can cause reliability problems. pplications that exceed this rating must be externally limited with a resistor, as shown in Figure 3. R IN MCP691 V IN + R IN V SS ( Minimum expected V IN ) R IN m FIGURE 3: Resistor (R IN ). ( Maximum expected V IN ) V DD m 3. RailtoRail Output Input Current Limiting The output voltage range of the MCP691//3/4/5 op amp is V DD 15mV (min.) and V SS +15mV (max.) when R L =1kΩ is connected to V DD / and V DD = 5.5V. Refer to Figure 16 for more information. 3.3 MCP693/5 Chip Select (CS) The MCP693 and MCP695 are single and dual op amps with chip select (CS), respectively. When CS is pulled high, the supply current drops to.7 µ (typ.) and flows through the CS pin to V SS. When this happens, the amplifier output is put into a highimpedance state. y pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 33 shows the output voltage and supply current response to a CS pulse. CS HiZ.7 µ, typ. I VSS V IL t on 1. m, typ. V IH t off HiZ.7 µ, typ..7 µ, typ. 1 n, typ.7 µ, typ. I CS FIGURE 33: Timing Diagram for the Chip Select (CS) pin on the MCP693 and MCP695. DS181Cpage 1 4 Microchip Technology Inc.

11 3.4 Cascaded Dual Op mps (MCP695) The MCP695 is a dual op amp with chip select (CS). The chip select input is available on what would be the noninverting input of a standard dual op amp (pin 5). This feature is provided by connecting the output of op amp to the noninverting input of op amp, as shown in Figure 34. The chip select input, which can be connected to a microcontroller I/O line, puts the device in Low Power mode. Refer to Section 3.3 MCP683/5 Chip Select (CS). V IN V IN + 3 FIGURE 34: /V IN + V IN 1 6 MCP695 5 CS Cascaded Gain mplifier. The key issue to note from this configuration is that the output of op amp is loaded by the input impedance. The input impedance of the op amp is typically 1 13 Ω 6 pf, as specified in the DC specification table (Refer to Section 3.5 Capacitive Loads for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as V SS 3 mv and V DD + 3 mv. However, since the output of op amp is limited to V OL and V OH ( mv from the rails with a 1 kω load), the noninverting input range of op amp is limited to the common mode input range of V SS + mv and V DD mv Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. s the load capacitance increases, the feedback loop s phase margin decreases and the closedloop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. unitygain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 1 pf when G = +1), a small series resistor at the output (R ISO in Figure 35) improves the feedback loop s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V IN R ISO FIGURE 35: Output Resistor, R ISO stabilizes large capacitive loads. Figure 36 gives recommended R ISO values for different capacitive loads and gains. The xaxis is the normalized load capacitance (C L /G N ), where G N is the circuit's noise gain. For noninverting gains, G N and the Signal Gain are equal. For inverting gains, G N is 1+ Signal Gain (e.g., 1 V/V gives G N = + V/V). Recommended R ISO ( ) 1 MCP691 + C L G N = 1 V/V G N V/V , 1, Normalized Load Capacitance; C L /G N (pf) FIGURE 36: Recommended R ISO values for Capacitive Loads. fter selecting R ISO for your circuit, doublecheck the resulting frequency response peaking and step response overshoot. Modify R ISO 's value until the response is reasonable. ench evaluation and simulations with the MCP691//3/4/5 SPICE macro model are very helpful. 4 Microchip Technology Inc. DS181Cpage 11

12 3.6 Supply ypass With this family of operational amplifiers, the power supply pin (V DD for single supply) should have a local bypass capacitor (i.e.,.1 µf to.1 µf) within mm for good highfrequency performance. It also needs a bulk capacitor (i.e., 1 µf or larger) within 1 mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.7 PC Surface Leakage In applications where low input bias current is critical, printed circuit board (PC) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1 1 Ω. 5V difference would cause 5 p, if currenttoflow, which is greater than the MCP691//3/4/5 family s bias current at 5 C (1 p, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. n example of this type of layout is shown in Figure 37. FIGURE 37: for Inverting Gain. V IN V IN + Guard Ring V SS Example Guard Ring Layout 1. For Inverting (Figure 37) and Transimpedance mplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the noninverting input pin (V IN +). This biases the guard ring to the same reference voltage as the op amp (e.g., V DD / or ground). b. Connect the inverting pin (V IN ) to the input with a wire that does not touch the PC surface.. Noninverting Gain and UnityGain uffer: a. Connect the noninverting pin (V IN +) to the input with a wire that does not touch the PC surface. b. Connect the guard ring to the inverting input pin (V IN ). This biases the guard ring to the common mode input voltage. 3.8 pplication Circuits MULTIPLE FEEDCK LOWPSS FILTER The MCP691//3/4/5 op amp can be used in activefilter applications. Figure 38 shows an inverting, thirdorder, multiple feedback lowpass filter that can be used as an antialiasing filter. V IN FIGURE 38: Pass Filter. Multiple Feedback Low This filter, and others, can be designed using Microchip s FilterLab software, which is available on our web site ( PHOTO DIODE MPLIFIER Figure 39 shows a photo diode biased in the photovoltaic mode for high precision. The resistor R converts the diode current I D to the voltage. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode s capacitance (it is not always needed). light V DD / FIGURE 39: R 1 R C 1 V DD / I D R 3 C 3 MCP691 C R MCP691 R 4 C 4 Photo Diode mplifier. DS181Cpage 1 4 Microchip Technology Inc.

13 3.8.3 CSCDED OP MPS PPLICTIONS The MCP695 provides the flexibility of Low Power mode for dual op amps in an 8pin package. The MCP695 eliminates the added cost and space in batterypowered applications by using two single op amps with chip select lines or a 1pin device with chip select line for each op amp. The only inherent limitation to this device is that the two op amps are internally cascaded. Therefore, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with chip select line becomes suitable. The circuits below show possible applications for this device Load Isolation With the cascaded op amp configuration, op amp can be used to isolate the load from op amp. In applications where op amp is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit) the op amp may not have sufficient source current to drive the load. In this case, op amp can be used as a buffer. R 4 R 3 R R 1 V IN FIGURE 311: Configuration. MCP695 CS Cascaded Gain Circuit Difference mplifier Figure 31 shows op amp as a difference amplifier with chip select. In this configuration, it is recommended to use well matched resistors (.1%) to increase the common mode rejection ratio (CMRR). Op amp can be used for additional gain or as a unitygain buffer to isolate the load from the difference amplifier. R 4 R 3 R R 1 MCP695 V IN R V IN1 R 1 MCP695 FIGURE 31: uffer. CS Isolating the Load with a Cascaded Gain Figure 311 shows a cascaded gain circuit configuration with chip select. Op amps and are configured in a noninverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp is amplified by the gain of op amp and, as shown below: = V IN G G + V OS G G + V OS G FIGURE 31: CS Difference mplifier Circuit. Where: G = op amp gain G = op amp gain V OS = op amp offset voltage V OS = op amp offset voltage Therefore, it is recommended to set most of the gain with op amp and use op amp with relatively small gain, or as a unitygain buffer. 4 Microchip Technology Inc. DS181Cpage 13

14 uffered Noninverting Integrator Figure 313 shows a buffered noninverting integrator with chip select. Op amp is configured as a noninverting integrator. In this configuration, matching the impedance at each input is recommended. R f is used to provide a feedback loop at frequencies << 1/(πRC). Op amp is used to isolate the load from the integrator SecondOrder MF LowPass Filter with an Extra PoleZero Pair Figure 315 is a secondorder multiple feedback lowpass filter with chip select. Use the Filterlab software from Microchip to determine the R and C values for the op amp s secondorder filter. Op amp can be used to add a polezero pair using C 3 and R 6. R 1 C 1 R 1 R 6 C 3 V IN R 1 C 1 R f 1 MCP695 V IN R 3 R R C 5 R 4 C1 MCP695 VOUT CS FIGURE 313: uffered Noninverting Integrator with Chip Select Circuit Integrator with ctive Compensation and a Chip Select Figure 314 uses an active compensator (op amp ) to compensate for the nonideal characteristics introduced at higher frequency integration. The alternative is to use a passive element, such as a resistor, for compensation. However, the quality of compensation would not be constant since the C characteristics of an amplifier varies over temperature and process. This circuit uses op amp as a unitygain buffer to isolate the integration capacitor C 1 from op amp and drives the capacitor with low impedance source. Since both amplifiers are matched very well, it provides a higher quality of integration. R 1 C 1 FIGURE 315: SecondOrder Multiple Feedback LowPass Filter with an Extra Pole Zero Pair and Chip Select SecondOrder SallenKey LowPass Filter with an Extra PoleZero Pair Figure 316 is a secondorder SallenKey lowpass filter with chip select. Use the Filterlab software from Microchip to determine the R and C values for the op amp s secondorder filter. Op amp can be used to add a polezero pair using C 3 and R 5. V IN R R 4 R 3 C 1 R 1 CS R5 C 3 MCP695 C CS V IN MCP695 FIGURE 316: SecondOrder SallenKey LowPass Filter with an Extra PoleZero Pair and Chip Select. CS FIGURE 314: Compensation. Integrator Circuit with ctive DS181Cpage 14 4 Microchip Technology Inc.

15 Capacitorless SecondOrder LowPass filter with Chip Select The lowpass filter shown in Figure 317 does not require external capacitors. It uses only three external resistors. The op amp s GWP sets the corner frequency. R 1 and R are used to set the circuit gain and R 3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R 3 ). Note that the amplifier bandwidth varies greatly over temperature and process. However, this configuration provides a low cost solution for applications with high bandwidth. V IN V REF R R 1 R 3 MCP695 CS FIGURE 317: Capacitorless SecondOrder LowPass Filter with Chip Select Circuit. 4. DESIGN TOOLS Microchip provides the basic design tools needed for the MCP691//3/4/5 family of op amps. 4.1 SPICE Macro Model The latest version of SPICE Macro Model for the MCP691//3/4/5 op amps is available on our web site at This model is intended to be an initial design tool that works well in the op amp s linear region of operation at room temperature. See the model file for information on its capabilities. ench testing is a very important part of any design and cannot be replaced with simulations. lso, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 4. FilterLab Software Microchip s FilterLab software is an innovative tool that simplifies analog activefilter (using op amps) design. vailable at no cost from our web site at the FilterLab activefilter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 4 Microchip Technology Inc. DS181Cpage 15

16 5. PCKGING INFORMTION 5.1 Package Marking Information 8Lead MSOP XXXXXX YWWNNN Example: Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP691 E/P Lead SOIC (15 mil) Example: XXXXXXXX XXXXYYWW NNN MCP691 E/SN47 56 Legend: XX...X Customer specific information* YY Year code (last digits of calendar year) WW Week code (week of January 1 is week 1 ) NNN lphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS181Cpage 16 4 Microchip Technology Inc.

17 Package Marking Information (Continued) 14Lead PDIP (3 mil) (MCP694) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP694E/P Lead SOIC (15 mil) (MCP694) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP694ESL Lead TSSOP (MCP694) Example: XXXXXX YYWW NNN 694ST Microchip Technology Inc. DS181Cpage 17

18 8Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p n 1 D α c φ 1 β (F) L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MX MIN NOM Number of Pins n 8 8 Pitch p.6 SC.65 SC Overall Height Molded Package Thickness Standoff Overall Width 1 E..193 TYP SC Molded Package Width Overall Length Foot Length E1 D L SC.118 SC SC 3. SC.6 Footprint (Reference) F.37 REF.95 REF Foot ngle φ 8 Lead Thickness c Lead Width Mold Draft ngle Top Mold Draft ngle ottom α β *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1" (.54mm) per side. JEDEC Equivalent: MO187 Drawing No. C4111 MX DS181Cpage 18 4 Microchip Technology Inc.

19 8Lead Plastic Dual Inline (P) 3 mil (PDIP) E1 D n 1 α E c 1 L β e 1 p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 8 8 Pitch p.1.54 Top to Seating Plane Molded Package Thickness ase to Seating Plane Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width Lower Lead Width Overall Row Spacing e Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 (.54mm) per side. JEDEC Equivalent: MS1 Drawing No. C418 4 Microchip Technology Inc. DS181Cpage 19

20 8Lead Plastic Small Outline (SN) Narrow, 15 mil (SOIC) E E1 p D n 1 45 h α c φ β L 1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 8 8 Pitch p Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 (.54mm) per side. JEDEC Equivalent: MS1 Drawing No. C457 DS181Cpage 4 Microchip Technology Inc.

21 14Lead Plastic Dual Inline (P) 3 mil (PDIP) E1 D n 1 α E c L β e 1 1 p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n Pitch p.1.54 Top to Seating Plane Molded Package Thickness ase to Seating Plane Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width Lower Lead Width Overall Row Spacing e Mold Draft ngle Top α Mold Draft ngle ottom * Controlling Parameter Significant Characteristic β Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 (.54mm) per side. JEDEC Equivalent: MS1 Drawing No. C45 4 Microchip Technology Inc. DS181Cpage 1

22 14Lead Plastic Small Outline (SL) Narrow, 15 mil (SOIC) E E1 p D n 1 45 h α c β L φ 1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n Pitch p Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 (.54mm) per side. JEDEC Equivalent: MS1 Drawing No. C465 DS181Cpage 4 Microchip Technology Inc.

23 14Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) p E E1 D n 1 α c φ β L 1 Units Dimension Limits Number of Pins n Pitch p Overall Height Molded Package Thickness Standoff 1 Overall Width E Molded Package Width E1 Molded Package Length D Foot Length L Foot ngle φ Lead Thickness c Lead Width 1 Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic MIN INCHES NOM MX MIN MILLIMETERS* NOM Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.5 (.17mm) per side. JEDEC Equivalent: MO153 Drawing No. C MX Microchip Technology Inc. DS181Cpage 3

24 NOTES: DS181Cpage 4 4 Microchip Technology Inc.

25 PRODUCT IDENTIFICTION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PRT NO. X /XX Device Temperature Range Package Device: MCP691: Single Operational mplifier MCP691T: Single Operational mplifier (Tape and Reel) (SOIC, MSOP) MCP69: Dual Operational mplifier MCP69T: Dual Operational mplifier (Tape and Reel) (SOIC, MSOP) MCP693: Single Operational mplifier with Chip Select MCP693T: Single Operational mplifier with Chip Select (Tape and Reel) (SOIC, MSOP) MCP694: Quad Operational mplifier MCP694T: Quad Operational mplifier (Tape and Reel) (SOIC, TSSOP) MCP695: Dual Operational mplifier with Chip Select MCP695T: Dual Operational mplifier with Chip Select (Tape and Reel) (SOIC, MSOP) Temperature Range: E = 4 C to +15 C Package: MS = Plastic MSOP, 8lead P = Plastic DIP (3 mil ody), 8lead, 14lead SN = Plastic SOIC, (15 mil ody), 8lead SL = Plastic SOIC (15 mil ody), 14lead ST = Plastic TSSOP (4.4mm ody), 14lead Examples: a) MCP691E/SN: Extended Temperature, 8LD SOIC package. b) MCP691E/MS: Extended Temperature, 8LD MSOP package. c) MCP691E/P: Extended Temperature, 8LD PDIP package. d) MCP691TE/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. a) MCP69E/SN: Extended Temperature, 8LD SOIC package. b) MCP69E/MS: Extended Temperature, 8LD MSOP package. c) MCP69E/P: Extended Temperature, 8LD PDIP package. d) MCP69TE/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. a) MCP693E/SN: Extended Temperature, 8LD SOIC package. b) MCP693E/MS: Extended Temperature, 8LD MSOP package. c) MCP693E/P: Extended Temperature, 8LD PDIP package. d) MCP693TE/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. a) MCP694E/P: Extended Temperature, 14LD PDIP package. b) MCP694TE/SL: Tape and Reel, Extended Temperature, 14LD SOIC package. c) MCP694E/SL: Extended Temperature, 14LD SOIC package. d) MCP694E/ST: Extended Temperature, 14LD TSSOP package. a) MCP695E/SN: Extended Temperature, 8LD SOIC package. b) MCP695E/MS: Extended Temperature, 8LD MSOP package. c) MCP695E/P: Extended Temperature, 8LD PDIP package. d) MCP695TE/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. The Microchip Corporate Literature Center U.S. FX: (48) The Microchip Worldwide Site ( Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site ( to receive the most current information on our products. 4 Microchip Technology Inc. DS181Cpage 5

26 NOTES: DS181Cpage 6 4 Microchip Technology Inc.

27 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. ll of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. ttempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright ct. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that ct. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, ccuron, dspic, KEELOQ, microid, MPL, PIC, PICmicro, PICSTRT, PRO MTE, PowerSmart, rfpic, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.. and other countries. mplab, FilterLab, MXDEV, MXL, PICMSTER, SEEVL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.. nalogforthedigital ge, pplication Maestro, dspicdem, dspicdem.net, dspicworks, ECN, ECONOMONITOR, FanSense, FlexROM, fuzzyl, InCircuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPSM, MPLI, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICL, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfl, rfpicdem, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.. ll other trademarks mentioned herein are property of their respective companies. 4, Microchip Technology Incorporated, Printed in the U.S.., ll Rights Reserved. Printed on recycled paper. Microchip received ISO/TS16949: quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, rizona and Mountain View, California in October 3. The Company s quality system processes and procedures are for its PICmicro 8bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 91: certified. 4 Microchip Technology Inc. DS181Cpage 7

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29 Mouser Electronics uthorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: MCP695E/MS MCP695E/SN MCP695E/P MCP695TE/SN MCP695TE/MS