1.0 ma, 10 MHz Rail-to-Rail Op Amp MCP6291 PDIP, SOIC, MSOP MCP6292 PDIP, SOIC, MSOP 6 V DD 1 2 V INA + 3 V DD V OUT V SS 4 MCP6294 PDIP, SOIC, TSSOP

Transcription

1 . m, MHz Rail-to-Rail Op mp Features Gain andwidth Product: MHz (typ.) Supply Current: I Q =. m Supply Voltage:.4V to.v Rail-to-Rail Input/Output Extended Temperature Range: -4 C to + C vailable in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP693) Dual with Chip Select (CS) (MCP69) pplications utomotive Portable Equipment Photodiode mplifier nalog Filters Notebooks and PDs attery-powered Systems vailable Tools SPICE Macro Model (at FilterLab Software (at Description The Microchip Technology Inc. family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a MHz Gain andwidth Product (GWP) and a 6 phase margin. This family also operates from a single supply voltage as low as.4v, while drawing m (typ.) quiescent current. In addition, the supports rail-to-rail input and output swing, with a common mode input voltage range of V DD +3mV to V SS 3 mv. This family of operational amplifiers is designed with Microchip s advanced CMOS process. The MCP69 has a Chip Select input (CS) for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp being connected to the non-inverting input of op amp. The CS input puts the device in a Low-power mode. The family operates over the Extended Temperature Range of -4 C to + C. It also has a power supply range of.4v to.v. Package Types MCP69 PDIP, SOIC, MSOP NC 8 NC _ V IN V IN V DD V SS 4 NC V SS V IN + 3 MCP69 SOT V DD 4 V IN V DD V IN + MCP69R SOT V SS - 4 V IN MCP69 PDIP, SOIC, MSOP 8 _ V IN - V IN + 3 V SS 4 V DD _ V IN V IN + MCP693 PDIP, SOIC, MSOP NC _ V IN V IN + V SS CS V DD NC V SS V IN + 3 MCP693 SOT V DD CS 4 V IN MCP694 PDIP, SOIC, TSSOP V IN _ V IN + V DD 3 4 V IN + _ V IN V IND + V SS 9 D V IND _ V INC + _ V INC MCP69 PDIP, SOIC, MSOP /V IN + 8 V _ IN V IN + V SS V DD V _ IN CS 7 8 C 4 Microchip Technology Inc. DS8D-page

2 . ELECTRICL CHRCTERISTICS bsolute Maximum Ratings V DD V SS...7.V ll Inputs and Outputs... V SS.3V to V DD +.3V Difference Input Voltage... V DD V SS Output Short Circuit Current...Continuous Current at Input Pins...± m Current at Output and Supply Pins...±3 m Storage Temperature...-6 C to + C Junction Temperature (T J )...+ C ESD Protection On ll Pins (HM/MM)... 4 kv/4v Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICL SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, R L = kω to V DD / and V DD /. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V OS mv V CM = V SS (Note ) Input Offset Voltage (Extended Temperature) V OS mv T = -4 C to + C, V CM = V SS (Note ) Input Offset Temperature Drift V OS / T ±.7 µv/ C T = -4 C to + C, V CM = V SS (Note ) Power Supply Rejection Ratio PSRR 7 9 d V CM = V SS (Note ) Input ias, Input Offset Current and Impedance Input ias Current I ±. p Note t Temperature I p T = +8 C (Note ) t Temperature I n T = + C (Note ) Input Offset Current I OS ±. p Note 3 Common Mode Input Impedance Z CM 3 6 Ω pf Note 3 Differential Input Impedance Z DIFF 3 3 Ω pf Note 3 Common Mode (Note 4) Common Mode Input Range V CMR V SS.3 V DD +.3 V Common Mode Rejection Ratio CMRR 7 8 d V CM = -.3V to.v, V DD = V Common Mode Rejection Ratio CMRR 6 8 d V CM = -.3V to.3v, V DD = V Open-Loop Gain DC Open-Loop Gain (Large Signal) OL 9 d =.V to V DD.V, V CM =V SS (Note ) Output Maximum Output Voltage Swing V OL, V OH V SS + V DD mv Output Short Circuit Current I SC ± m Power Supply Supply Voltage V DD.4. V T = -4 C to + C Quiescent Current per mplifier I Q.7..3 m I O = Note : The MCP69 s V CM for op amp (pins /V IN + and V IN ) is V SS + mv. : The current at the MCP69 s V IN pin is specified by I only. 3: This specification does not apply to the MCP69 s /V IN + pin. 4: The MCP69 s V IN pin (op amp ) has a common mode range (V CMR ) of V SS + mv to V DD mv. The MCP69 s /V IN + pin (op amp ) has a voltage range specified by V OH and V OL. DS8D-page 4 Microchip Technology Inc.

3 C ELECTRICL SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions C Response Gain andwidth Product GWP. MHz Phase Margin at Unity-Gain PM 6 Slew Rate SR 7 V/µs Noise Input Noise Voltage E ni 3. µv P-P f =. Hz to Hz Input Noise Voltage Density e ni 8.7 nv/ Hz f = khz Input Noise Current Density i ni 3 f/ Hz f = khz TEMPERTURE SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, V DD = +.4V to +.V and V SS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -4 + C Note Storage Temperature Range T -6 + C Thermal Package Resistances Thermal Resistance, L-SOT-3 θ J 6 C/W Thermal Resistance, 6L-SOT-3 θ J 3 C/W Thermal Resistance, 8L-PDIP θ J 8 C/W Thermal Resistance, 8L-SOIC θ J 63 C/W Thermal Resistance, 8L-MSOP θ J 6 C/W Thermal Resistance, 4L-PDIP θ J 7 C/W Thermal Resistance, 4L-SOIC θ J C/W Thermal Resistance, 4L-TSSOP θ J C/W Note: The Junction Temperature (T J ) must not exceed the bsolute Maximum specification of + C. 4 Microchip Technology Inc. DS8D-page 3

4 MCP693/MCP69 CHIP SELECT (CS) SPECIFICTIONS Electrical Characteristics: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V IL V SS. V DD V CS Input Current, Low I CSL. µ CS = V SS CS High Specifications CS Logic Threshold, High V IH.8 V DD V DD V CS Input Current, High I CSH.7 µ CS = V DD GND Current per mplifier I SS -.7 µ CS = V DD mplifier Output Leakage. µ CS = V DD Dynamic Specifications (Note ) CS Low to Valid mplifier Output, Turn-on Time t ON 4 µs CS Low. V DD, G = + V/V, V IN = V DD /, =.9 V DD /, V DD =.V CS High to mplifier Output High-Z t OFF. µs CS High.8 V DD, G = + V/V, V IN = V DD /, =. V DD / Hysteresis V HYST.6 V V DD = V Note : The input condition (V IN ) specified applies to both op amp and of the MCP69. The dynamic specification is tested at the output of op amp ( ). CS V IL V IH t ON t OFF Hi-Z Hi-Z -.7 µ (typ.) -.7 µ (typ.) I SS -. m (typ.).7 µ (typ.).7 µ (typ.) I CS n (typ.) FIGURE -: Timing Diagram for the Chip Select (CS) pin on the MCP693 and MCP69. DS8D-page 4 4 Microchip Technology Inc.

5 . TYPICL PERFORMNCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Percentage of Occurrences % % % 9% 8% 7% 6% % 4% 3% % % % 84 Samples V CM = V SS Input Offset Voltage (mv)..4.8 Percentage of Occurrences % % % % % % 84 Samples V CM = V SS T = -4 C to + C Input Offset Voltage Drift (µv/ C) 8 FIGURE -: Input Offset Voltage. FIGURE -4: Input Offset Voltage Drift. Percentage of Occurrences 4% 3% 3% % % % % % % Samples T = 8 C Input ias Current (p) Percentage of Occurrences 3% % % % % % % Samples T = + C Input ias Current (p) FIGURE -: T = +8 C. Input ias Current at FIGURE -: T = + C. Input ias Current at Input Offset Voltage (µv) V DD =.4V T = -4 C T = + C T = +8 C T = + C Common Mode Input Voltage (V) FIGURE -3: Input Offset Voltage vs. Common Mode Input Voltage at V DD =.4V. Input Offset Voltage (µv) V DD =.V T = + C T = +8 C T = + C T = -4 C Common Mode Input Voltage (V) FIGURE -6: Input Offset Voltage vs. Common Mode Input Voltage at V DD =.V. 4 Microchip Technology Inc. DS8D-page

6 .E+.E+.E+.E+3.E+4.E+.E+6 TYPICL PERFORMNCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Input Offset Voltage (µv) V DD =.V V DD =.4V Output Voltage (V) V CM = V SS Representative Part Input ias, Offset Currents (p),, V CM = V DD V DD =.V Input ias Current Input Offset Current mbient Temperature ( C) FIGURE -7: Output Voltage. Input Offset Voltage vs. FIGURE -: Input ias, Input Offset Currents vs. mbient Temperature. CMRR, PSRR (d) 9 CMRR 8 PSRR- 7 PSRR k k k M Frequency (Hz) PSRR, CMRR (d) CMRR PSRR V CM = V SS mbient Temperature ( C) FIGURE -8: Frequency. CMRR, PSRR vs. FIGURE -: Temperature. CMRR, PSRR vs. mbient Input ias, Offset Currents (p) T = +8 C V DD =.V Input ias Current Input Offset Current Common Mode Input Voltage (V) FIGURE -9: Input ias, Offset Currents vs. Common Mode Input Voltage at T =+8 C. Input ias, Offset Currents (n) T = + C V DD =.V Input ias Current Input Offset Current Common Mode Input Voltage (V) FIGURE -: Input ias, Offset Currents vs. Common Mode Input Voltage at T = + C. DS8D-page 6 4 Microchip Technology Inc.

7 TYPICL PERFORMNCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Quiescent Current (m/mplifier) Power Supply Voltage (V) T = + C T = +8 C T = + C T = -4 C FIGURE -3: Quiescent Current vs. Power Supply Voltage. Ouput Voltage Headroom (mv) V OL - V SS V DD - V OH.. Output Current Magnitude (m) FIGURE -6: Output Voltage Headroom vs. Output Current Magnitude. 6 9 Open-Loop Gain (d) -3 Gain 8-6 Phase k k k M M M.E-.E+.E+.E+.E+3 Frequency (Hz).E+4.E+.E+6.E+7.E+8 Open-Loop Phase ( ) Gain andwidth Product (MHz) GWP, V DD =.V GWP, V DD =.4V PM, V DD =.V PM, V DD =.4V mbient Temperature ( C) Phase Margin ( ) FIGURE -4: Frequency. Open-Loop Gain, Phase vs. FIGURE -7: Gain andwidth Product, Phase Margin vs. mbient Temperature. Maximum Output Voltage Swing (V P-P ) V DD =.V V DD =.4V Slew Rate (V/µs) Falling Edge, V DD =.V V DD =.4V Rising Edge, V DD =.V V DD =.4V. k k k M M Frequency (Hz).E+3.E+4.E+.E+6.E mbient Temperature ( C) FIGURE -: Maximum Output Voltage Swing vs. Frequency. FIGURE -8: Temperature. Slew Rate vs. mbient 4 Microchip Technology Inc. DS8D-page 7

8 .E-.E+.E+.E+.E+3.E+4.E+.E+6 TYPICL PERFORMNCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Input Noise Voltage Density (nv/ Hz),. k k k Frequency (Hz) M Input Noise Voltage Density (nv/ Hz) 9 8 f = khz 7 V DD =.V Common Mode Input Voltage (V) FIGURE -9: vs. Frequency. Input Noise Voltage Density FIGURE -: Input Noise Voltage Density vs. Common Mode Input Voltage at khz. Ouptut Short Circuit Current (m) 3 3 T = + C T = +8 C T = + C T = -4 C Power Supply Voltage (V) Channel-to-Channel Separation (d) 4 3 Frequency (khz) FIGURE -: Output Short Circuit Current vs. Power Supply Voltage. FIGURE -3: Channel-to-Channel Separation vs. Frequency (MCP69, MCP694 and MCP69 only). Quiescent Current (m/mplifier) Op-mp shuts off here Op-mp turns on here CS swept high to low Hysteresis CS swept low to high V DD =.4V Quiescent Current (m/mplifier) Op mp shuts off Op mp turns on CS swept high to low Hysteresis CS swept low to high V DD =.V Chip Select Voltage (V) FIGURE -: Quiescent Current vs. Chip Select (CS) Voltage at V DD =.4V (MCP693 and MCP69 only) Chip Select Voltage (V) FIGURE -4: Quiescent Current vs. Chip Select (CS) Voltage at V DD =.V (MCP693 and MCP69 only). DS8D-page 8 4 Microchip Technology Inc.

9 .E+.E-6.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E-.E+.E-6.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E-.E+.E-6.E-.E-.E- 3.E- 3.E- 4.E- 4.E-.E-.E- TYPICL PERFORMNCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = + C, V DD = +.4V to +.V, V SS = GND, V CM = V DD /, V DD /, R L = kω to V DD / and C L = 6 pf. Output Voltage (V) Time ( µs/div) G = +V/V V DD =.V Output Voltage (V) G = -V/V V DD =.V Time ( µs/div) FIGURE -: Pulse Response. Large-Signal Non-inverting FIGURE -8: Response. Large-Signal Inverting Pulse G = +V/V G = -V/V Output Voltage ( mv/div) Output Voltage ( mv/div) Time ( ns/div) Time ( ns/div) FIGURE -6: Pulse Response. Small-Signal Non-inverting FIGURE -9: Response. Small-Signal Inverting Pulse Chip Select, Output Voltages (V) CS Voltage Output High-Z V DD =.4V G = +V/V V IN = V SS Output On.E+.E-6.E-.E-.E- 3.E- 3.E- 4.E- 4.E-.E-.E- Time ( µs/div) Chip Select, Output Voltages (V) CS Voltage Output High-Z Time ( µs/div) V DD =.V G = +V/V V IN = V SS Output On FIGURE -7: Chip Select (CS) to mplifier Output Response Time at V DD =.4V (MCP693 and MCP69 only). FIGURE -3: Chip Select (CS) to mplifier Output Response Time at V DD =.V (MCP693 and MCP69 only). 4 Microchip Technology Inc. DS8D-page 9

10 3. PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3- (single op amps) and Table 3- (dual and quad op amps). TLE 3-: PIN FUNCTION TLE FOR SINGLE OP MPS MCP69 (PDIP, SOIC, MSOP) MCP69 (SOT-3-) MCP67R (SOT-3-) MCP693 (PDIP, SOIC, MSOP) MCP693 (SOT-3-6) Symbol Description 6 6 nalog Output V IN Inverting Input V IN + Non-inverting Input V DD Positive Power Supply 4 4 V SS Negative Power Supply 8 CS Chip Select,,8, NC No Internal Connection TLE 3-: PIN FUNCTION TLE FOR DUL ND QUD OP MPS MCP69 MCP694 MCP69 Symbol Description nalog Output (op amp ) V IN Inverting Input (op amp ) V IN + Non-inverting Input (op amp ) V DD Positive Power Supply V IN + Non-inverting Input (op amp ) V IN Inverting Input (op amp ) nalog Output (op amp ) 8 C nalog Output (op amp C) 9 V INC Inverting Input (op amp C) V INC + Non-inverting Input (op amp C) 4 4 V SS Negative Power Supply V IND + Non-inverting Input (op amp D) 3 V IND Inverting Input (op amp D) 4 D nalog Output (op amp D) /V IN + nalog Output (op amp )/Non-inverting Input (op amp ) CS Chip Select 3. nalog Outputs The output pins are low-impedance voltage sources. 3. nalog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 MCP69 s /V IN + Pin For the MCP69 only, the output of op amp is connected directly to the non-inverting input of op amp ; this is the /V IN + pin. This connection makes it possible to provide a Chip Select pin for duals in 8-pin packages. 3.4 CS Digital Input This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3. Power Supply (V SS and V DD ) The positive power supply (V DD ) is.4v to.v higher than the negative power supply (V SS ). For normal operation, the other pins are between V SS and V DD. Typically, these parts are used in a single (positive) supply configuration). In this case, V SS is connected to ground and V DD is connected to the supply. V DD will need a local bypass capacitor (typically. µf to. µf) within mm of the V DD pin. These parts need to use a bulk capacitor (within mm), which can be shared with nearby analog parts. DS8D-page 4 Microchip Technology Inc.

11 PPLICTION INFORMTION The family of op amps is manufactured using Microchip s state-of-the-art CMOS process, specifically designed for low-cost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the ideal for battery-powered applications. 4. Rail-to-Rail Inputs The op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4- shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltage (V) V IN Time ( ms/div) V DD =.V G = +V/V FIGURE 4-: The Show No Phase Reversal. The input stage of the op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (V CM ), while the other operates at high V CM. With this topology, the device operates with V CM up to.3 mv above V DD and.3 mv below V SS. The Input Offset Voltage (V OS ) is measured at V CM =V SS.3mV and V DD +.3 mv to ensure proper operation. Input voltages that exceed the absolute maximum voltage (V SS.3V to V DD +.3V) can cause excessive current to flow into or out of the input pins. Current beyond ± m can cause reliability problems. pplications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-. R IN MCP69X V IN + ( Maximum expected V IN ) V DD R IN m V SS ( Minimum expected V IN ) R IN m FIGURE 4-: Resistor (R IN ). 4. Rail-to-Rail Output Input Current Limiting The output voltage range of the op amp is V DD mv (min.) and V SS +mv (max.) when R L =kω is connected to V DD / and V DD =.V. Refer to Figure -6 for more information. 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. s the load capacitance increases, the feedback loop s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. unity-gain buffer (G = +) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > pf when G = +), a small series resistor at the output (R ISO in Figure 4-3) improves the feedback loop s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V IN MCP69X + R ISO C L FIGURE 4-3: Output Resistor, R ISO stabilizes large capacitive loads. Figure 4-4 gives recommended R ISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (C L /G N ), where G N is the circuit's noise gain. For non-inverting gains, G N and the Signal Gain are equal. For inverting gains, G N is + Signal Gain (e.g., - V/V gives G N = + V/V). 4 Microchip Technology Inc. DS8D-page

12 Recommended R ISO (Ω ) G N = V/V G N V/V,, Normalized Load Capacitance; C L /G N (pf) FIGURE 4-4: Recommended R ISO Values for Capacitive Loads. fter selecting R ISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify R ISO 's value until the response is reasonable. ench evaluation and simulations with the SPICE macro model are helpful. 4.4 MCP69X Chip Select (CS) The MCP693 and MCP69 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to.7 µ (typ.) and flows through the CS pin to V SS. When this happens, the amplifier output is put into a high-impedance state. y pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure - shows the output voltage and supply current response to a CS pulse. 4. Cascaded Dual Op mps (MCP69) The MCP69 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin ). This is available because the output of op amp connects to the non-inverting input of op amp, as shown in Figure 4-. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in Low-power mode. Refer to Section 4.3 MCP693/ Chip Select (CS). V IN V IN + 3 FIGURE 4-: /V IN + V IN 6 MCP69 CS Cascaded Gain mplifier. The output of op amp is loaded by the input impedance of op amp, which is typically 3 Ω 6 pf, as specified in the DC specification table (Refer to Section 4.3 Capacitive Loads for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as V SS 3 mv and V DD + 3 mv. However, since the output of op amp is limited to V OL and V OH ( mv from the rails with a kω load), the non-inverting input range of op amp is limited to the common mode input range of V SS + mv and V DD mv. 4.6 Supply ypass With this family of operational amplifiers, the power supply pin (V DD for single supply) should have a local bypass capacitor (i.e.,. µf to. µf) within mm for good high-frequency performance. It also needs a bulk capacitor (i.e., µf or larger) within mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.7 PC Surface Leakage In applications where low input bias current is critical, Printed Circuit oard (PC) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is Ω. V difference would cause p of current to flow, which is greater than the family s bias current at C ( p, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. n example of this type of layout is shown in Figure DS8D-page 4 Microchip Technology Inc.

13 V IN V IN + V SS 4.8 pplication Circuits 4.8. MULTIPLE FEEDCK LOW-PSS FILTER The op amp can be used in activefilter applications. Figure 4-7 shows an inverting, thirdorder, multiple feedback low-pass filter that can be used as an anti-aliasing filter. FIGURE 4-6: for Inverting Gain. Guard Ring Example Guard Ring Layout. For Inverting Gain and Transimpedance mplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (V IN +). This biases the guard ring to the same reference voltage as the op amp (e.g., V DD / or ground). b. Connect the inverting pin (V IN ) to the input with a wire that does not touch the PC surface.. Non-inverting Gain and Unity-Gain uffer: a. Connect the non-inverting pin (V IN +) to the input with a wire that does not touch the PC surface. b. Connect the guard ring to the inverting input pin (V IN ). This biases the guard ring to the common mode input voltage. V IN FIGURE 4-7: Pass Filter. R R C V DD / R 3 C 3 MCP69 Multiple Feedback Low- This filter, and others, can be designed using Microchip s FilterLab software, which is available on our web site ( PHOTODIODE MPLIFIER Figure 4-8 shows a photodiode biased in the photovoltaic mode for high precision. The resistor R converts the diode current I D to the voltage. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode s capacitance (it is not always needed). R 4 C 4 C I D R light V DD / MCP69 FIGURE 4-8: Photodiode mplifier. 4 Microchip Technology Inc. DS8D-page 3

14 4.8.3 CSCDED OP MP PPLICTIONS The MCP69 provides the flexibility of Low-power mode for dual op amps in an 8-pin package. The MCP69 eliminates the added cost and space in battery-powered applications by using two single op amps with Chip Select lines or a -pin device with one Chip Select line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with Chip Select line becomes suitable. The circuits below show possible applications for this device Load Isolation With the cascaded op amp configuration, op amp can be used to isolate the load from op amp. In applications where op amp is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. In this case, op amp can be used as a buffer. R 4 R 3 R R V IN FIGURE 4-: Configuration. MCP69 CS Cascaded Gain Circuit Difference mplifier Figure 4- shows op amp as a difference amplifier with Chip Select. In this configuration, it is recommended to use well-matched resistors (e.g.,.%) to increase the Common Mode Rejection Ratio (CMRR). Op amp can be used for additional gain or as a unitygain buffer to isolate the load from the difference amplifier. MCP69 CS Load R R V IN R V IN R R 4 R 3 MCP69 FIGURE 4-9: uffer. Isolating the Load with a Cascaded Gain Figure 4- shows a cascaded gain circuit configuration with Chip Select. Op amps and are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp is amplified by the gain of op amp and, as shown below: = V IN G G + V OS G G + V OS G FIGURE 4-: CS Difference mplifier Circuit. Where: G = op amp gain G = op amp gain V OS = op amp input offset voltage V OS = op amp input offset voltage Therefore, it is recommended to set most of the gain with op amp and use op amp with relatively small gain (e.g., a unity-gain buffer). DS8D-page 4 4 Microchip Technology Inc.

15 uffered Non-inverting Integrator Figure 4- shows a lossy non-inverting integrator that is buffered and has a Chip Select input. Op amp is configured as a non-inverting integrator. In this configuration, matching the impedance at each input is recommended. R F is used to provide a feedback loop at frequencies << /(πr C ) and makes this a lossy integrator (it has a finite gain at DC). Op amp is used to isolate the load from the integrator. V IN R R C C R F R C = ( R R F )C MCP69 FIGURE 4-: uffered Non-inverting Integrator with Chip Select Inverting Integrator with ctive Compensation and Chip Select Figure 4-3 uses an active compensator (op amp ) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp as a unity-gain buffer to isolate the integration capacitor C from op amp and drives the capacitor with low-impedance source. Since both op amps are matched very well, they provide a high quality integrator. CS Second-Order MF Low-Pass Filter with an Extra Pole-Zero Pair Figure 4-4 is a second-order multiple feedback lowpass filter with Chip Select. Use the FilterLab software from Microchip to determine the R and C values for the op amp s second-order filter. Op amp can be used to add a pole-zero pair using C 3, R 6 and R 7. V IN R 3 R R C R 4 FIGURE 4-4: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair Figure 4- is a second-order, Sallen-Key low-pass filter with Chip Select. Use the FilterLab software from Microchip to determine the R and C values for the op amp s second-order filter. Op amp can be used to add a pole-zero pair using C 3, R and R 6. R R C R R 6 C 3 MCP69 CS R R 7 C 3 VOUT V IN R C V IN R 4 R 3 C MCP69 R 6 C CS CS MCP69 FIGURE 4-: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-3: Compensation. Integrator Circuit with ctive 4 Microchip Technology Inc. DS8D-page

16 Capacitorless Second-Order Low-Pass filter with Chip Select The low-pass filter shown in Figure 4-6 does not require external capacitors and uses only three external resistors; the op amp s GWP sets the corner frequency. R and R are used to set the circuit gain and R 3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R 3 ). Note that the amplifier bandwidth varies greatly over temperature and process. However, this configuration provides a low cost solution for applications with high bandwidth requirements. V IN V REF R R R 3 MCP69 CS FIGURE 4-6: Capacitorless Second-Order Low-Pass Filter with Chip Select.. DESIGN TOOLS Microchip provides the basic design tools needed for the family of op amps.. SPICE Macro Model The latest SPICE macro model for the op amps is available on our web site at This model is intended to be an initial design tool that works well in the op amp s linear region of operation at room temperature. See the macro model file for information on its capabilities. ench testing is a very important part of any design and cannot be replaced with simulations. lso, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.. FilterLab Software Microchip s FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. vailable at no cost from our web site at the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS8D-page 6 4 Microchip Technology Inc.

17 6. PCKGING INFORMTION 6. Package Marking Information -Lead SOT-3 (MCP69 and MCP69R) Example: XXNN Device Code MCP69 CJNN MCP69R EVNN Note: pplies to -Lead SOT-3 CJ 6-Lead SOT-3 (MCP683) Example: XXNN CM 8-Lead MSOP XXXXXX YWWNNN Example: 69E Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP69 E/P Lead SOIC ( mil) Example: XXXXXXXX XXXXYYWW NNN MCP69 E/SN436 6 Legend: XX...X Customer specific information* YY Year code (last digits of calendar year) WW Week code (week of January is week ) NNN lphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 4 Microchip Technology Inc. DS8D-page 7

18 Package Marking Information (Continued) 4-Lead PDIP (3 mil) (MCP694) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP694-E/P Lead SOIC ( mil) (MCP694) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP694ESL Lead TSSOP (MCP694) Example: XXXXXX YYWW NNN 694EST DS8D-page 8 4 Microchip Technology Inc.

19 -Lead Plastic Small Outline Transistor (OT) (SOT-3) E E p p D n α c β L φ Units Dimension Limits Number of Pins n Pitch p Outside lead pitch (basic) p Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β *Controlling Parameter MIN INCHES* NOM MX MILLIMETERS MIN NOM Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.7mm) per side. MX EIJ Equivalent: SC-74 Drawing No. C4-9 4 Microchip Technology Inc. DS8D-page 9

20 6-Lead Plastic Small Outline Transistor (CH) (SOT-3) E E p D n α c φ β L Units Dimension Limits Number of Pins n Pitch p Outside lead pitch (basic) p Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β *Controlling Parameter MIN INCHES* NOM MX MILLIMETERS MIN NOM Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.7mm) per side. MX JEIT (formerly EIJ) equivalent: SC-74 Drawing No. C4- DS8D-page 4 Microchip Technology Inc.

21 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E p n D α c φ β (F) L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MX MIN NOM Number of Pins n 8 8 Pitch p.6 SC.6 SC Overall Height Molded Package Thickness Standoff Overall Width E.93 TYP. 4.9 SC Molded Package Width E.8 SC 3. SC Overall Length D.8 SC 3. SC Foot Length L Footprint (Reference) F.37 REF.9 REF Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top Mold Draft ngle ottom α β *Controlling Parameter Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.4mm) per side. JEDEC Equivalent: MO-87 Drawing No. C4- MX Microchip Technology Inc. DS8D-page

22 8-Lead Plastic Dual In-line (P) 3 mil (PDIP) E D n α E c L β e p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 8 8 Pitch p..4 Top to Seating Plane Molded Package Thickness ase to Seating Plane..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width Lower Lead Width Overall Row Spacing e Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.4mm) per side. JEDEC Equivalent: MS- Drawing No. C4-8 DS8D-page 4 Microchip Technology Inc.

23 8-Lead Plastic Small Outline (SN) Narrow, mil (SOIC) E E p D n 4 h α c φ β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 8 8 Pitch p..7 Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.4mm) per side. JEDEC Equivalent: MS- Drawing No. C4-7 4 Microchip Technology Inc. DS8D-page 3

24 4-Lead Plastic Dual In-line (P) 3 mil (PDIP) E D n α E c L β e p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 4 4 Pitch p..4 Top to Seating Plane Molded Package Thickness ase to Seating Plane..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width Lower Lead Width Overall Row Spacing e Mold Draft ngle Top α Mold Draft ngle ottom * Controlling Parameter Significant Characteristic β Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.4mm) per side. JEDEC Equivalent: MS- Drawing No. C4- DS8D-page 4 4 Microchip Technology Inc.

25 4-Lead Plastic Small Outline (SL) Narrow, mil (SOIC) E E p D n 4 h α c β L φ Units INCHES* MILLIMETERS Dimension Limits MIN NOM MX MIN NOM MX Number of Pins n 4 4 Pitch p..7 Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.4mm) per side. JEDEC Equivalent: MS- Drawing No. C4-6 4 Microchip Technology Inc. DS8D-page

26 4-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) p E E D n α c φ β L Units Dimension Limits Number of Pins n Pitch p Overall Height Molded Package Thickness Standoff Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot ngle φ Lead Thickness c Lead Width Mold Draft ngle Top α Mold Draft ngle ottom β * Controlling Parameter Significant Characteristic MIN INCHES NOM MX MIN MILLIMETERS* NOM 4.6 Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.7mm) per side. JEDEC Equivalent: MO-3 Drawing No. C MX DS8D-page 6 4 Microchip Technology Inc.

27 PPENDIX : REVISION HISTORY Revision (June 3) Original data sheet release. Revision (October 3) Revision C (June 4) Revision D (December 4) The following is the list of modifications:. dded SOT-3- packages for the MCP69 and MCP69R single op amps.. dded SOT-3-6 package for the MCP693 single op amp. 3. dded Section 3. Pin Descriptions. 4. Corrected application circuits (Section 4.8 pplication Circuits ).. dded SOT-3- and SOT-3-6 packages and corrected package marking information (Section 6. Packaging Information ). 6. dded ppendix : Revision History. 4 Microchip Technology Inc. DS8D-page 7

28 NOTES: DS8D-page 8 4 Microchip Technology Inc.

29 PRODUCT IDENTIFICTION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PRT NO. X /XX Device Temperature Range Package Device: MCP69: Single Op mp MCP69T: Single Op mp (Tape and Reel) (SOIC, MSOP, SOT-3-) MCP69RT: Single Op mp (Tape and Reel) (SOT-3-) MCP69: Dual Op mp MCP69T: Dual Op mp (Tape and Reel) (SOIC, MSOP) MCP693: Single Op mp with Chip Select MCP693T: Single Op mp with Chip Select (Tape and Reel) (SOIC, MSOP, SOT-3-6) MCP694: Quad Op mp MCP694T: Quad Op mp (Tape and Reel) (SOIC, TSSOP) MCP69: Dual Op mp with Chip Select MCP69T: Dual Op mp with Chip Select (Tape and Reel) (SOIC, MSOP) Temperature Range: E = -4 C to + C Package: OT = Plastic Small Outline Transistor (SOT-3), -lead (MCP69, MCP69R) CH = Plastic Small Outline Transistor (SOT-3), 6-lead (MCP693) MS = Plastic MSOP, 8-lead P = Plastic DIP (3 mil ody), 8-lead, 4-lead SN = Plastic SOIC, ( mil ody), 8-lead SL = Plastic SOIC ( mil ody), 4-lead ST = Plastic TSSOP (4.4 mm ody), 4-lead Examples: a) MCP69-E/SN: Extended Temperature, 8LD SOIC package. b) MCP69-E/MS: Extended Temperature, 8LD MSOP package. c) MCP69-E/P: Extended Temperature, 8LD PDIP package. d) MCP69T-E/OT: Tape and Reel, Extended Temperature, LD SOT-3 package. a) MCP69-E/SN: Extended Temperature, 8LD SOIC package. b) MCP69-E/MS: Extended Temperature, 8LD MSOP package. c) MCP69-E/P: Extended Temperature, 8LD PDIP package. d) MCP69T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. a) MCP693-E/SN: Extended Temperature, 8LD SOIC package. b) MCP693-E/MS: Extended Temperature, 8LD MSOP package. c) MCP693-E/P: Extended Temperature, 8LD PDIP package. d) MCP693T-E/CH: Tape and Reel, Extended Temperature, 6LD SOT-3 package. a) MCP694-E/P: Extended Temperature, 4LD PDIP package. b) MCP694T-E/SL: Tape and Reel, Extended Temperature, 4LD SOIC package. c) MCP694-E/SL: Extended Temperature, 4LD SOIC package. d) MCP694-E/ST: Extended Temperature, 4LD TSSOP package. a) MCP69-E/SN: Extended Temperature, 8LD SOIC package. b) MCP69-E/MS: Extended Temperature, 8LD MSOP package. c) MCP69-E/P: Extended Temperature, 8LD PDIP package. d) MCP69T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:. Your local Microchip sales office. The Microchip Worldwide Site ( Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site ( to receive the most current information on our products. 4 Microchip Technology Inc. DS8D-page 9

30 NOTES: DS8D-page 3 4 Microchip Technology Inc.

31 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. ll of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. ttempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright ct. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that ct. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MKES NO REPRESENTTIONS OR WR- RNTIES OF NY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORL, STTUTORY OR OTHERWISE, RELTED TO THE INFORMTION, INCLUDING UT NOT LIMITED TO ITS CONDITION, QULITY, PERFORMNCE, MERCHNTILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, ccuron, dspic, KEELOQ, microid, MPL, PIC, PICmicro, PICSTRT, PRO MTE, PowerSmart, rfpic, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.. and other countries. mplab, FilterLab, Migratable Memory, MXDEV, MXL, PICMSTER, SEEVL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.. nalog-for-the-digital ge, pplication Maestro, dspicdem, dspicdem.net, dspicworks, ECN, ECONOMONITOR, FanSense, FlexROM, fuzzyl, In-Circuit Serial Programming, ICSP, ICEPIC, MPSM, MPLI, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICL, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfl, rfpicdem, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.. ll other trademarks mentioned herein are property of their respective companies. 4, Microchip Technology Incorporated, Printed in the U.S.., ll Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-6949: quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, rizona and Mountain View, California in October 3. The Company s quality system processes and procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9: certified. 4 Microchip Technology Inc. DS8D-page 3

32 WORLDWIDE SLES ND SERVICE MERICS Corporate Office 3 West Chandler lvd. Chandler, Z Tel: Fax: Technical Support: Web ddress: tlanta lpharetta, G Tel: Fax: oston Westford, M Tel: Fax: Chicago Itasca, IL Tel: Fax: Dallas ddison, TX Tel: Fax: Detroit Farmington Hills, MI Tel: Fax: Kokomo Kokomo, IN Tel: Fax: Los ngeles Mission Viejo, C Tel: Fax: San Jose Mountain View, C Tel: Fax: Toronto Mississauga, Ontario, Canada Tel: Fax: SI/PCIFIC ustralia - Sydney Tel: Fax: China - eijing Tel: Fax: China - Chengdu Tel: Fax: China - Fuzhou Tel: Fax: China - Hong Kong SR Tel: 8-4- Fax: China - Shanghai Tel: Fax: China - Shenyang Tel: Fax: China - Shenzhen Tel: Fax: China - Shunde Tel: Fax: China - Qingdao Tel: Fax: SI/PCIFIC India - angalore Tel: Fax: India - New Delhi Tel: Fax: Japan - Kanagawa Tel: Fax: Korea - Seoul Tel: Fax: or Singapore Tel: Fax: Taiwan - Kaohsiung Tel: Fax: Taiwan - Taipei Tel: Fax: Taiwan - Hsinchu Tel: Fax: EUROPE ustria - Weis Tel: Fax: Denmark - allerup Tel: Fax: France - Massy Tel: Fax: Germany - Ismaning Tel: Fax: Italy - Milan Tel: Fax: Netherlands - Drunen Tel: Fax: England - erkshire Tel: Fax: //4 DS8D-page 3 4 Microchip Technology Inc.

33 Mouser Electronics uthorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: MCP693-E/SN MCP694-E/SL MCP694-E/ST MCP693-E/MS MCP69-E/P MCP69-E/SN MCP69-E/MS MCP694-E/P MCP69-E/P MCP69-E/SN MCP69T-E/SN MCP69T-E/MS MCP69T-E/SN MCP693T- E/SN MCP694T-E/SL MCP69T-E/MS MCP693T-E/MS MCP694T-E/ST MCP693-E/P MCP69RT-E/OT MCP69T-E/OT MCP693T-E/CH