MCP6241/2/4. 50 µa, 550 khz Rail-to-Rail Op Amp. Description. Features. Applications. Package Types. Available Tools. Typical Application

Transcription

1 µa, khz Rail-to-Rail Op Amp Features Gain Bandwidth Product: khz (typ.) Supply Current: I Q = µa (typ.) Supply Voltage:.8V to.v Rail-to-Rail Input/Output Extended Temperature Range: -4 C to +2 C Available in -pin SC-7 and SOT-23 packages Applications Automotive Portable Equipment Photodiode (Transimpedance) Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Available Tools SPICE Macro Models (at FilterLab Software (at Typical Application V IN2 V IN R G2 R G RF Description The Microchip Technology Inc. MCP624/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP624/2/4 has a khz Gain Bandwidth Product (GBWP) and 68 (typ.) phase margin. This family operates from a single supply voltage as low as.8v, while drawing µa (typ.) quiescent current. In addition, the MCP624/2/4 family supports rail-to-rail input and output swing, with a common mode input voltage range of V DD + 3 mv to V SS 3 mv. These op amps are designed in one of Microchip s advanced CMOS processes. Package Types V OUT V SS 2 V IN + 3 V OUT V DD V IN MCP624 SOT MCP624R SOT V DD 4 V IN V SS 4 V IN MCP624 PDIP, SOIC, MSOP NC V IN 2 V IN + 3 V SS NC V DD 6 V OUT NC MCP6242 PDIP, SOIC, MSOP 8 V DD _ V INA V INA V _ INB V INB + V OUTA V SS V OUTB V DD R X R Y R Z MCP624 + V OUT MCP624U SC-7-, SOT-23- V IN + V SS 2 V IN 3 + V DD 4 V OUT 4 MCP6244 PDIP, SOIC, TSSOP V OUTA 4 V OUTD V INA V IND V INA V IND + V DD V SS Summing Amplifier Circuit V INB + V INC + V INB V OUTB V INC V OUTC 2 Microchip Technology Inc. DS2882C-page

2 . ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings V DD V SS...7.V All Inputs and Outputs... V SS.3V to V DD +.3V Difference Input Voltage... V DD V SS Output Short Circuit Current...continuous Current at Input Pins...±2 ma Current at Output and Supply Pins...±3 ma Storage Temperature...-6 C to + C Maximum Junction Temperature (T J )...+ C ESD Protection On All Pins (HBM;MM)... 4 kv; 3V Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, T A = +2 C, V DD = +.8V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2 and V OUT V DD /2. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V OS mv V CM = V SS Extended Temperature V OS mv T A = -4 C to +2 C, V CM = V SS (Note) Input Offset Drift with Temperature ΔV OS /ΔT A ±3. µv/ C T A = -4 C to +2 C, V CM = V SS Power Supply Rejection PSRR 83 db V CM = V SS Input Bias Current and Impedance Input Bias Current: I B ±. pa At Temperature I B 2 pa T A = +8 C At Temperature I B pa T A = +2 C Input Offset Current I OS ±. pa Common Mode Input Impedance Z CM 3 6 Ω pf Differential Input Impedance Z DIFF 3 3 Ω pf Common Mode Common Mode Input Range V CMR V SS.3 V DD +.3 V Common Mode Rejection Ratio CMRR 6 7 db V CM = -.3V to.3v, V DD = V Open-Loop Gain DC Open-Loop Gain (large signal) Output A OL 9 db V OUT =.3V to V DD.3V, V CM =V SS Maximum Output Voltage Swing V OL, V OH V SS + 3 V DD 3 mv R L = kω,.v Output Overdrive Output Short-Circuit Current I SC ±6 ma V DD =.8V I SC ±23 ma V DD =.V Power Supply Supply Voltage V DD.8. V Quiescent Current per Amplifier I Q 3 7 µa I O =, V CM = V DD.V Note: The SC-7 package is only tested at +2 C. DS2882C-page 2 2 Microchip Technology Inc.

3 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, T A = +2 C, V DD = +.8 to.v, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2 and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP khz Phase Margin PM 68 G = + Slew Rate SR.3 V/µs Noise Input Noise Voltage E ni µv P-P f =. Hz to Hz Input Noise Voltage Density e ni 4 nv/ Hz f = khz Input Noise Current Density i ni.6 fa/ Hz f = khz TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V DD = +.8V to +.V and V SS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Extended Temperature Range T A C Operating Temperature Range T A C (Note) Storage Temperature Range T A -6 + C Thermal Package Resistances Thermal Resistance, L-SC7 θ JA 33 C/W Thermal Resistance, L-SOT-23 θ JA 26 C/W Thermal Resistance, 8L-MSOP θ JA 26 C/W Thermal Resistance, 8L-PDIP θ JA 8 C/W Thermal Resistance, 8L-SOIC θ JA 63 C/W Thermal Resistance, 4L-PDIP θ JA 7 C/W Thermal Resistance, 4L-SOIC θ JA 2 C/W Thermal Resistance, 4L-TSSOP θ JA C/W Note: The internal Junction Temperature (T J ) must not exceed the Absolute Maximum specification of + C. 2 Microchip Technology Inc. DS2882C-page 3

4 2. TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T A = +2 C, V DD = +.8V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2 and C L = 6 pf. Percentage of Occurrences 2% 8% 6% 4% 2% % 8% 6% 4% 2% % 63 Samples V CM = V SS Input Offset Voltage (mv) 3 4 CMRR, PSRR (db) PSRR (V CM = V SS ) CMRR (V CM = -.3V to +.3V, V DD =.V) Ambient Temperature ( C) FIGURE 2-: Input Offset Voltage. FIGURE 2-4: Temperature. CMRR, PSRR vs. Ambient PSRR, CMRR (db) Open-Loop Gain (db) Phase Gain R L =. k V CM = V DD /2 PSRR- 9 8 CMRR 7 PSRR k k k.e+.e+2.e+3.e+4.e+ Frequency (Hz) -2-2.E-..E+.E+.E+.E+ k.e+ k k.e+.e+ M M.E+ Frequency 2 3 (Hz) Open-Loop Phase ( ) FIGURE 2-2: Frequency. PSRR, CMRR vs. FIGURE 2-: Frequency. Open-Loop Gain, Phase vs. Percentage of Occurrences 2% 2% % % % % 8 Samples V CM = V DD /2 T A = +8 C Percentage of Occurrences 3% 2% 2% % % % % 8 Samples V CM = V DD /2 T A = +2 C Input Bias Current (pa) Input Bias Current (na) FIGURE 2-3: Input Bias Current at +8 C. FIGURE 2-6: Input Bias Current at +2 C. DS2882C-page 4 2 Microchip Technology Inc.

5 Note: Unless otherwise indicated, T A = +2 C, V DD = +.8V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2 and C L = 6 pf. Input Noise Voltage Density (nv/ Hz),,. k k k.e-.e+.e+.e+.e+.e+.e+ Frequency 2 (Hz) 3 4 Percentage of Occurrences 2% 8% 6% 4% 2% % 8% 6% 4% 2% % 628 Samples V CM = V SS T A = -4 C to +2 C Input Offset Voltage Drift (µv/ C) FIGURE 2-7: vs. Frequency. Input Noise Voltage Density FIGURE 2-: Input Offset Voltage Drift. Input Offset Voltage (µv) T A = -4 C T A = +2 C T A = +8 C T A = +2 C Common Mode Input Voltage (V) V DD =.8V Input Offset Voltage (µv) 7 V CM = V SS 6 6 V DD =.V 4 V DD =.8V Output Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at V DD =.8V. FIGURE 2-: Output Voltage. Input Offset Voltage vs. Input Offset Voltage (µv) T A = -4 C T A = +2 C T A = +8 C T A = +2 C Common Mode Input Voltage (V) V DD =.V FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at V DD =.V. Short Circuit Current (ma) I SC -I SC Power Supply Voltage (V) T A = +2 C T A = +8 C T A = +2 C T A = -4 C FIGURE 2-2: Output Short-Circuit Current vs. Ambient Temperature. 2 Microchip Technology Inc. DS2882C-page

6 Note: Unless otherwise indicated, T A = +2 C, V DD = +.8V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2 and C L = 6 pf. Slew Rate (V/µs)..4 V DD =.V.4 Falling Edge V DD =.8V. Rising Edge Ambient Temperature ( C) Output Voltage ( mv/div) Time ( µs/div) G = + V/V R L = k FIGURE 2-3: Temperature. Slew Rate vs. Ambient FIGURE 2-6: Pulse Response. Small-Signal, Non-Inverting Output Voltage Headroom (mv), V DD V OH V OL V SS.E-2 µ.e- µ.e+ m.e+ m Output Current Magnitude (A) Output Voltage (V) Time ( µs/div) V DD =.V G = + V/V FIGURE 2-4: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-7: Pulse Response. Large-Signal, Non-Inverting Max. Output Voltage Swing (V P-P ) V DD =.V V DD =.8V. k k k M.E+3.E+4.E+.E+6 Frequency (Hz) Quiescent Current per Amplifier (µa) 8 V CM =.9V DD T A = +2 C T A = +8 C 2 T A = +2 C T A = -4 C Power Supply Voltage (V) FIGURE 2-: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-8: Quiescent Current vs. Power Supply Voltage. DS2882C-page 6 2 Microchip Technology Inc.

7 3. PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3- (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-: MCP624 (PDIP, SOIC, MSOP) TABLE 3-2: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP624 (SOT-23-) MCP624R (SOT-23-) MCP624U (SOT-23-) Symbol PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS Description 6 4 V OUT Analog Output V IN Inverting Input V IN + Non-inverting Input 7 2 V DD Positive Power Supply V SS Negative Power Supply,, 8 NC No Internal Connection MCP6242 MCP6244 Symbol Description V OUTA Analog Output (op amp A) 2 2 V INA Inverting Input (op amp A) 3 3 V INA + Non-inverting Input (op amp A) 8 4 V DD Positive Power Supply V INB + Non-inverting Input (op amp B) 6 6 V INB Inverting Input (op amp B) 7 7 V OUTB Analog Output (op amp B) 8 V OUTC Analog Output (op amp C) 9 V INC Inverting Input (op amp C) V INC + Non-inverting Input (op amp C) 4 V SS Negative Power Supply 2 V IND + Non-inverting Input (op amp D) 3 V IND Inverting Input (op amp D) 4 V OUTD Analog Output (op amp D) 3. Analog Outputs The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 Power Supply (V SS and V DD ) The positive power supply (V DD ) is.8v to.v higher than the negative power supply (V SS ). For normal operation, the other pins are between V SS and V DD. Typically, these parts are used in a single-(positive) supply configuration. In this case, V SS is connected to ground and V DD is connected to the supply. V DD will need a local bypass capacitor (typically. µf to. µf) within 2 mm of the V DD pin. These parts can share a bulk capacitor (typically µf to µf) with other nearby analog parts; it needs to be within mm of the V DD pin. 2 Microchip Technology Inc. DS2882C-page 7

8 4. APPLICATION INFORMATION The MCP624/2/4 family of op amps is manufactured using Microchip s state-of-the-art CMOS process and is specifically designed for low-power and generalpurpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP624/2/4 ideal for battery-powered applications. 4. Rail-to-Rail Inputs The MCP624/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4- shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltage (V) FIGURE 4-: Phase Reversal. V IN V OUT Time ( ms/div) V DD =.V G = +2 V/V The MCP624/2/4 Show No The input stage of the MCP624/2/4 op amps use two differential input stages in parallel. One operates at low common mode input voltage (V CM ) and the other at high V CM. With this topology, the device operates with V CM up to 3 mv above V DD and 3 mv below V SS. The Input Offset Voltage is measured at V CM =V SS 3 mv and V DD + 3 mv to ensure proper operation. Input voltages that exceed the input voltage range (V SS.3V to V DD +.3V at 2 C) can cause excessive current to flow into or out of the input pins. Current beyond ±2 ma can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-2. R IN MCP624X V OUT V IN + FIGURE 4-2: Resistor (R IN ). ( Maximum expected V IN ) V DD ma V SS ( Minimum expected V IN ) R IN ma R IN 4.2 Rail-to-Rail Output Input Current-Limiting The output voltage range of the MCP624/2/4 op amps is V DD 3 mv (max.) and V SS + 3 mv (min.) when R L =kω is connected to V DD /2 and V DD =.V. Refer to Figure 2-4 for more information. 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage-feedback op amps. As the load capacitance increases, the feedback loop s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 7 pf when G = +), a small series resistor at the output (R ISO in Figure 4-3) improves the feedback loop s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V IN MCP624X + R ISO C L V OUT FIGURE 4-3: Output resistor, R ISO stabilizes large capacitive loads. Figure 4-4 gives recommended R ISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (C L /G N ), where G N is the circuit s noise gain. For non-inverting gains, G N and the signal gain are equal. For inverting gains, G N is + Signal Gain (e.g., V/V gives G N = +2 V/V). DS2882C-page 8 2 Microchip Technology Inc.

9 .E+4 k Recommended R ISO ( ).E+3 k G N = + V/V G N +2 V/V.E+2.E+ p.e+2 p.e+3 n.e+4 n Normalized Load Capacitance; C L /G N (F) FIGURE 4-4: Recommended R ISO Values for Capacitive Loads. After selecting R ISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP624/2/4 SPICE macro model are very helpful. Modify R ISO s value until the response is reasonable. 4.6 PCB Surface Leakage In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 2 Ω. A V difference would cause pa of current to flow, which is greater than the MCP624/2/4 family s bias current at 2 C ( pa, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-6. V IN - V IN + V SS 4.4 Supply Bypass With this op amp, the power supply pin (V DD for single-supply) should have a local bypass capacitor (i.e.,. µf to. µf) within 2 mm for good highfrequency performance. It can use a bulk capacitor (i.e., µf or larger) within mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts. 4. Unused Op Amps An unused op amp in a quad package (MCP6244) should be configured as shown in Figure 4-. Both circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage, and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of components, but may draw a little more supply current for the unused op amp. ¼ MCP6244 (A) ¼ MCP6244 (B) FIGURE 4-6: for Inverting Gain. Guard Ring Example Guard Ring Layout. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (V IN +) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (V IN ). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (V IN +). This biases the guard ring to the same reference voltage as the op amp (e.g., V DD /2 or ground). b. Connect the inverting pin (V IN ) to the input with a wire that does not touch the PCB surface. V DD V DD V DD FIGURE 4-: Unused Op Amps. 2 Microchip Technology Inc. DS2882C-page 9

10 4.7 Application Circuits 4.7. MATCHING THE IMPEDANCE AT THE INPUTS To minimize the effect of offset voltage in an amplifier circuit, the impedances at the inverting and noninverting inputs need to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-7 shows a summing amplifier circuit. V IN2 V IN R X R Y V DD FIGURE 4-7: R G2 R G R Z MCP624X + V OUT Summing Amplifier Circuit. To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting V IN, V IN2 and V OUT to ground. In this case, R G, R G2 and R F are in parallel. The total resistance at the inverting input is: R VIN = RF R G R G2 R F Where: R VIN = total resistance at the inverting input COMPENSATING FOR THE PARASITIC CAPACITANCE In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-8 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (C PARA, which includes the common mode capacitance of 6 pf, typical) and large R F and R G, the frequency response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit instability. V AC V DC R G C PARA FIGURE 4-8: Effect of Parasitic Capacitance at the Input. + MCP624X One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding C F in parallel with the feedback resistor (R F ). C F needs to be selected so that the ratio C PARA :C F is equal to the ratio of R F :R G. R F C F V OUT R G C F = C PARA R F At the non-inverting input, V DD is the only voltage source. When V DD is set to ground, both R X and R Y are in parallel. The total resistance at the non-inverting input is: R VIN + = R Z R X R Y Where: R VIN + = total resistance at the inverting input To minimize offset voltage and increase circuit accuracy, the resistor values need to meet the condition: R VIN + = R VIN DS2882C-page 2 Microchip Technology Inc.

11 . DESIGN TOOLS Microchip provides the basic design tools needed for the MCP624/2/4 family of op amps.. SPICE Macro Model The latest SPICE macro model for the MCP624/2/4 op amps is available on our web site at This model is intended to be an initial design tool that works well in the op amp s linear region of operation at room temperature. See the macro model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves..2 FilterLab Software Microchip s FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site at the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 2 Microchip Technology Inc. DS2882C-page

12 6. PACKAGING INFORMATION 6. Package Marking Information -Lead SC-7 (MCP624U Only) Example: XXN (Front) YWW (Back) OR XXNN AT2 (Front) 46 (Back) OR AT2 -Lead SOT-23 4 XXNN Lead MSOP XXXXXX YWWNNN Device Code MCP624 BQNN MCP624R BRNN MCP624U BSNN Note: Applies to -Lead SOT-23. Example: 4 BQ2 2 3 Example: 6242E Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6242 E/P e3 ^^ Lead SOIC ( mil) Example: XXXXXXXX XXXXYYWW NNN MCP6242E SN^^ e Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January is week ) NNN e3 Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS2882C-page 2 2 Microchip Technology Inc.

13 Package Marking Information (Continued) 4-Lead PDIP (3 mil) (MCP6244) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP6244 E/P^^ e Lead SOIC ( mil) (MCP6244) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6244 E/SL^^3 e Lead TSSOP (MCP6244) Example: XXXXXXXX YYWW NNN 6244E Microchip Technology Inc. DS2882C-page 3

14 -Lead Plastic Small Outline Transistor Package (LT) (SC-7) E E D p B n Q c A2 A A L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p.26 (BSC).6 (BSC) Overall Height A Molded Package Thickness A Standoff A..4.. Overall Width E Molded Package Width E Overall Length D Foot Length L Top of Molded Pkg to Lead Shoulder Q Lead Thickness c Lead Width B *Controlling Parameter Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.27mm) per side. JEITA (EIAJ) Standard: SC-7 Drawing No. C4-6 DS2882C-page 4 2 Microchip Technology Inc.

15 -Lead Plastic Small Outline Transistor (OT) (SOT23) E E p B p D n α c A A2 β L φ A Units Dimension Limits Number of Pins n Pitch p Outside lead pitch (basic) p Overall Height A Molded Package Thickness A2 Standoff A Overall Width E Molded Package Width E Overall Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β *Controlling Parameter MIN INCHES* NOM MAX MILLIMETERS MIN NOM Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.27mm) per side. MAX EIAJ Equivalent: SC-74A Drawing No. C4-9 2 Microchip Technology Inc. DS2882C-page

16 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E p B n 2 D α c φ A A A2 β (F) L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM Number of Pins n 8 8 Pitch p.26 BSC.6 BSC Overall Height A Molded Package Thickness A Standoff A Overall Width E.93 TYP. 4.9 BSC Molded Package Width E.8 BSC 3. BSC Overall Length D.8 BSC 3. BSC Foot Length L Footprint (Reference) F.37 REF.9 REF Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α - - Mold Draft Angle Bottom β - - *Controlling Parameter Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.24mm) per side. JEDEC Equivalent: MO-87 Drawing No. C4- MAX DS2882C-page 6 2 Microchip Technology Inc.

17 8-Lead Plastic Dual In-line (P) 3 mil (PDIP) E 2 D n α E A A2 c A L β eb B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p. 2.4 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS- Drawing No. C4-8 2 Microchip Technology Inc. DS2882C-page 7

18 8-Lead Plastic Small Outline (SN) Narrow, mil (SOIC) E E p 2 D B n 4 h α c A A2 φ β L A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p..27 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α 2 2 Mold Draft Angle Bottom β 2 2 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS-2 Drawing No. C4-7 DS2882C-page 8 2 Microchip Technology Inc.

19 4-Lead Plastic Dual In-line (P) 3 mil (PDIP) E D 2 n α E A A2 c L β eb A B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p. 2.4 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic β Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS- Drawing No. C4-2 Microchip Technology Inc. DS2882C-page 9

20 4-Lead Plastic Small Outline (SL) Narrow, mil (SOIC) E E p D 2 B n 4 h α c A A2 β L φ A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p..27 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α 2 2 Mold Draft Angle Bottom β 2 2 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS-2 Drawing No. C4-6 DS2882C-page 2 2 Microchip Technology Inc.

21 4-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) p E E D B n 2 A α c φ β L A A2 Units Dimension Limits Number of Pins n Pitch p Overall Height A Molded Package Thickness A2 Standoff A Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic MIN INCHES NOM MAX MIN MILLIMETERS* NOM 4.6 Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.27mm) per side. JEDEC Equivalent: MO-3 Drawing No. C MAX Microchip Technology Inc. DS2882C-page 2

22 NOTES: DS2882C-page 22 2 Microchip Technology Inc.

23 APPENDIX A: REVISION HISTORY Revision C (March 2) The following is the list of modifications:. Added the MCP6244 quad op amp. 2. Re-compensated parts. Specifications that change are: Gain Bandwidth Product (BWP) and Phase Margin (PM) in AC Electrical Characteristics table. 3. Corrected plots in Section 2. Typical Performance Curves. 4. Added Section 3. Pin Descriptions.. Added new SC-7 package markings. Added PDIP-4, SOIC-4, and TSSOP-4 packages and corrected package marking information (Section 6. Packaging Information ). 6. Added Appendix A: Revision History. Revision B (August 24) Revision A (March 24) Original Release of this Document. 2 Microchip Technology Inc. DS2882C-page 23

24 NOTES: DS2882C-page 24 2 Microchip Technology Inc.

25 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X -X /XX Device Tape and Reel and/or Alternate Pinout Temperature Range Package Device: MCP624: Single Op Amp (MSOP, PDIP, SOIC) MCP624T: Single Op Amp (Tape and Reel) (MSOP, SOIC, SOT-23) MCP624RT: Single Op Amp (Tape and Reel) (SOT-23) MCP624UT: Single Op Amp (Tape and Reel) (SC-7, SOT-23) MCP6242: Dual Op Amp MCP6242T: Dual Op Amp (Tape and Reel) (MSOP, SOIC) MCP6244: Quad Op Amp MCP6244T: Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Examples: a) MCP624-E/SN: Extended Temp., 8LD SOIC package. b) MCP624-E/MS: Extended Temp., 8LD MSOP package. c) MCP624-E/P: Extended Temp., 8LD PDIP package. d) MCP624RT-E/OT: Tape and Reel, Extended Temp., LD SOT-23 package e) MCP624UT-E/OT: Tape and Reel, Extended Temp., LD SOT-23 package. f) MCP624UT-E/LT: Tape and Reel, Extended Temp., LD SC-7 package. Temperature Range: E = -4 C to +2 C Package: LT = Plastic Package (SC-7), -lead (MCP624U only) MS = Plastic Micro Small Outline (MSOP), 8-lead P = Plastic DIP (3 mil Body), 8-lead, 4-lead OT = Plastic Small Outline Transistor (SOT-23), -lead (MCP624, MCP624R, MCP624U) SN = Plastic SOIC ( mil Body), 8-lead SL = Plastic SOIC ( mil Body), 4-lead ST = Plastic TSSOP (4.4 mil Body), 4-lead a) MCP6242-E/SN: Extended Temp., 8LD SOIC package. b) MCP6242-E/MS: Extended Temp., 8LD MSOP package. c) MCP6242-E/P: Extended Temp., 8LD PDIP package. d) MCP6242T-E/SN: Tape and Reel, Extended Temp., 8LD SOIC package. a) MCP6244-E/P: Extended Temp., 4LD PDIP package. b) MCP6244-E/SL: Extended Temp., 4LD SOIC package. c) MCP6244-E/ST: Extended Temp., 4LD TSSOP package. d) MCP6244T-E/SL: Tape and Reel, Extended Temp., 4LD SOIC package. e) MCP6244T-E/ST: Tape and Reel, Extended Temp., 4LD TSSOP package. 2 Microchip Technology Inc. DS2882C-page 2

26 NOTES: DS2882C-page 26 2 Microchip Technology Inc.

27 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KEELOQ, microid, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfpic, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dspicdem, dspicdem.net, dspicworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rflab, rfpicdem, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-6949:22 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 23. The Company s quality system processes and procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9:2 certified. 2 Microchip Technology Inc. DS2882C-page 27

28 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 23 West Chandler Blvd. Chandler, AZ Tel: Fax: Technical Support: Web Address: Atlanta Alpharetta, GA Tel: Fax: Boston Westborough, MA Tel: Fax: Chicago Itasca, IL Tel: Fax: Dallas Addison, TX Tel: Fax: Detroit Farmington Hills, MI Tel: Fax: Kokomo Kokomo, IN Tel: Fax: Los Angeles Mission Viejo, CA Tel: Fax: San Jose Mountain View, CA Tel: Fax: Toronto Mississauga, Ontario, Canada Tel: Fax: ASIA/PACIFIC Australia - Sydney Tel: Fax: China - Beijing Tel: Fax: China - Chengdu Tel: Fax: China - Fuzhou Tel: Fax: China - Hong Kong SAR Tel: Fax: China - Shanghai Tel: Fax: China - Shenyang Tel: Fax: China - Shenzhen Tel: Fax: China - Shunde Tel: Fax: China - Qingdao Tel: Fax: ASIA/PACIFIC India - Bangalore Tel: Fax: India - New Delhi Tel: Fax: Japan - Kanagawa Tel: Fax: Korea - Seoul Tel: Fax: or Singapore Tel: Fax: Taiwan - Kaohsiung Tel: Fax: Taiwan - Taipei Tel: Fax: Taiwan - Hsinchu Tel: Fax: EUROPE Austria - Weis Tel: Fax: Denmark - Ballerup Tel: Fax: France - Massy Tel: Fax: Germany - Ismaning Tel: Fax: Italy - Milan Tel: Fax: Netherlands - Drunen Tel: Fax: England - Berkshire Tel: Fax: // DS2882C-page 28 2 Microchip Technology Inc.

29 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: MCP6244-E/P MCP624-E/MC MCP624T-E/MC MCP6244-E/SL MCP6244-E/ST MCP6244T-E/SL MCP6244T- E/ST