MCP6021/2/3/4. Rail-to-Rail Input/Output, 10 MHz Op Amps PACKAGE TYPES. Description. Features. Typical Applications.

Transcription

1 M MCP6//3/4 Rail-to-Rail Input/Output, MHz Op Amps Features Rail-to-Rail Input/Output Wide Bandwidth: MHz (typ.) Low Noise:.7 nv/ Hz, at khz (typ.) Low Offset Voltage: - Industrial Temperature: ±5 µv (max.) - Extended Temperature: ±5 µv (max.) Mid-Supply V REF : MCP6 and MCP63 Low Supply Current: ma (typ.) Total Harmonic Distortion:.53% (typ., G = ) Unity Gain Stable Power Supply Range:.5V to 5.5V Temperature Range: - Industrial: -4 C to +5 C - Extended: -4 C to +5 C Typical Applications Automotive Driving A/D Converters Multi-Pole Active Filters Barcode Scanners Audio Processing Communications DAC Buffer Test Equipment Medical Instrumentation Description The MCP6, MCP6, MCP63 and MCP64 from Microchip Technology Inc. are rail-to-rail input and output op amps with high performance. Key specifications include: wide bandwidth ( MHz), low noise (.7 nv/ Hz), low input offset voltage and low distortion (.53% THD+N). These features make these op amps well suited for applications requiring high performance and bandwidth. The MCP63 also offers a chip select pin (CS) that gives power savings when the part is not in use. The single MCP6, single MCP63 and dual MCP6 are available in standard -lead PDIP, SOIC and TSSOP. The quad MCP64 is offered in 4-lead PDIP, SOIC and TSSOP packages. The MCP6//3/4 family is available in the Industrial and Extended temperature ranges. It has a power supply range of.5v to 5.5V. Available Tools SPICE Macro Model (at FilterLab software (at PACKAGE TYPES MCP6 PDIP SOIC, TSSOP NC V IN V IN + 3 V SS NC V DD V OUT V REF V OUTA V INA V INA + V SS MCP6 PDIP SOIC, TSSOP 3 4 V DD 7 V OUTB 6 V INB 5 V INB + MCP63 PDIP SOIC, TSSOP NC V IN V IN + 3 V SS 4 CS 7 V DD 6 V OUT 5 V REF MCP64 PDIP SOIC, TSSOP V OUTA V INA V INA + V DD V OUTD 3 V IND V IND + V SS V INB + 5 V INC + V INB V OUTB V INC V OUTC 3 Microchip Technology Inc. DS65B-page

2 MCP6//3/4. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings V DD - V SS...7.V All Inputs and Outputs... V SS -.3V to V DD +.3V Difference Input Voltage... V DD -V SS Output Short Circuit Current...continuous Current at Input Pins...± ma Current at Output and Supply Pins...±3 ma Storage Temperature C to +5 C Junction Temperature...+5 C ESD Protection on all pins (HBM/MM)... kv / V Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Pin Function Table Name V IN +, V INA +, V INB +, V INC +, V IND + V IN, V INA, V INB, V INC, V IND V DD V SS CS V REF V OUT, V OUTA, V OUTB, V OUTC, V OUTD NC Function Non-inverting Inputs Inverting Inputs Positive Power Supply Negative Power Supply Chip Select Reference Voltage Outputs No Internal Connection Electrical Specifications: Unless otherwise indicated, T A = +5 C, V DD = +.5V to +5.5V, V SS = GND, V CM = V DD /, V OUT V DD / and R L =kω to V DD /. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage: Industrial Temperature Parts V OS µv V CM = V Extended Temperature Parts V OS µv V CM = V, V DD = 5.V Extended Temperature Parts V OS mv V CM = V, V DD = 5.V T A = -4 C to +5 C Input Offset Voltage Temperature Drift V OS / T A ±3.5 µv/ C T A = -4 C to +5 C Power Supply Rejection Ratio PSRR 74 9 db V CM = V Input Current and Impedance Input Bias Current I B pa Industrial Temperature Parts I B 3 5 pa T A = +5 C Extended Temperature Parts I B 64 5, pa T A = +5 C Input Offset Current I OS ± pa Common-Mode Input Impedance Z CM 3 6 Ω pf Differential Input Impedance Z DIFF 3 3 Ω pf Common-Mode Common-Mode Input Range V CMR V SS -.3 V DD +.3 V Common-Mode Rejection Ratio CMRR 74 9 db V DD = 5V, V CM = -.3V to 5.3V CMRR 7 5 db V DD = 5V, V CM = 3.V to 5.3V CMRR 74 9 db V DD = 5V, V CM = -.3V to 3.V Voltage Reference (MCP6 and MCP63 only) V REF Accuracy (V REF - V DD /) V REF mv V REF Temperature Drift V REF / T ± µv/ C T A = -4 C to +5 C A Open Loop Gain DC Open Loop Gain (Large Signal) A OL 9 db V CM = V, V OUT = V SS +.3V to V DD -.3V DS65B-page 3 Microchip Technology Inc.

3 MCP6//3/4 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, T A = +5 C, V DD = +.5V to +5.5V, V SS = GND, V CM = V DD /, V OUT V DD / and R L =kω to V DD /. Parameters Sym Min Typ Max Units Conditions Output Maximum Output Voltage Swing V OL, V OH V SS +5 V DD - mv.5v output overdrive Output Short Circuit Current I SC ±3 ma Power Supply Supply Voltage V S V Quiescent Current per Amplifier I Q ma I O = AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = 5 C, V DD = +.5V to +5.5V, V SS = GND, V CM = V DD /, V OUT V DD /, R L =kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP MHz Phase Margin at Unity-Gain PM 65 G = Settling Time,.% t SETTLE 5 ns G =, V OUT = mv p-p Slew Rate SR 7. V/µs Total Harmonic Distortion Plus Noise f = khz, G = THD+N.53 % V OUT =.5V + 3.5V, BW = khz f = khz, G =, R L = 6Ω@ KHz THD+N.64 % V OUT =.5V + 3.5V, BW = khz f = khz, G = + V/V THD+N.4 % V OUT = 4V P-P, V DD = 5.V, BW = khz f = khz, G = + V/V THD+N.9 % V OUT = 4V P-P, V DD = 5.V, BW = khz f = khz, G = + V/V THD+N.5 % V OUT = 4V P-P, V DD = 5.V, BW = khz Noise Input Voltage Noise E ni.9 µvp-p f =. Hz to Hz Input Voltage Noise Density e ni.7 nv/ Hz f = khz Input Current Noise Density i ni 3 fa/ Hz f = khz MCP63 CHIP SELECT (CS) CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = 5 C, V DD = +.5V to +5.5V, V SS = GND, V CM = V DD /, V OUT V DD /, R L =kω to V DD / and C L = 6 pf. Parameters Sym Min Typ Max Units Conditions DC Characteristics CS Logic Threshold, Low V IL.V DD V CS Input Current, Low I CSL -.. µa CS = V SS CS Logic Threshold, High V IH.V DD V DD V CS Input Current, High I CSH.. µa CS = V DD CS Input High, GND Current I SS.5. µa CS = V DD Amplifier Output Leakage. µa CS = V DD Timing CS Low to Amplifier Output Turn-on Time CS High to Amplifier Output High-Z Turn-off Time t ON µs G =, V IN = V SS, CS =.V DD to V OUT =.45V DD time t OFF. µs G =, V IN = V SS, CS =.V DD to V OUT =.5V DD time Hysteresis V HYST.6 V Internal Switch 3 Microchip Technology Inc. DS65B-page 3

4 MCP6//3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +.5V to +5.5V and V SS = GND. Parameters Symbol Min Typ Max Units Conditions Temperature Ranges Industrial Temperature Range T A C Extended Temperature Range T A C Operating Temperature Range T A C Note Storage Temperature Range T A C Thermal Package Resistances Thermal Resistance, L-PDIP θ JA 5 C/W Thermal Resistance, L-SOIC θ JA 63 C/W Thermal Resistance, L-TSSOP θ JA 4 C/W Thermal Resistance, 4L-PDIP θ JA 7 C/W Thermal Resistance, 4L-SOIC θ JA C/W Thermal Resistance, 4L-TSSOP θ JA C/W Note : The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any case, the internal junction temperature (T J ) must not exceed the absolute maximum specification of 5 C. CS t ON t OFF V OUT Hi-Z Amplifier On Hi-Z I SS 5 na (typ.) ma (typ.) 5 na (typ.) I CS na (typ.) na (typ.) na (typ.) FIGURE -: Timing diagram for the CS pin on the MCP63. DS65B-page 4 3 Microchip Technology Inc.

5 MCP6//3/4. TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. Percentage of Occurances 6% 4% % % % 6% 4% % % 9 Samples T A = +5 C I-Temp Parts 4 5 Percentage of Occurances % % % 9% % 7% 6% 5% 4% 3% % % % 9 Samples T A = -4 C to +5 C I-Temp Parts Input Offset Voltage (µv) Input Offset Voltage Drift (µv/ C) FIGURE -: Input Offset Voltage, (Industrial Temperature Parts). FIGURE -4: Input Offset Voltage Drift, (Industrial Temperature Parts). Percentage of Occurances 4% % % % 6% 4% % % % 6% 4% % % 43 Samples V DD = 5.V V CM = V T A = +5 C E-Temp Parts 6 Percentage of Occurances 6% 4% % % % 6% 4% % % % 6% 4% % % - E-Temp Parts Samples V CM = V T A = -4 C to +5 C 4 6 Input Offset Voltage (µv) Input Offset Voltage Drift (µv/ C) FIGURE -: Input Offset Voltage, (Extended Temperature Parts). FIGURE -5: Input Offset Voltage Drift, (Extended Temperature Parts). Input Offset Voltage (µv) V DD =.5V -4 C +5 C +5 C +5 C Common Mode Input Voltage (V) Input Offset Voltage (µv) V DD = 5.5V -4 C +5 C +5 C +5 C Common Mode Input Voltage (V) FIGURE -3: Input Offset Voltage vs. Common Mode Input Voltage with V DD =.5V. FIGURE -6: Input Offset Voltage vs. Common Mode Input Voltage with V DD = 5.5V. 3 Microchip Technology Inc. DS65B-page 5

6 .E-.E+.E+.E+.E+3.E+4.E+5.E+6.E+.E+3.E+4.E+5.E+6 MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. Input Offset Voltage (µv) V DD = 5.V V CM = V Ambient Temperature ( C) Input Offset Voltage (µv) V CM = V DD / 5 5 V DD = 5.5V -5 V DD =.5V Output Voltage (V) FIGURE -7: Temperature. Input Offset Voltage vs. FIGURE -: Output Voltage. Input Offset Voltage vs. Input Noise Voltage Density (nv/ Hz),. k k k M Frequency (Hz) Input Noise Voltage Density (nv/ Hz) f = khz V DD = 5.V Common Mode Input Voltage (V) FIGURE -: vs. Frequency. Input Noise Voltage Density FIGURE -: Input Noise Voltage Density vs. Common Mode Input Voltage. CMRR, PSRR (db) CMRR PSRR+ PSRR- k k k M Frequency (Hz) FIGURE -9: Common Mode, Power Supply Rejection Ratios vs. Frequency. PSRR, CMRR (db) 5 CMRR PSRR (V CM = V) Ambient Temperature ( C) FIGURE -: Common Mode, Power Supply Rejection Ratios vs. Temperature. DS65B-page 6 3 Microchip Technology Inc.

7 .E+.E+.E+.E+3.E+4.E+5.E+6.E+7.E+ MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. Input Bias, Offset Currents (pa), V DD = 5.5V I B, T A = +5 C, I OS, T A = +5 C I B, T A = +5 C I OS, T A = +5 C Input Bias, Offset Currents (pa),, V CM = V DD V DD = 5.5V I B I OS Common Mode Input Voltage (V) Ambient Temperature ( C) FIGURE -3: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE -6: vs. Temperature. Input Bias, Offset Currents Quiescent Current (ma/amplifier) C +5 C +5 C -4 C Power Supply Voltage (V) Quiescent Current (ma/amplifier).. V. DD = 5.5V.9. V DD =.5V V CM = V DD -.5V Ambient Temperature ( C) FIGURE -4: Supply Voltage. Quiescent Current vs. FIGURE -7: Temperature. Quiescent Current vs. Output Short Circuit Current (ma) C +5 C +5 C 5-4 C Supply Voltage (V) Open-Loop Gain (db) Phase Gain k k k M MM Frequency (Hz) Open-Loop Phase ( ) FIGURE -5: vs. Supply Voltage. Output Short-Circuit Current FIGURE -: Frequency. Open-Loop Gain, Phase vs. 3 Microchip Technology Inc. DS65B-page 7

8 .E+.E+3.E+4.E+5 MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. DC Open-Loop Gain (db) 3 V DD = 5.5V V DD =.5V 9 k k k Load Resistance ( ) DC Open-Loop Gain (db) 5 V DD = 5.5V 5 V DD =.5V Ambient Temperature ( C) FIGURE -9: Load Resistance. DC Open-Loop Gain vs. FIGURE -: Temperature. DC Open-Loop Gain vs. DC Open-Loop Gain (db) 9 V CM = V DD / V DD = 5.5V V DD =.5V Output Voltage Headroom (V); V DD - V OH or V OL - V SS Gain Bandwidth Product (MHz) Gain Bandwidth Product Phase Margin, G = + 5 V DD = 5.V Common Mode Input Voltage (V) Phase Margin, G = + ( ) FIGURE -: Small Signal DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE -3: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Gain Bandwidth Product (MHz) GBWP, V DD = 5.5V GBWP, V DD =.5V PM, V DD =.5V PM, V DD = 5.5V Ambient Temperature ( C) Phase Margin, G = + ( ) Gain Bandwidth Product (MHz) Gain Bandwidth Product V DD = 5.V V CM = V DD / Phase Margin, G = Output Voltage (V) Phase Margin, G = + ( ) FIGURE -: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE -4: Gain Bandwidth Product, Phase Margin vs. Output Voltage. DS65B-page 3 Microchip Technology Inc.

9 .E+.E-5.E-5 3.E-5 4.E-5 5.E-5 6.E-5 7.E-5.E-5 9.E-5.E-4.E+4.E+5.E+6.E+7.E+3.E+4.E+5.E+6 MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. Slew Rate (V/µs) Falling, V DD = 5.5V Rising, V DD = 5.5V Falling, V DD =.5V Rising, V DD =.5V Ambient Temperature ( C) Maximum Output Voltage Swing (V P-P ) V DD = 5.5V V DD =.5V. k k M M Frequency (Hz) FIGURE -5: Slew Rate vs. Temperature. FIGURE -: Maximum Output Voltage Swing vs. Frequency. THD+N (%).%.%.%.% G = + V/V G = + V/V G = + V/V f = khz BW Meas = khz V DD = 5.V Output Voltage (V P-P ) THD+N (%).%.%.% G = + V/V G = + V/V G = + V/V f = khz BW Meas = khz V DD = 5.V.% Output Voltage (V P-P ) FIGURE -6: Total Harmonic Distortion plus Noise vs. Output Voltage with f = khz. FIGURE -9: Total Harmonic Distortion plus Noise vs. Output Voltage with f = khz. Input, Output Voltage (V) V OUT V IN Time ( µs/div) V DD = 5V G = + V/V Channel to Channel Separation (db) G = + V/V 5 k k k Frequency (Hz) M FIGURE -7: The MCP6//3/4 family shows no phase reversal under overdrive. FIGURE -3: Channel-to-Channel Separation vs. Frequency (MCP6 and MCP64 only). 3 Microchip Technology Inc. DS65B-page 9

10 6.E- 5.E- 4.E- 3.E-.E-.E-.E+ -.E- -.E- -3.E- -4.E- -5.E- -6.E-.E+ 5.E-7.E-6.E-6.E-6 3.E-6 3.E-6 4.E-6 4.E-6 5.E-6 5.E-6 6.E- 5.E- 4.E- 3.E-.E-.E-.E+ -.E- -.E- -3.E- -4.E- -5.E- -6.E-.E+ 5.E-7.E-6.E-6.E-6 3.E-6 3.E-6 4.E-6 4.E-6 5.E-6 5.E-6 MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. Output Voltage Headroom; V DD -V OH or V OL -V SS (mv), V OL - V SS V DD - V OH.. Output Current Magnitude (ma) Output Voltage Headroom V DD -V OH or V OL -V SS (mv) 9 V OL - V SS V DD - V OH Ambient Temperature ( C) FIGURE -3: vs. Output Current. Output Voltage Headroom FIGURE -34: vs. Temperature. Output Voltage Headroom Output Voltage ( mv/div) G = + V/V Output Voltage ( mv/div) G = - V/V R F = k.e+.e-7 4.E-7 6.E-7.E-7.E-6.E-6.E-6.E-6.E-6.E-6 Time ( ns/div).e+.e-7 4.E-7 6.E-7.E-7.E-6.E-6.E-6.E-6.E-6.E-6 Time ( ns/div) FIGURE -3: Pulse Response. Small-Signal Non-inverting FIGURE -35: Response. Small-Signal Inverting Pulse Output Voltage (V) Time (5 ns/div) G = + V/V Output Voltage (V) G = - V/V R F = k Time (5 ns/div) FIGURE -33: Pulse Response. Large-Signal Non-inverting FIGURE -36: Response. Large-Signal Inverting Pulse DS65B-page 3 Microchip Technology Inc.

11 .E+ 5.E-6.E-5.5E-5.E-5.5E-5 3.E-5 3.5E-5 MCP6//3/4 Note: Unless otherwise indicated, T A =+5 C, V DD = +.5V to +5.5V, V SS = GND, V CM =V DD /, R L =kω to V DD /, V OUT V DD / and C L = 6 pf. V REF Accuracy; V REF -V DD / (mv) Power Supply Voltage (V) V REF Accuracy; V REF -V DD / (mv) 5 4 Representative Part 3 V DD = 5.5V - V DD =.5V Ambient Temperature ( C) FIGURE -37: V REF Accuracy vs. Supply Voltage (MCP6 and MCP63 only). FIGURE -4: V REF Accuracy vs. Temperature (MCP6 and MCP63 only). Quiescent Current (ma/amplifier).6.4 Op Amp Op Amp turns on here shuts off here... CS swept Hysteresis high to low.6.4 V DD =.5V CS swept G = + V/V low to high. V IN =.5V Chip Select Voltage (V) Quiescent Current (ma/amplifier).6 Op Amp Op Amp.4 turns on here shuts off here.. Hysteresis CS swept. high to low.6 CS swept V DD = 5.5V low to high.4 G = + V/V. V IN =.75V Chip Select Voltage (V) FIGURE -3: Chip Select (CS) Hysteresis (MCP63 only) with V DD =.5V. FIGURE -4: Chip Select (CS) Hysteresis (MCP63 only) with V DD = 5.5V. Chip Select Voltage, Output Voltage (V) Output on CS Voltage V OUT Output High-Z Time (5 µs/div) V DD = 5.V G = + V/V V IN = V SS Output on FIGURE -39: Chip Select (CS) to Amplifier Output Response Time (MCP63 only). 3 Microchip Technology Inc. DS65B-page

12 MCP6//3/4 3. APPLICATIONS INFORMATION The MCP6//3/4 family of operational amplifiers are fabricated on Microchip s state-of-the-art CMOS process. They are unity-gain stable and suitable for a wide range of general-purpose applications. 3. Rail-to-Rail Input The MCP6//3/4 amplifier family is designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure -7 shows an input voltage exceeding both supplies with no resulting phase inversion. The input stage of the MCP6//3/4 family of devices uses two differential input stages in parallel; one operates at low common-mode input voltage (V CM ), while the other operates at high V CM. With this topology, the device operates with V CM up to.3v past either supply rail (V SS -.3V to V DD +.3V) at 5 C. The amplifier input behaves linearly as long as V CM is kept within the specified V CMR limits. The input offset voltage is measured at both V CM =V SS -.3V and V DD +.3V to ensure proper operation. Input voltages that exceed the input voltage range (V CMR ) can cause excessive current to flow in or out of the input pins. Current beyond ± ma introduces possible reliability problems. Thus, applications that exceed this rating must externally limit the input current with an input resistor (R IN ), as shown in Figure MCP63 Chip Select (CS) The MCP63 is a single amplifier with chip select (CS). When CS is high, the supply current is less than na (typ) and travels from the CS pin to V SS, with the amplifier output being put into a high-impedance state. When CS is low, the amplifier is enabled. If CS is left floating, the amplifier will not operate properly. Figure - and Figure -39 show the output voltage and supply current response to a CS pulse. 3.4 MCP6 and MCP63 Reference Voltage The single op amps (MCP6 and MCP63) have an internal mid-supply reference voltage connected to the V REF pin (see Figure 3-). The MCP6 has CS internally tied to V SS, which always keeps the op amp on and always provides a mid-supply reference. With the MCP63, taking the CS pin high conserves power by shutting down both the op amp and the V REF circuitry. Taking the CS pin low turns on the op amp and V REF circuitry. V REF V DD 5 kω 5 kω CS V IN R IN MCP6X V OUT V SS (CS tied internally to V SS for MCP6) R IN (Maximum expected V IN ) - V DD ma R IN V SS - (Minimum expected V IN ) ma FIGURE 3-: into an input pin. 3. Rail-to-Rail Output R IN limits the current flow The Maximum Output Voltage Swing is the maximum swing possible under a particular output load. According to the specification table, the output can reach within mv of either supply rail when R L =kω. See Figure -3 and Figure -34 for more information concerning typical performance. FIGURE 3-: Simplified internal V REF circuit (MCP6 and MCP63 only). See Figure 3-3 for a non-inverting gain circuit using the internal mid-supply reference. The DC-blocking capacitor (C B ) also reduces noise by coupling the op amp input to the source. V IN R G C B R F V REF V OUT FIGURE 3-3: Non-inverting gain circuit using V REF (MCP6 and MCP63 only). DS65B-page 3 Microchip Technology Inc.

13 MCP6//3/4 To use the internal mid-supply reference for an inverting gain circuit, connect the V REF pin to the noninverting input, as shown in Figure 3-4. The capacitor C B helps reduce power supply noise on the output. V IN R G R F V OUT Recommended R ISO ( ), G N + FIGURE 3-4: Inverting gain circuit using V REF (MCP6 and MCP63 only). If you don t need the mid-supply reference, leave the V REF pin open. 3.5 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop s phase margin decreases, and the closed loop bandwidth is reduced. This produces gain-peaking in the frequency response, with overshoot and ringing in the step response. When driving large capacitive loads with these op amps (e.g., > 6 pf when G = +), a small series resistor at the output (R ISO in Figure 3-5) improves the feedback loop s phase margin (stability) by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V IN MCP6X V REF C B R ISO FIGURE 3-5: Output resistor R ISO stabilizes large capacitive loads. Figure 3-6 gives recommended R ISO values for different capacitive laods and gains. The x-axis is the normalized load capacitance (C L /G N ), where G N is the circuit s noise gain. For non-inverting gains, G N and the gain are equal. For inverting gains, G N is + Gain (e.g., - V/V gives G N = + V/V). C L V OUT,, Normalized Capacitance; C L /G N (pf) FIGURE 3-6: Recommended R ISO values for capacitive loads. After selecting R ISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6//3/4 Spice macro model are very helpful. Modify R ISO s value until the response is reasonable. 3.6 Supply Bypass With this family of operational amplifiers, the power supply pin (V DD for single supply) should have a local bypass capacitor (i.e.,. µf to. µf) within mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., µf or larger) within mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.7 PCB Surface Leakage In applications where low input bias current is critical, PCB (printed circuit board) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is Ω. A 5V difference would cause 5 pa of current to flow, which is greater than the MCP6//3/4 family s bias current at 5 C ( pa, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-7. Guard Ring V IN V IN + FIGURE 3-7: Example guard ring layout. 3 Microchip Technology Inc. DS65B-page 3

14 MCP6//3/4. Inverting (Figure 3-7) and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors). a. Connect the guard ring to the non-inverting input pin (V IN +). This biases the guard ring to the same reference voltage as the op amp s input (e.g., V DD / or ground). b. Connect the inverting pin (V IN ) to the input with a wire that does not touch the PCB surface.. Non-inverting Gain and Unity-Gain Buffer a. Connect the guard ring to the inverting input pin (V IN ); this biases the guard ring to the common mode input voltage. b. Connect the non-inverting pin (V IN +) to the input with a wire that does not touch the PCB surface. 3. High-Speed PCB Layout Due to their speed capabilities, a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in the performance of these op amps. Good PC board layout techniques will help you achieve the performance shown in the Electrical Characteristics and Typical Performance Curves, while also helping you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane and connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Separate digital from analog, low-speed from highspeed and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separating them from interfering components and traces. This is especially important for high-frequency (low rise-time) signals. Sometimes it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect the guard trace to ground plane at both ends, and in the middle for long traces. Use coax cables (or low inductance wiring) to route signal and power to and from the PCB. 3.9 Typical Applications 3.9. A/D CONVERTER DRIVER AND ANTI-ALIASING FILTER Figure 3- shows a third-order Butterworth filter that can be used as an A/D converter driver. It has a bandwidth of khz and a reasonable step response. It will work well for conversion rates of ksps and greater (it has 9 db attenuation at 6 khz)..45 kω. nf 4.7 kω 33. kω FIGURE 3-: A/D converter driver and anti-aliasing filter with a khz cutoff frequency. This filter can easily be adjusted to another bandwidth by multiplying all capacitors by the same factor. Alternatively, the resistors can all be scaled by another common factor to adjust the bandwidth OPTICAL DETECTOR AMPLIFIER Figure 3-9 shows the MCP6 op amp used as a transimpedance amplifier in a photo detector circuit. The photo detector looks like a capacitive current source, so the kω resistor gains the input signal to a reasonable level. The 5.6 pf capacitor stabilizes this circuit and produces a flat frequency response with a bandwidth of 37 khz. Photo Detector pf. nf pf V DD / 5.6 pf kω MCP6X MCP6 FIGURE 3-9: Transimpedance amplifier for an optical detector. DS65B-page 4 3 Microchip Technology Inc.

15 MCP6//3/4 4. DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6//3/4 family of op amps. 4. SPICE Macro Model The latest SPICE macro model for the MCP6//3/4 op amps is available on our web site ( This model is intended as an initial design tool that works well in the op amp s linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specs and plots. 4. FilterLab Software The FilterLab software is an innovative tool that simplifies analog active filter (using op amps) design. Available at no cost from our web site (at the FilterLab software active filter design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the Macro Model to simulate actual filter performance. 3 Microchip Technology Inc. DS65B-page 5

16 MCP6//3/4 5. PACKAGING INFORMATION 5. Package Marking Information -Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6 I/P Lead SOIC (5 mil) Example: XXXXXXXX XXXXYYWW NNN MCP6 I/SN Lead TSSOP Example: XXXX YWW NNN 6 E33 56 Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last digits of calendar year) WW Week code (week of January is week ) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard device marking consists of Microchip part number, year code, week code, and traceability code. DS65B-page 6 3 Microchip Technology Inc.

17 MCP6//3/4 Package Marking Information (Continued) 4-Lead PDIP (3 mil) (MCP64) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP64-I/P XXXXXXXXXXXXXX Lead SOIC (5 mil) (MCP64) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP64ISL XXXXXXXXXX Lead TSSOP (MCP64) Example: XXXXXX YYWW NNN 64E Microchip Technology Inc. DS65B-page 7

18 MCP6//3/4 -Lead Plastic Dual In-line (P) 3 mil (PDIP) E D n α E A A c A L β eb B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p..54 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A.5.3 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.54mm) per side. JEDEC Equivalent: MS- Drawing No. C4- DS65B-page 3 Microchip Technology Inc.

19 MCP6//3/4 -Lead Plastic Small Outline (SN) Narrow, 5 mil (SOIC) E E p D B n 45 h α c A A φ β L A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p.5.7 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ 4 4 Lead Thickness c Lead Width B Mold Draft Angle Top α 5 5 Mold Draft Angle Bottom β 5 5 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.54mm) per side. JEDEC Equivalent: MS- Drawing No. C Microchip Technology Inc. DS65B-page 9

20 MCP6//3/4 -Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) E E p D B n A α c φ A A β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p.6.65 Overall Height A.43. Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot Angle φ 4 4 Lead Thickness c Lead Width B Mold Draft Angle Top α 5 5 Mold Draft Angle Bottom β 5 5 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.5 (.7mm) per side. JEDEC Equivalent: MO-53 Drawing No. C4-6 DS65B-page 3 Microchip Technology Inc.

21 MCP6//3/4 4-Lead Plastic Dual In-line (P) 3 mil (PDIP) E D n α E A A c L β eb A B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p..54 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A.5.3 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic β Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.54mm) per side. JEDEC Equivalent: MS- Drawing No. C4-5 3 Microchip Technology Inc. DS65B-page

22 MCP6//3/4 4-Lead Plastic Small Outline (SL) Narrow, 5 mil (SOIC) E E p D B n 45 h α c A A β L φ A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p.5.7 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ 4 4 Lead Thickness c Lead Width B Mold Draft Angle Top α 5 5 Mold Draft Angle Bottom β 5 5 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.54mm) per side. JEDEC Equivalent: MS- Drawing No. C4-65 DS65B-page 3 Microchip Technology Inc.

23 MCP6//3/4 4-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) p E E D B n A α c φ β L A A Units Dimension Limits Number of Pins n Pitch p Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic MIN INCHES NOM MAX MIN MILLIMETERS* NOM 4.65 Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.5 (.7mm) per side. JEDEC Equivalent: MO-53 Drawing No. C MAX Microchip Technology Inc. DS65B-page 3

24 MCP6//3/4 NOTES: DS65B-page 4 3 Microchip Technology Inc.

25 MCP6//3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP6 CMOS Single Op Amp MCP6T CMOS Single Op Amp (Tape and Reel for SOIC, TSSOP) MCP6 CMOS Dual Op Amp MCP6T CMOS Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP63 CMOS Single Op Amp w/ CS Function MCP63T CMOS Single Op Amp w/ CS Function (Tape and Reel for SOIC and TSSOP) MCP64 CMOS Quad Op Amp MCP64T CMOS Quad Op Amp (Tape and Reel for SOIC and TSSOP) Temperature Range: I = -4 C to +5 C E = -4 C to +5 C Package: P = Plastic DIP (3 mil Body), -lead, 4-lead SN = Plastic SOIC (5mil Body), -lead SL = Plastic SOIC (5 mil Body), 4-lead ST = Plastic TSSOP, -lead, 4-lead Examples: a) MCP6-I/P: Industrial temperature, PDIP package. b) MCP6-E/P: Extended temperature, PDIP package. c) MCP6-E/SN: Extended temperature, SOIC package. a) MCP6-I/P: Industrial temperature, PDIP package. b) MCP6-E/P: Extended temperature, PDIP package. c) MCP6T-E/ST: Tape and Reel, Extended temperature, TSSOP package. a) MCP63-I/P: Industrial temperature, PDIP package. b) MCP63-E/P: Extended temperature, PDIP package. c) MCP63-E/SN: Extended temperature, SOIC package. a) MCP64-I/SL: Industrial temperature, SOIC package. b) MCP64-E/SL: Extended temperature, SOIC package. c) MCP64T-E/ST: Tape and Reel, Extended temperature, TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:. Your local Microchip sales office. The Microchip Corporate Literature Center U.S. FAX: (4) The Microchip Worldwide Site ( Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site ( to receive the most current information on our products. 3 Microchip Technology Inc. DS65B-page 5

26 MCP6//3/4 NOTES: DS65B-page 6 3 Microchip Technology Inc.

27 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microid, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dspicdem, dspicdem.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rflab, rfpic, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 3, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 999 and Mountain View, California in March. The Company s quality system processes and procedures are QS-9 compliant for its PICmicro -bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9 certified. 3 Microchip Technology Inc. DS65B-page 7

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