MCP601/2/3/4. 2.7V to 5.5V Single Supply CMOS Op Amps FEATURES DESCRIPTION TYPICAL APPLICATIONS AVAILABLE TOOLS PACKAGE TYPES
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1 M MCP6/2/3/4 2.7V to.v Single Supply CMOS Op Amps FEATURES Single Supply: 2.7V to.v Rail-to-Rail Output Input Range Includes Ground Gain Bandwidth Product: 2.8 MHz (typ.) Unity Gain Stable Low Quiescent Current: 23 µa/amplifier (typ.) Chip Select: MCP63 Temperature Ranges: - Industrial: -4 C to +8 C - Extended: -4 C to +2 C Available in Single, Dual and Quad TYPICAL APPLICATIONS Portable Equipment A/D Converter Driver Photo Diode Pre-amp Analog Filters Data Acquisition Notebooks and PDAs Sensor Interface AVAILABLE TOOLS SPICE Macro Models at FilterLab Software at DESCRIPTION The Microchip Technology Inc. MCP6/2/3/4 family of low-power op amps (operational amplifiers) are offered in single (MCP6), single with Chip Select (MCP63), dual (MCP62) and quad (MCP64) configurations. These op amps utilize an advanced CMOS technology, which provides low bias current, high-speed operation, high open-loop gain, and rail-to-rail output swing. This product offering operates with a single supply voltage that can be as low as 2.7V, while drawing 23 µa (typ.) of quiescent current per amplifier. In addition, the common mode input voltage range goes.3v below ground, making these amplifiers ideal for single supply operation. These devices are appropriate for low-power, batteryoperated circuits due to the low quiescent current, for A/D convert driver amplifiers because of their wide bandwidth or for anti-aliasing filters by virtue of their low input bias current. The MCP6, MCP62 and MCP63 are available in standard 8-lead PDIP, SOIC and TSSOP packages. The MCP6 and MCP6R are also available in a standard -lead SOT23 package and the MCP63 in a standard 6-lead SOT23 package. The MCP64 is offered in standard 4-lead PDIP, SOIC and TSSOP packages. The MCP6/2/3/4 family is available in the Industrial and Extended temperature ranges and also has a power supply range of 2.7V to.v. PACKAGE TYPES MCP6 PDIP, SOIC, TSSOP NC V IN V IN+ V SS NC V DD V OUT NC MCP6 SOT23- V OUT V SS 2 V IN+ 3 4 V DD V IN MCP62 PDIP, SOIC, TSSOP V OUTA V INA V INA+ V SS V DD V OUTB V INB V INB+ MCP6R SOT23- V OUT V DD 2 V IN+ 3 4 V SS V IN MCP63 PDIP, SOIC, TSSOP NC V IN V IN+ V SS CS V DD V OUT NC V OUT V SS 2 V IN+ 3 MCP63 SOT V DD CS 4 V IN MCP64 PDIP, SOIC, TSSOP V OUTA V INA V INA V OUTD 3 V IND 2 V IND+ V DD 4 V SS V INB+ V INC+ V INB 6 9 V INC V OUTB 7 8 V OUTC 23 Microchip Technology Inc. DS234E-page
2 MCP6/2/3/4. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings V DD - V SS...7.V All inputs and outputs... V SS -.3V to V DD +.3V Difference Input voltage... V DD - V SS Output Short Circuit Current...continuous Current at Input Pin...±2 ma Current at Output and Supply Pins...±3 ma Storage temperature...-6 C to + C Junction temperature...+ C ESD protection on all pins (HBM; MM)... 3 kv; 2V PIN FUNCTION TABLE Name V IN+, V INA+, V INB+, V INC+, V IND+ V IN, V INA, V INB, V INC, V IND V DD V SS V OUT, V OUTA, V OUTB, V OUTC, V OUTD CS NC Function Non-inverting Inputs Inverting Inputs Positive Power Supply Negative Power Supply Outputs Chip Select No Internal Connection Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, and R L = kω to V DD /2. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V OS -2 ±.7 +2 mv Industrial Temperature V OS -3 ± +3 mv T A = -4 C to +8 C (Note ) Extended Temperature V OS -4. ± +4. mv T A = -4 C to +2 C (Note ) Input Offset Temperature Drift V OS / T A ±2. µv/ C T A = -4 C to +2 C Power Supply Rejection PSRR 8 88 db V DD = 2.7V to.v Input Current and Impedance Input Bias Current I B pa Industrial Temperature I B 2 6 pa T A = +8 C (Note 2) Extended Temperature I B 4 pa T A = +2 C (Note 2) Input Offset Current I OS ± pa Common Mode Input Impedance Z CM 3 6 Ω pf Differential Input Impedance Z DIFF 3 3 Ω pf Common Mode Common Mode Input Range V CMR V SS -.3 V DD -.2 V Common Mode Rejection Ratio CMRR 7 9 db V DD =.V, V CM = -.3V to 3.8V Open-loop Gain DC Open-loop Gain (large signal) A OL db R L = 2 kω to V DD /2, V OUT = mv to V DD - mv A OL 9 db R L = kω to V DD /2, V OUT = mv to V DD - mv Output Maximum Output Voltage Swing V OL, V OH V SS + V DD -2 mv R L = 2 kω to V DD /2, Output overdrive =.V V OL, V OH V SS +4 V DD -6 mv R L = kω to V DD /2, Output overdrive =.V Linear Output Voltage Swing V OUT V SS + V DD - mv R L = 2 kω to V DD /2, A OL db V OUT V SS + V DD - mv R L = kω to V DD /2, A OL 9 db Output Short Circuit Current I SC ±22 ma V DD =.V I SC ±2 ma V DD = 2.7V Power Supply Supply Voltage V DD 2.7. V Quiescent Current per Amplifier I Q µa I O = Note : Maximum and minimum specified for PDIP and SOIC packages only. Typical specs refer to all packages. 2: Maximum and minimum specified for PDIP, SOIC and TSSOP packages only. Typical specs refer to all packages. DS234E-page 2 23 Microchip Technology Inc.
3 MCP6/2/3/4 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2,and C L = pf. Parameters Sym Min Typ Max Units Conditions Frequency Response Gain Bandwidth Product GBWP 2.8 MHz Phase Margin PM G = + V/V Step Response Slew Rate SR 2.3 V/µs G = + V/V Settling Time (.%) t settle 4. µs G = + V/V, 3.8V step Noise Input Noise Voltage E ni 7 µv P-P f =. Hz to Hz Input Noise Voltage Density e ni 29 nv/ Hz f = khz e ni 2 nv/ Hz f = khz Input Noise Current Density i ni.6 fa/ Hz f = khz MCP63 CHIP SELECT CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, V OUT V DD /2, R L = kω to V DD /2, and C L = pf. Parameters Sym Min Typ Max Units Conditions DC Characteristics CS Logic Threshold, Low V IL V SS.2 V DD V CS Input Current, Low I CSL -. µa CS =.2V DD CS Logic Threshold, High V IH.8 V DD V DD V CS Input Current, High I CSH.7 2. µa CS = V DD Shutdown V SS current I Q_SHDN µa CS = V DD Amplifier Output Leakage in Shutdown I O_SHDN na CS Threshold Hysteresis HYST.3 V Internal switch Timing CS Low to Amplifier Output Turn-on t ON 3. µs CS.2V DD, G = + V/V Time CS High to Amplifier Output High-Z Time t OFF ns CS.8V DD, G = + V/V, No Load CS t ON t OFF V OUT Hi-Z Output Active Hi-Z I DD 2 na (typ.) 23 µa (typ.) I SS -7 na (typ.) -23 µa (typ.) CS 7 na (typ.) 2nA (typ.) Current FIGURE -: timing diagram. MCP63 Chip Select (CS) 23 Microchip Technology Inc. DS234E-page 3
4 MCP6/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +2.7V to +.V and V SS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T A C Industrial temperature parts T A C Extended temperature parts Operating Temperature Range T A C Note Storage Temperature Range T A -6 + C Thermal Package Resistances Thermal Resistance, L-SOT23 θ JA 26 C/W Thermal Resistance, 6L-SOT23 θ JA 23 C/W Thermal Resistance, 8L-PDIP θ JA 8 C/W Thermal Resistance, 8L-SOIC θ JA 63 C/W Thermal Resistance, 8L-TSSOP θ JA 24 C/W Thermal Resistance, 4L-PDIP θ JA 7 C/W Thermal Resistance, 4L-SOIC θ JA 2 C/W Thermal Resistance, 4L-TSSOP θ JA C/W Note: The Industrial temperature parts operate over this extended range, but with reduced performance. The Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction temperature (T J ) must not exceed the absolute maximum specification of C. DS234E-page 4 23 Microchip Technology Inc.
5 .E-.E+.E+.E+2.E+3.E+4.E+.E+6.E+7,,.E-.E+.E+.E+2.E+3.E+4.E+.E+6 MCP6/2/3/4 2. TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Open-Loop Gain (db) 2 Gain -3 8 Phase k k k M M Frequency (Hz) Open-Loop Phase ( ) Quiescent Current per Amplifier (µa) 3 I O = -4 C 2 +2 C 2 +8 C +2 C Supply Voltage (V) FIGURE 2-: Frequency. Open-Loop Gain, Phase vs. FIGURE 2-4: Supply Voltage. Quiescent Current vs. Slew Rate (V/µs) 3. V DD =.V 3. Falling Edge Rising Edge Ambient Temperature ( C) Quiescent Current per Amplifier (µa) 3 I O = 2 V DD =.V 2 V DD = 2.7V Ambient Temperature ( C) FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-: Temperature. Quiescent Current vs. Gain Bandwidth Product (MHz) GBWP PM, G = Ambient Temperature ( C) Phase Margin, G = + ( ) Input Noise Voltage Density (V/ Hz) µ µ n n. k k k M Frequency (Hz) FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-6: vs. Frequency. Input Noise Voltage Density 23 Microchip Technology Inc. DS234E-page
6 MCP6/2/3/4 Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Percentage of Occurrences 6% 2 Samples 4% 2% % 8% 6% 4% 2% % Input Offset Voltage (mv) Percentage of Occurrences 8% 2 Samples 6% T A = -4 to +2 C 4% 2% % 8% 6% 4% 2% % Input Offset Voltage Drift (µv/ C) FIGURE 2-7: Input Offset Voltage. FIGURE 2-: Input Offset Voltage Drift. Input Offset Voltage (mv)..4.3 V DD =.V.2. V. DD = 2.7V CMRR, PSRR (db) 9 9 PSRR 8 CMRR Ambient Temperature ( C) Ambient Temperature ( C) FIGURE 2-8: Temperature. Input Offset Voltage vs. FIGURE 2-: Temperature. CMRR, PSRR vs. Input Offset Voltage (µv) V DD = 2.7V T A = +2 C T A = -4 C T A = +2 C T A = +8 C T A = +2 C Common Mode Input Voltage (V) Input Offset Voltage (µv) V DD =.V T A = +2 C T A = -4 C T A = +2 C T A = +8 C T A = +2 C Common Mode Input Voltage (V). FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with V DD = 2.7V. FIGURE 2-2: Input Offset Voltage vs. Common Mode Input Voltage with V DD =.V. DS234E-page 6 23 Microchip Technology Inc.
7 .E+3.E+4.E+.E+6.E+2.E+3.E+4.E+.E+.E+.E+2.E+3.E+4.E+.E+6 MCP6/2/3/4 Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Channel to Channel Separation (db) No Load k k k M Frequency (Hz) CMRR, PSRR (db) CMRR PSRR+ PSRR- 2 V DD =.V k k k Frequency (Hz) FIGURE 2-3: Channel-to-Channel Separation vs. Frequency. FIGURE 2-6: Frequency. CMRR, PSRR vs. Input Bias and Offset Currents (pa) V DD =.V V CM = 4.3V Ambient Temperature ( C) I B I OS Input Bias and Offset Currents (pa) V DD =.V max. V CMR 4.3V I OS, +2 C I B, +2 C I B, +8 C I OS, +8 C Common Mode Input Voltage (V) FIGURE 2-4: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-7: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. DC Open-Loop Gain (db) 2 V DD =.V 9 V DD =2.7V 8 k k k Load Resistance (Ω) DC Open-Loop Gain (db) 2 R L =2kΩ Supply Voltage (V) FIGURE 2-: Load Resistance. DC Open-Loop Gain vs. FIGURE 2-8: Supply Voltage. DC Open-Loop Gain vs. 23 Microchip Technology Inc. DS234E-page 7
8 .E+2.E+3.E+4.E+.E+4.E+.E+6.E+7 MCP6/2/3/4 Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Gain Bandwidth Product (MHz) V DD =.V. k k Load Resistance (Ω) GBWP PM, G = k Phase Margin, G = + ( ) DC Open-Loop Gain (db) V DD =.V,R L =2kΩ V DD =.V,R L =kω V DD =2.7V,R L =2kΩ V DD =2.7V,R L =kω Ambient Temperature ( C) FIGURE 2-9: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-22: Temperature. DC Open-Loop Gain vs. Output Headroom (mv); V DD - V OH and V OL - V SS, V DD -V OH V OL -V SS.. Output Current Magnitude (ma) Output Headroom (mv); V DD -V OH and V OL -V SS V DD =.V R L tiedtov DD /2 V DD -V OH, R L =kω V OL -V SS, R L =kω V DD -V OH, R L =2kΩ V OL -V SS, R L =2kΩ Ambient Temperature ( C) FIGURE 2-2: vs. Output Current. Output Voltage Headroom FIGURE 2-23: vs. Temperature. Output Voltage Headroom Maximum Output Voltage Swing (V P-P ). k k Frequency (Hz) M V DD =.V M Output Short Circuit Current Magnitude (ma) T A = -4 C T A = +2 C T A = +8 C T A = +2 C Supply Voltage (V) FIGURE 2-2: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-24: vs. Supply Voltage. Output Short-Circuit Current DS234E-page 8 23 Microchip Technology Inc.
9 E+.E-6 2.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E-.E+.E-6.E-.E- 2.E- 2.E- 3.E- 3.E- 4.E- 4.E-.E E+.E-6 2.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E- MCP6/2/3/4 Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Output Voltage (V) V DD =.V G = + Time ( µs/div) Output Voltage (V) V DD =.V G = - Time ( µs/div) FIGURE 2-2: Pulse Response. Large Signal Non-Inverting FIGURE 2-28: Response. Large Signal Inverting Pulse Output Voltage (2 mv/div) V DD =.V G = + Output Voltage (2 mv/div) V DD =.V G = -.E+.E-6 2.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E- Time ( µs/div).e+.e-6 2.E-6 3.E-6 4.E-6.E-6 6.E-6 7.E-6 8.E-6 9.E-6.E- Time ( µs/div) FIGURE 2-26: Pulse Response. Small Signal Non-Inverting FIGURE 2-29: Response. Small Signal Inverting Pulse Output Voltage, Chip Select Voltage (V) CS V OUT Active Time ( µs/div) V DD =.V G=+ V IN =2.V R L = kω to GND V OUT High-Z Quiescent Current through V SS (µa) V DD =.V Chip Select Voltage (V) FIGURE 2-27: (MCP63). Chip Select Timing FIGURE 2-3: Quiescent Current Through V SS vs. Chip Select Voltage (MCP63). 23 Microchip Technology Inc. DS234E-page 9
10 .E+.E-6.E-.E- 2.E- 2.E- MCP6/2/3/4 Note: Unless otherwise indicated, T A = +2 C, V DD = +2.7V to +.V, V SS = GND, V CM = V DD /2, R L = kω to V DD /2, V OUT V DD /2, and C L = pf. Chip Select Pin Current (µa).8 V DD =.V (Input and Output Voltages (V) V DD = +.V G = +2 V IN V OUT Chip Select Voltage (V) Time ( µs/div) FIGURE 2-3: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-33: The MCP6/2/3/4 family of op amps shows no phase reversal under input overdrive. Internal Chip Select Switch Output Voltage (V) Amplifier On CS Hi to Low CS Low to Hi V DD =.V. Amplifier Hi-Z Chip Select Voltage (V) FIGURE 2-32: Internal Switch. Hysteresis of Chip Select s DS234E-page 23 Microchip Technology Inc.
11 MCP6/2/3/4 3. APPLICATIONS INFORMATION The MCP6/2/3/4 family of operational amplifiers are fabricated on Microchip s state-of-the-art CMOS process. They are unity-gain stable and suitable for a wide range of general purpose applications. 3. Input The MCP6/2/3/4 amplifier family is designed to not exhibit phase reversal when the input pins exceed the supply rails. Figure 2-33 shows an input voltage that exceeds both supplies with no resulting phase inversion. The Common Mode Input Voltage Range (V CMR ) includes ground in single supply systems (V SS ), but does not include V DD. This means that the amplifier input behaves linearly as long as the Common Mode Input Voltage (V CM ) is kept within the specified V CMR limits (V SS -.3V to V DD -.2V at +2 C). Input voltages that exceed the input voltage range (V SS -.3V to V DD -.2V at +2 C) can cause excessive current to flow into, or out of, the input pins. Current beyond ±2 ma may cause reliability problems. Applications that exceed this rating must externally limit the input current with a resistor (R IN ), as shown in Figure 3-. V IN R IN R IN FIGURE 3-: into an input pin. R IN MCP6X (maximum expected V IN ) - V DD 2mA V SS - (minimum expected V IN ) 2mA 3.2 Rail-to-Rail Output R IN limits the current flow There are two specifications that describe the output swing capability of the MCP6/2/3/4 family of operational amplifiers. The first specification, Maximum Output Voltage Swing, defines the absolute maximum swing that can be achieved under the specified load conditions. For instance, the output voltage swings to within mv of the negative rail with a 2 kω load to V DD /2. Figure 2-33 shows how the output voltage is limited when the input goes beyond the linear region of operation. The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Swing. This specification defines the maximum output swing that can be achieved while the amplifier is still operating in its linear region. To verify linear operation in this range, the large signal, DC Open-Loop Gain (A OL ), is measured at points mv inside the supply rails. The measurement must exceed the specified gains in the spec table. 3.3 MCP63 Chip Select The MCP63 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to -.7 µa (typ.), which is pulled through the CS pin to V SS. When this happens, the amplifier output is put into a high impedance state. Pulling CS low enables the amplifier. If the CS pin is left floating, the amplifier may not operate properly. Figure - is the Chip Select timing diagram and shows the output voltage, supply currents and CS current in response to a CS pulse. Figure 2-27 shows the measured output voltage response to a CS pulse. 3.4 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response with overshoot and ringing in the step response. When driving large capacitive loads with these op amps (e.g., > 4 pf when G = +), a small series resistor at the output (R ISO in Figure 3-2) improves the feedback loop s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. R G MCP6X R F R ISO FIGURE 3-2: Output resistor R ISO stabilizes large capacitive loads. V OUT Figure 3-3 gives recommended R ISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (C L /G N ) to make it easier to interpret the plot for arbitrary gains. G N is the circuit s noise gain. For non-inverting gains, G N and the gain are equal. For inverting gains, G N is + Gain (e.g., - V/V gives G N = +2 V/V). C L 23 Microchip Technology Inc. DS234E-page
12 ,,, MCP6/2/3/4 Recommended R ISO ( ) k p p n n Normalized Load Capacitance; C L / G N (F) FIGURE 3-3: Recommended R ISO values for capacitive loads. After selecting R ISO for your circuit, double-check the resulting frequency response peaking and step response overshoot in your circuit. Evaluation on the bench and simulations with the MCP6/2/3/4 SPICE macro model are very helpful. Modify R ISO s value until the response is reasonable. 3. Supply Bypass With this family of operational amplifiers, the power supply pin (V DD for single supply) should have a local bypass capacitor (i.e.,. µf to. µf) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., µf or larger) within mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.6 PCB Surface Leakage In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 2 Ω. A V difference would cause pa of current to flow. This is greater than the MCP6/2/3/4 family s bias current at +2 C ( pa, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-4. FIGURE 3-4: Guard Ring G N = + G N +2 V IN V IN+ Example guard ring layout.. Connect the guard ring to the inverting input pin (V IN ) for non-inverting gain amplifiers, including unity-gain buffers. This biases the guard ring to the common mode input voltage. 2. Connect the guard ring to the non-inverting input pin (V IN+ ) for inverting gain amplifiers and transimpedance amplifiers (convert current to voltage, such as photo detectors). This biases the guard ring to the same reference voltage as the op amp (e.g., V DD /2 or ground). 3.7 Typical Applications 3.7. ANALOG FILTERS Figure 3- and Figure 3-6 show low-pass, secondorder, Butterworth filters with a cutoff frequency of Hz. The filter in Figure 3- has a non-inverting gain of + V/V, and the filter in Figure 3-6 has an inverting gain of - V/V. V IN FIGURE 3-: Key filter. V IN R R kω 64 kω C 2 47 nf FIGURE 3-6: Feedback filter. C 47 nf C 2 22 nf R 2 68 kω MCP6X R R 3 C 68 kω. MΩ 8.2 nf V DD /2 G = + V/V f P = Hz V OUT 2 nd order, low-pass Sallen- MCP6X G = - V/V f P = Hz V OUT 2 nd order, low-pass Multiple- The MCP6/2/3/4 family of operational amplifiers have low input bias current, which allows the designer to select larger resistor values and smaller capacitor values for these filters. This helps produce a compact PCB layout. These filters, and others, can be designed using Microchip s FilterLab software. DS234E-page 2 23 Microchip Technology Inc.
13 MCP6/2/3/ INSTRUMENTATION AMPLIFIER CIRCUITS Instrumentation amplifiers have a differential input, which subtracts one input voltage from another and rejects common mode signals. These amplifiers also provide a single-ended output voltage. The three op amp instrumentation amplifier is illustrated in Figure 3-7. One advantage of this approach is unity-gain operation. A disadvantage is that the common mode input range is reduced as R 2 /R G gets larger. V MCP6X R G R 2 R 2 R 3 R 4 MCP6X R 3 R 4 V OUT PHOTO DETECTION The MCP6/2/3/4 op amps can be used to easily convert the signal from a sensor that produces an output current (such as a photo diode) into a voltage (a transimpedance amplifier). This is implemented with a single resistor (R 2 ) in the feedback loop of the amplifiers shown in Figure 3-9 and Figure 3-. The optional capacitor (C 2 ) sometimes provides stability for these circuits. A photodiode configured in the photovoltaic mode has zero voltage potential placed across it (Figure 3-9). In this mode, the light sensitivity and linearity is maximized, making it best suited for precision applications. The key amplifier specifications for this application are: low input bias current, low noise, common mode input voltage range (including ground) and rail-to-rail output. C 2 R 2 V 2 MCP6X V OUT = (V - V 2 ) V REF 2R 2 R V R G R REF 3 Light I D D MCP6X V DD V OUT FIGURE 3-7: Three op amp instrumentation amplifier. The two op amp instrumentation amplifier is shown in Figure 3-8. Its power consumption is lower than the three op amp version. Its main drawbacks are that the common mode range is reduced with higher gains and it must be configured in gains of two or higher. R R G R 2 R 2 R V OUT FIGURE 3-9: V OUT = I D R 2 Photovoltaic mode detector. In contrast, a photodiode that is configured in the photoconductive mode has a reverse bias voltage across the photo sensing element (Figure 3-). This decreases the diode capacitance, which facilitates high-speed operation (e.g., high-speed digital communications). The design trade off is increased diode leakage current and linearity errors. The op amp needs to have a wide Gain Bandwidth Product. C 2 V REF MCP6X MCP6X V 2 R 2 V I D V DD V OUT V OUT = (V - V 2 ) FIGURE 3-8: amplifier. R 2R V R 2 R REF G Two op amp instrumentation Both instrumentation amplifiers should use a bulk bypass capacitor of at least µf. The CMRR of these amplifiers will be set by the op amp CMRR and by resistor matching. D Light V BIAS FIGURE 3-: Detector. MCP6X V OUT = I D R 2 V BIAS < V Photoconductive Mode 23 Microchip Technology Inc. DS234E-page 3
14 MCP6/2/3/4 4. DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6/2/3/4 family of op amps. 4. SPICE Macro Model The latest SPICE macro model of the MCP6/2/3/4 operational amplifiers is available on our website (at This model is intended as an initial design tool that works well in the op amp s linear region of operation at room temperature. See the SPICE model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specs and plots. 4.2 FilterLab 2. FilterLab 2. is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from our web site (at the FilterLab active filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the Macro Model to simulate actual filter performance. DS234E-page 4 23 Microchip Technology Inc.
15 MCP6/2/3/4. PACKAGING INFORMATION. Package Marking Information -Lead SOT-23 (MCP6 and MCP6R Only) Example: XXNN SANN 6-Lead SOT-23A (MCP63 Only) Example: XXNN AUNN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January is week ) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. 23 Microchip Technology Inc. DS234E-page
16 MCP6/2/3/4 Package Marking Information 8-Lead PDIP (3 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6 I/P Lead SOIC ( mil) Example: XXXXXXXX XXXXYYWW NNN MCP6 I/SN Lead TSSOP Example: XXXX XYWW NNN 6 I Lead PDIP (3 mil) (MCP64 Only) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP64-I/P XXXXXXXXXXXXXX Lead SOIC ( mil) (MCP64 Only) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP64ISL XXXXXXXXXXX Lead TSSOP (4.4mm) (MCP64 Only) Example: XXXXXXXX YYWW NNN 64I DS234E-page 6 23 Microchip Technology Inc.
17 MCP6/2/3/4 -Lead Plastic Small Outline Transistor (OT) (SOT-23) E E p B p D n α c A A2 β L φ A Units Dimension Limits Number of Pins n Pitch p Outside lead pitch (basic) p Overall Height A Molded Package Thickness A2 Standoff A Overall Width E Molded Package Width E Overall Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic MIN INCHES* NOM MAX MILLIMETERS MIN NOM Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MO-78 Drawing No. C4-9 MAX Microchip Technology Inc. DS234E-page 7
18 MCP6/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E B p D n α c A A2 φ β L A Units Dimension Limits Number of Pins n Pitch p Outside lead pitch (basic) p Overall Height A Molded Package Thickness A2 Standoff A Overall Width E Molded Package Width E Overall Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β *Controlling Parameter MIN INCHES* NOM MAX MILLIMETERS MIN NOM Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed." (.27mm) per side. MAX JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C4-2 DS234E-page 8 23 Microchip Technology Inc.
19 MCP6/2/3/4 8-Lead Plastic Dual In-line (P) 3 mil (PDIP) E 2 D n α E A A2 c A L β eb B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p. 2.4 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS- Drawing No. C Microchip Technology Inc. DS234E-page 9
20 MCP6/2/3/4 8-Lead Plastic Small Outline (SN) Narrow, mil (SOIC) E E p 2 D B n 4 h α c A A2 φ β L A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p..27 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α 2 2 Mold Draft Angle Bottom β 2 2 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS-2 Drawing No. C4-7 DS234E-page 2 23 Microchip Technology Inc.
21 MCP6/2/3/4 8-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) E E p 2 D B n A α c φ A A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p.26.6 Overall Height A.43. Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.27mm) per side. JEDEC Equivalent: MO-3 Drawing No. C Microchip Technology Inc. DS234E-page 2
22 MCP6/2/3/4 4-Lead Plastic Dual In-line (P) 3 mil (PDIP) E D 2 n α E A A2 c L β eb A B B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p. 2.4 Top to Seating Plane A Molded Package Thickness A Base to Seating Plane A..38 Shoulder to Shoulder Width E Molded Package Width E Overall Length D Tip to Seating Plane L Lead Thickness c Upper Lead Width B Lower Lead Width B Overall Row Spacing eb Mold Draft Angle Top α Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic β Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS- Drawing No. C4- DS234E-page Microchip Technology Inc.
23 MCP6/2/3/4 4-Lead Plastic Small Outline (SL) Narrow, mil (SOIC) E E p D 2 B n 4 h α c A A2 β L φ A Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 4 4 Pitch p..27 Overall Height A Molded Package Thickness A Standoff A Overall Width E Molded Package Width E Overall Length D Chamfer Distance h Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α 2 2 Mold Draft Angle Bottom β 2 2 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.24mm) per side. JEDEC Equivalent: MS-2 Drawing No. C Microchip Technology Inc. DS234E-page 23
24 MCP6/2/3/4 4-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP) p E E D B n 2 A α c φ β L A A2 Units Dimension Limits Number of Pins n Pitch p Overall Height A Molded Package Thickness A2 Standoff A Overall Width E Molded Package Width E Molded Package Length D Foot Length L Foot Angle φ Lead Thickness c Lead Width B Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Significant Characteristic MIN INCHES NOM MAX MIN MILLIMETERS* NOM 4.6 Notes: Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. (.27mm) per side. JEDEC Equivalent: MO-3 Drawing No. C MAX DS234E-page Microchip Technology Inc.
25 MCP6/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Range Package Device MCP6 Single Op Amp MCP6T Single Op Amp (Tape and Reel for SOT23, SOIC and TSSOP) MCP6RT Single Op Amp (Tape and Reel for SOT23-) MCP62 Dual Op Amp MCP62T Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP63 Single Op Amp with Chip Select MCP63T Single Op Amp with Chip Select (Tape and Reel for SOT23, SOIC and TSSOP) MCP64 Quad Op Amp MCP64T Quad Op Amp (Tape and Reel for SOIC and TSSOP) Temperature Range I = -4 C to +8 C E = -4 C to +2 C Package OT = Plastic SOT23, -lead (MCP6 only) CH = Plastic SOT23, 6-lead (MCP63 only) P = Plastic DIP (3 mil Body), 8, 4-lead SN = Plastic SOIC ( mil Body), 8-lead SL = Plastic SOIC ( mil Body), 4-lead ST = Plastic TSSOP (4.4mm Body), 8, 4-lead a) MCP6-I/P: Single Op Amp, Industrial Temp., 8LD PDIP package. b) MCP6-E/SN: Single Op Amp, Extended Temp., 8LD SOIC package. c) MCP6T-I/OT: Tape and Reel, Industrial Temp., Single Op Amp, -LD SOT23 package. d) MCP6T-E/ST: Tape and Reel, Extended Temp., Single Op Amp, 8LD TSSOP package e) MCP6RT-E/OT: Tape and Reel, Extended Temp., Single Op Amp, Rotated, -LD SOT23 package. a) MCP62-I/SN: Dual Op Amp, Industrial Temp., 8LD SOIC package. b) MCP62-E/P: Dual Op Amp, Extended Temp., 8LD PDIP package. c) MCP62T-E/ST: Tape and Reel, Extended Temp., Dual Op Amp, 8LD TSSOP package. a) MCP63-I/SN: Industrial Temp., Single Op Amp with Chip Select, 8LD SOIC package. b) MCP63-E/P: Extended Temp., Single Op Amp with Chip Select, 8LD PDIP package. c) MCP63T-E/ST: Tape and Reel, Extended Temp., Single Op Amp with Chip Select, 8LD TSSOP package. d) MCP63T-I/SN: Tape and Reel, Industrial Temp., Single Op Amp with Chip Select, 8LD SOIC package. a) MCP64-I/P: Industrial Temp., Quad Op Amp, 4LD PDIP package. b) MCP64-E/SL: Extended Temp., Quad Op Amp, 4LD SOIC package. c) MCP64T-I/ST: Tape and Reel, Industrial Temp., Quad Op Amp, 4LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (48) The Microchip Worldwide Site ( Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site ( to receive the most current information on our products. 23 Microchip Technology Inc. DS234E-page 2
26 MCP6/2/3/4 NOTES: DS234E-page Microchip Technology Inc.
27 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microid, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dspicdem, dspicdem.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rflab, rfpic, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 23, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 999 and Mountain View, California in March 22. The Company s quality system processes and procedures are QS-9 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9 certified. DS234E-page Microchip Technology Inc.
28 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 23 West Chandler Blvd. Chandler, AZ Tel: Fax: Technical Support: Web Address: Atlanta 378 Mansell Road, Suite 3 Alpharetta, GA 322 Tel: Fax: Boston 2 Lan Drive, Suite 2 Westford, MA 886 Tel: Fax: Chicago 333 Pierce Road, Suite 8 Itasca, IL 643 Tel: Fax: Dallas 47 Westgrove Drive, Suite 6 Addison, TX 7 Tel: Fax: Detroit Tri-Atria Office Building 322 Northwestern Highway, Suite 9 Farmington Hills, MI Tel: Fax: Kokomo 2767 S. Albright Road Kokomo, IN 4692 Tel: Fax: Los Angeles 82 Von Karman, Suite 9 Irvine, CA 9262 Tel: Fax: Phoenix 23 West Chandler Blvd. Chandler, AZ Tel: Fax: San Jose 27 North First Street, Suite 9 San Jose, CA 93 Tel: Fax: Toronto 628 Northam Drive, Suite 8 Mississauga, Ontario L4V X, Canada Tel: Fax: ASIA/PACIFIC Australia Suite 22, 4 Rawson Street Epping 22, NSW Australia Tel: Fax: China - Beijing Unit 9 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 27, No. China Tel: Fax: China - Chengdu Rm , 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 66, China Tel: Fax: China - Fuzhou Unit 28F, World Trade Plaza No. 7 Wusi Road Fuzhou 3, China Tel: Fax: China - Hong Kong SAR Unit 9-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: Fax: China - Shanghai Room 7, Bldg. B Far East International Plaza No. 37 Xian Xia Road Shanghai, 2 Tel: Fax: China - Shenzhen Rm. 82, 8/F, Building A, United Plaza No. 22 Binhe Road, Futian District Shenzhen 833, China Tel: Fax: China - Shunde Room 4, Hongjian Building No. 2 Fengxiangnan Road, Ronggui Town Shunde City, Guangdong 2833, China Tel: Fax: China - Qingdao Rm. BA, Fullhope Plaza, No. 2 Hong Kong Central Rd. Qingdao 2667, China Tel: Fax: India Divyasree Chambers Floor, Wing A (A3/A4) No., O Shaugnessey Road Bangalore, 6 2, India Tel: Fax: Japan Benex S- 6F 3-8-2, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, , Japan Tel: Fax: Korea 68-, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: Fax: or Singapore 2 Middle Road #7-2 Prime Centre Singapore, 8898 Tel: Fax: Taiwan Kaohsiung Branch 3F - No. 8 Min Chuan 2nd Road Kaohsiung 86, Taiwan Tel: Fax: Taiwan Taiwan Branch F-3, No. 27 Tung Hua North Road Taipei,, Taiwan Tel: Fax: EUROPE Austria Durisolstrasse 2 A-46 Wels Austria Tel: Fax: Denmark Regus Business Centre Lautrup hoj -3 Ballerup DK-27 Denmark Tel: Fax: France Parc d Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 93 Massy, France Tel: Fax: Germany Steinheilstrasse D-8737 Ismaning, Germany Tel: Fax: Italy Via Quasimodo, 2 22 Legnano (MI) Milan, Italy Tel: Fax: Netherlands P. A. De Biesbosch 4 NL-2 SC Drunen, Netherlands Tel: Fax: United Kingdom Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG4 TU Tel: Fax: /28/3 DS234E-page Microchip Technology Inc.
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