This document is an author-formatted work. The definitive version for citation appears as: R. Zand, A. Roohi, D. Fan and R. F.

Transcription

1 This document is an author-formatted work. The definitive version for citation appears as: R. Zand, A. Roohi, D. Fan and R. F. DeMara, "Energy-Efficient Nonvolatile Reconfigurable Logic Using Spin Hall Effect-Based Lookup Tables," in IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp , Jan doi: /TNANO

2 1 Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables Ramtin Zand, Arman Roohi, Deliang Fan, and Ronald F. DeMara Department of Engineering and Computer Science University of Central Florida Orlando, FL, USA Abstract In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE-MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE-MTJ based LUT is validated using SPICE simulation. Our proposed SHE-MTJ based LUT (SHE-LUT) is compared with the most energy-efficient MTJ-based LUT circuits. The obtained results show more than 6%, 37%, and 67% improvement over three previous MTJ-based designs in term of read energy consumption. Moreover, the reconfiguration delay and energy of the proposed design is compared with that of the MTJ-based LUTs which utilize the spin transfer torque (STT) switching approach for reconfiguration. The results exhibit that SHE-LUT can operate at 78% higher clock frequency while achieving at least 21% improvement in terms of reconfiguration energy consumption. The operationspecific clocking mechanisms for managing the SHE-LUT operations are introduced along with detailed analyses concerning tradeoffs. Results are extended to design a 6-input fracturable LUT using SHE-MTJs. Index Terms Fracturable LUT, Magnetic tunnel junction, reconfigurable fabric, spin-based memory cell, spin Hall effect, spin transfer torque. I. INTRODUCTION The main motivations for embracing reconfigurable fabrics namely Field Programming Gate Arrays (FPGAs) could be divided into two categories: (1) flexibility and accessibility: fabric flexibility allows realization of logic elements at medium and fine granularities while incurring low non-recurring engineering and rapid deployment to market, and (2) resiliency and runtime adaptability: reconfigurable fabrics have been demonstrated to provide a viable solution for process-voltage-temperature variation induced problems and could be utilized effectively for fault recovery [1-3]. However these advantages are achieved at a cost of increased fabric area and power consumption, as well as a decrease in performance compared to the application-specific integrated circuits (ASICs). Innovations using emerging devices within reconfigurable fabrics have been sought to bridge the gaps needed to provide these benefits. Currently, static random access memory (SRAM) cells are the basis for most of the commercial FPGAs, and can be found in the well-known Xilinx and Altera products. In FPGAs, SRAM cells are employed within programmable switching blocks to control the interconnection between logic building blocks. Moreover, they are utilized in lookup-tables (LUTs) to store the logic function configuration data, which constitute the primary components in reconfigurable fabrics [4]. The re-programmability of the SRAM cells, and the fact that they can be implemented by highly-scaled MOS technology, have made the SRAM-based FPGAs the most popular reconfigurable fabrics. However, SRAM cells have some limiting attributes which caused FPGAs to have a niche market share of ASICs. In [5], Kuon and Rose have provided a comprehensive comparison between SRAM-based FPGAs and ASICs in terms of area, performance, and power consumption. They have reported that in order to achieve a same functionality and performance in an FPGA as an ASIC, FPGA requires significantly larger area while consuming approximately 14 times more power. This is mainly due to the crucial drawbacks of the SRAM cells such as: high static power, volatility, and low logic density. Due to the mentioned concerns associated with the SRAM cells, considerable attention has been recently attracted to alternative emerging memory technologies to be integrated in reconfigurable fabrics. One of the introduced alternatives is based on nonvolatile flash-based LUTs, however it targets a niche market due to their low reconfiguration endurance [6]. Higher endurance non-volatile LUTs can be enabled by emerging resistive technologies, such as spintronic storage elements [7-12], resistive random access memory (RRAM) [13-16], and phase change memory (PCM) [17, 18]. Although PCM can offer non-volatility, its considerable reconfiguration power and high write latency can significantly exceed that of an SRAM LUT. Spintronic devices offer non-volatility, near-zero static power, and high integration density [19, 20]. Two of the spin-based devices, which are previously proposed for use in reconfigurable fabrics are spin transfer torque (STT)-based magnetic tunnel junctions (MTJs) [7-10] and domain wall (DW)-based racetrack memory (RM) [11, 12]. In this paper, we develop a 4-input nonvolatile LUT using spin Hall effect (SHE)-based MTJ devices, and provide a detailed comparison between the SHE-MTJ-based LUT (SHE-LUT) and 2-terminal MTJ-based LUTs including the reconfiguration energy consumption and delay. The remainder of this paper is organized as follows. The related work are studied in Section II. Section III provides a comprehensive description regarding fundamentals of the perpendicular and in-plane MTJ devices. STT-MTJ and SHE-MTJ modeling approaches are elaborated in Section IV. Section V provides the SHE-LUT circuit design and describes its components, as well as a circuit design of a 6-input fracturable SHE-LUT. The proposed circuit simulation results and comparison with previous MTJ-based LUTs are provided in Section VI. Advances in clocking schemes for MTJ-based LUTs are investigated in Section VII.

3 2 Finally, Section VIII concludes the paper and highlights our proposed design advantages and features. II. RELATED WORK In FPGA LUTs, three types of energy consumption profiles can be identified. First, LUTs at configuration time must be written to, which incurs an initial write energy consumption. Second, upon configuration the LUTs comprising active logic paths will consume read energy, which may constitute only certain sub areas within high gate equivalent capacity of contemporary FPGA chips. Third, the remaining significant quantity of the LUTs comprising the fabric that may be inactive, thus consuming standby energy. Consequently, it is not possible to power-gate LUT islands, as they must retain the stored configuration. It has been estimated in [15] that if the combined effect of these three modes can be mitigated with a suitable SRAM alternative, then typical power consumption can be reduced up to 81% under representative applications based on measurements of fabricated devices. In [21], Suzuki et al. have fabricated a nonvolatile FPGA with input STT-MTJ based LUTs under 90nm CMOS and 75nm perpendicular MTJ technologies. They have utilized the LUT designs introduced in [8, 9], and in addition to the mentioned energy savings they also achieved 56% area reduction. In [22], Zand et al. have introduced a new STT-MTJ based LUT design (STT-LUT). They provided a comparison between their proposed LUT and the design introduced by Suzuki et al. in [9], which was the basis of the aforementioned fabricated MTJ-based FPGA. The comparison results show an additional 42% reduction in active power consumption for read operations. Therefore, even more power reduction is expected, in comparison to what is achieved in [21], by fabricating a nonvolatile FPGA based on the LUT design introduced in [22]. It is worth noting that the mentioned total power reductions are achieved using MTJs that utilize STT switching approach for reconfiguration operation, which consumes approximately ten times greater power than that of the conventional SRAM cells [23]. Thus, extensions to accommodate the increased write energy consumed by MTJ-based LUTs are sought to be addressed. Despite the mentioned advantages of conventional MTJ devices, their main challenge is relatively high switching delay and power consumption. Moreover, they are two-terminal devices that can experience occasional read/write disturbances due to sharing a common path for read and write operations. Recently, 3-terminal spin Hall effect (SHE)-based MTJ has been introduced as an alternative for conventional 2-terminal MTJs. SHE-MTJ provides separate paths for read and write operations, while expending significantly less switching energy [24-26]. The fundamentals of the 2-terminal and 3-terminal MTJ devices are described in next section. III. FUNDAMENTALS OF MAGNETIC TUNNEL JUNCTION In recent years, MTJs are widely researched as an alternative for CMOS technology spanning both logic and memory functionalities [27, 28]. MTJs consist of two ferromagnetic (FM) layers, called Fixed Layer and Free Layer, which are separated by a thin oxide barrier, e.g. MgO [29]. Figure 1 (a) depicts the vertical structure of an MTJ [30, 31]. Fixed layer is magneticallypinned and utilized as a reference layer, while the free layer magnetic orientation can be switched. There are two different magnetization configurations for ferromagnetic layers, parallel (P) and antiparallel (AP), according to which MTJ resistance changes between R P and R AP, respectively. MTJ resistance is determined by the angle (θ) between the magnetization orientations of fixed layer and free layer due to the tunnel magnetoresistance (TMR) effect. The MTJ resistance in P (θ = 0 ), and AP (θ = 180 ) states is expressed by the following equations [32-34] : 1 + TMR R(θ) = 2R MTJ 2 + TMR + TMR. cosθ R p = R MTJ, θ = 0 = { R ap = R MTJ (1 + TMR), θ = 180 R MTJ = t ox Factor Area. φ exp (1.025 t ox. φ) TMR = TMR(0) 1 + ( V b ) 2 V h (3) (1) (2) V V + Al 2 O 3 Cr/Au Ru Ta FM MgO FM Ta Ru Ta Si/SiO 2 Al 2 O 3 fixed layer (NiFe) tunnel barrier (MgO) free layer (NiFe) fixed layer (CoFeB) tunnel barrier (MgO) free layer (CoFeB) (c) (a) Fig. 1. (a) MTJ vertical structure [24, 25], (b) In-plane MTJ (IMTJ), and (c) Perpendicular MTJ (PMTJ). (b)

4 3 where V b is the bias voltage, and V h = 0.5V is the bias voltage when TMR is half of the TMR 0, t ox is the oxide thickness of MTJ, Factor is obtained from the resistance-area product value of the MTJ that relies on the material composition of its layers, Area is the surface of MTJ, and φ is the oxide layer energy barrier height. The energy barrier between P and AP configurations of MTJ is in a range such that it can switch between configurations, while also retaining thermal stability. The magnetic direction of MTJ layers can be in the film plane, in-plane MTJ (IMA), or out of the film plane referred to as perpendicular MTJ (PMA) structure, as shown in Fig. 1(b) and 1(c), respectively. PMAs have advantages over IMAs such as lower switching critical current and higher thermal stability. Equations (4) and (5) express the switching critical current for IMA (I c-ima) [35] and PMA (I c-pma) [30], respectively. I c IMTJ = 2αeM s V (H C + H eff 2 ) /g(θ)ph (4) I c PMTJ = αγem s H k V/μ B g(θ) (5) The parameter α is the magnetic damping constant, μ B is the Bohr magneton, γ is the gyromagnetic ratio, e is the electric charge, V is the volume of the free layer, M s is the saturation magnetization, h is the reduced Planck's constant, H C is the in-plane coercive field, H eff is the effective out-of-plane demagnetization field, and H k is the anisotropy field. The effective demagnetization field in IMA is approximately equal to the saturation magnetization, which is normally larger than anisotropy field in PMA. Thus, switching current for PMA is smaller than that of the IMA devices according to the Equations (4) and (5). Moreover, spin polarization efficiency factor, g(θ), is a function of the angle between free layer and fixed layer magnetization directions (θ), and is obtained by the Equations (6) and (7) for IMA [36] and PMA [34] devices, respectively. g IMTJ = [ 4 + (P 1/2 + P 1/2 ) (3 + cosθ)/4] 1 (6) g PMTJ = g SV ± g tunnel g SV = [ 4 + (P 1/2 + P 1/2 ) 3 (3 + cosθ)/4] 1 g tunnel = (P 2)/(1 + P 2 cosθ) (7) where P is the spin polarization percentage of the tunnel current, g SV is the spin polarization efficiency in a spin valve and g tunnel is the spin polarization efficiency in tunnel junction nanopillars. IV. MAGNETIC TUNNEL JUNCTION MODEL Field-induced magnetic switching (FIMS) [37] and thermally assisted switching (TAS) [38] are the first generation of the techniques proposed for changing the MTJ configurations. FIMS and TAS approaches consume significant power, thus they are not favorable for low power designs. In 1996, Slonczewski [39] proposed STT switching approach which is known as a promising method for changing the MTJ states. Although STT switching showed a handful of advantages compared with the FIMS and TAS methods, its energy consumption is still significantly larger than that of required for switching the SRAM cells. Consequently, SHE and Rashba effect are investigated recently to achieve an alternative low power switching approach [24-26]. In this section, the fundamentals of STT and SHE-assisted switching methods are provided along with the physical equations and relations which are required for modeling these approaches. A. Modeling the Spin Transfer Torque (STT) Switching Based on the STT approach, a bidirectional spin-polarized current (I MTJ) is required for switching MTJ nanomagnet configuration, as shown in Fig. 2. Electrons that flow through the MTJ free layer will experience an exchange field which aligns the spin of the electron with the magnetization direction of the nanomagnet. This phenomenon is called spin-filtering effect. The conservation of the angular momentum results in the exertion of an opposite sign torque with equal magnitude on the free layer which eventually change its magnetization direction. The P or AP configuration of the MTJ is determined by the direction of the current that flows through it. The required bidirectional current could be produced by means of simple MOS-based circuits. Due to the vertical structure of the MTJ, it can be readily integrated at the back-end process of the CMOS fabrication [27, 28]. According I MTJ Logic 0 R MTJ R AP I MTJ I AP-P Logic 1 I MTJ I P-AP (a) I MTJ I P-AP R P (b) I AP-P I MTJ Fig. 2. (a) MTJ state change from AP to P due to the positive current I MTJ>I AP-P condition, and vice versa. (c) MTJ resistance hysteresis curve relative to the I MTJ.

5 4 to the relative amplitude of the I MTJ and the switching critical current (I C), STT switching behavior can be categorized into two main regions: (1) precessional region (I MTJ > I C), and (2) thermal activation region (I MTJ < I C) which are described by Sun model [40] and Ne el-brown model [41], respectively. In the precessional region, MTJ experiences a rapid precessional switching. Equation (8) describes the switching duration of the MTJ in this region [28]. 1 τ STT = [ 2 C + ln(π 2 ) ] μ B P em(1 + P 2 ) (I MTJ I C ) (8) where τ STT is the mean duration for precessional switching region, C=0.577 is the Euler s constant, Δ= E 4k B T is the thermal stability factor, and m is the free layer magnetic moment. In the thermal activation region, although the current is less than the critical value, the switching can occur with a long input current pulse due to the thermal activation. The switching duration in the thermal activation region is described by below equation [28]: 1 τ STT = τ 0 exp ( (1 I MTJ I C )) (9) where τ STT is the mean pulse duration for the thermal activation region, and τ 0 is the attempt period. In practice, in order to have high switching speed, MTJ is required to work in precessional region with current amplitude larger than critical current. While STT approach offers significant advantages in terms of read energy and speed, a significant incubation delay due to the pre-switching oscillation [42, 43] incurs high switching energy. Recently, SHE-MTJ is introduced as an alternative for 2-terminal MTJs, which provides separate paths for read and write operations, while expending significantly less switching energy [44-47]. B. Modeling the Spin Hall Effect (SHE) Switching As mentioned, spin-polarized currents can be utilized to generate the torque required for switching the magnetization directions of the free layer in MTJs. It is shown in [24] that a spin current can be produced in nanomagnetic devices by the spin Hall effect. In [45], Manipatruni et al. have provided the physical equations of the three-terminal SHE-MTJ device behavior. Figure 3 shows the structure of the SHE-MTJ device, in which the magnetic orientation of the free layer changes by passing a charge current through a heavy metal (HM). MTJ free layer is directly connected to HM which is normally made of β-tantalum (β -Ta) [24], βtungsten (β -W) [26] or Pt [48]. The MTJ logic state that is defined by the free layer magnetic direction is determined by the direction of the applied charge current. The spin-orbit coupling in HM deflects the electrons with different spins in opposite directions, which results in a spin injection current transverse to the applied charge current. The injected current produces the required spin torque for aligning the magnetic direction of the free layer. Ratio of the injected spin current to the applied charge current, called spin Hall injection efficiency (SHIE), is defined by Equation (10): SHIE = I sz = π.mtj width I cx 4HM thick θ SHE [1 sech ( HM thick λ sf )] (10) where HM width is the width of the HM, HM thick is the thickness of the HM, λ sf is the spin flip length in HM, and ϴ SHE is the SHE angle [45]. This equation is valid for SHE-MTJ devices in which length of the MTJ equals the width of the HM. In this paper, SHIE value is equal to 1.73 that is extracted using Equation (10) and the parameters mentioned in Table I. Thus, the generated spin current is larger than the applied charge current. Whereas the spin injection efficiency of a 2-terminal MTJ is normally less than one resulting in a favorable write switching energy for SHE-MTJs used in LUTs herein, as quantified by Equation (10). The critical spin current required for switching the free layer magnetization orientation is expressed by Equation (11) [49]: I S,critical = 2qαM S V MTJ (H k + 2πM S )/h (11) y z x I READ T 2 spin-polarized I WRITE current MTJ Width T 1 charge current T 3 HM Width MTJ Length HM Length (a) Fig. 3. (a) SHE-MTJ vertical structure. Positive current along +x induces a spin injection current +z direction. The injected spin current produces the required spin torque for aligning the magnetic direction of the free layer in +y directions, and vice versa [39]. (b) SHE-MTJ Top view. (b)

6 5 where V MTJ is the MTJ free layer volume. Thus, SHE-MTJ critical charge current can be calculated using Equations (10) and (11). Equation (12) shows the relation between SHE-MTJ switching time and the voltage applied to the HM terminals with the critical voltage v c given by Equation (13) [45]. τ SHE = τ 0 ln(π/2θ 0 ) ( v v c ) 1 v c = 8ρI c {θ SHE [1 sech ( HM 1 thick )] πhm λ length } sf (12) (13) where, θ 0 = k B /2E b is the effect of stochastic variation, E b is the thermal barrier of the magnet of volume V, HM length is the length of the HM, and I C is the critical charge current for spin- torque induced switching. In order to model the SHE-MTJ, the HM resistance is also required, which is expressed by Equation (14), where ρ HM is the electrical resistivity of HM. In this paper, Verilog-AMS is utilized to model the behavior of 2-terminal MTJ and SHE-MTJ devices based on the aforementioned physical equations. Then, the model is leveraged in SPICE circuit simulator to validate the functionality of the designed circuits using experimental parameters listed in Table I, as shown in Fig. 4. R HM = (ρ HM. HM length ) (HM width HM thick ) (14) Figure 5 (a) and 5 (b) show the MOS-based bitcell of the 2-terminal MTJ and SHE-MTJ, respectively. In SHE-MTJ, the spin current can be significantly larger than the applied charge current. Therefore, the transistor utilized in the bitcell of the 2-terminal MTJ should be larger than that of the SHE-MTJ to be able to provide equal switching delay. Thus, although SHE-MTJ bitcell requires two MOS transistors, its integration density is comparable to the 2-terminal MTJs. Increasing the transistor size in 2- terminal MTJs may also results in occasional read/write disturbances due to a common read/write path. Moreover, the reliability of tunneling oxide barrier is improved in SHE-MTJ, since the current does not flow through it during the write operation. The reader is referred to [27] for additional background information regarding SHE-MTJ and SOT-MRAM devices. Verilog-A STT/SHE MTJ Resistive Behavior Parameters:,,, TMR,, F, applied voltage Equations used herein: (1), (2), (3), (14), (15) Device Modeling and Simulation R MTJ SPICE Circuit Simulator Parameters: nominal voltage transistor technology node operating frequency write current Matlab STT/SHE MTJ Switching Model Parameters: MTJ and HM Volume,,,, g,,,,, P Equations used herein: (5), (7), (8), (10), (11), (12), (13) power delay Fig. 4. Modeling and simulation process of STT/SHE MTJ devices. BL BL RL WL WL SL SL (a) (b) Fig. 5. (a) 2-terminal MTJ bitcell, (b) SHE-MTJ bitcell V. PROPOSED SHE-MTJ BASED LUT In this section, a non-volatile LUT circuit is developed based on the SHE-MTJ devices introduced in Section II. As shown in Fig. 6, SHE-LUT structure includes two main parts: write circuit and read circuit. Designing the read and write circuits requires considering important details which can significantly influence the energy consumption and delay of the LUT circuit. A. Read Circuit LUT is utilized in reconfigurable fabrics to implement combinational logic. In general, LUT is a memory with 2 m cells in which the truth table of an m-input Boolean function is stored. Inputs can be considered as the address according to which corresponding output of the Boolean function will be returned. The select tree in the read circuit enables accessing each of the storage cells in LUT according to the address provided by A, B, C, and D input signals. Pass Transistors (PTs) and Transmission Gates (TGs) have

7 6 TABLE I: PARAMETERS OF SHE-MTJ-BASED LUT [44-47] Parameter Description Value HM Volume HM Length HM Width HM Thickness 100 nm 60 nm 3 nm MTJ Area MTJ Length MTJ Width π/4 60nm 30nm π/4 MTJ Area Reference MTJ Surface 50nm 25nm π/4 t ox Thickness of oxide barrier 0.85 nm α Gilbert Damping factor 07 μ B Bohr Magneton 9.27e-24 J T -1 M s Saturation magnetization 7.8e5 A m -1 P Spin Polarization 0.52 γ Gyromagnetic Ratio 1.76e7 (Oe.s) -1 R AP, R P MTJ Resistances 2.8 KΩ, 5.6 KΩ R P Reference MTJ Resistance 4.12 KΩ TMR 0 TMR ratio 100% H k Anisotropy Field 80 Oe µ 0 Permeability of Free Space e-6 T.m/A θ SHE Spin Hall Angle 0.3 ρ HM HM Resistivity 200 µω.cm φ Potential Barrier Height 0.4 V Λsf Spin Flip Length 1.5nm e Electric charge 1.602e-19 C h Reduced Planck's Constant 6.626e-34/2π J.s I C-SHE SHE-MTJ Critical Current 108 µa I P-AP STT-MTJ Critical Current For P to AP Switching 37 µa I AP-P STT-MTJ Critical Current For AP to P Switching 18 µa Read Control Circuit CLK sense amplifier OUT A BC D SHE-MTJ0 TG-based Select Tree SHE-MTJ15 TG-based Reference tree reference SHE-MTJ write circuit CLK Write Control Circuit write circuit Fig. 6. Schematic of proposed 4-input SHE-based MTJ-LUT. been investigated in [22, 50] to be utilized in the LUT select tree. Results exhibited that TG-based select tree has lower propagation delay and more resiliency to process variation compared with PT-based select tree while consuming relatively equal power. Therefore, herein TG-based select tree is utilized in our proposed SHE-LUT, as shown in Fig. 7. In this paper, we have utilized SHE-MTJ as a storage element in the LUT circuit. In general, data is stored in resistive memory cells in form of different resistance levels, e.g. high resistance state stands for logic 1 and vice versa. Therefore, a sense amplifier (SA) is required to distinguish the resistive state of the memory cell. In [51], Zhao et al. studied various SAs which could be leveraged for sensing the magnetic configuration of the MTJs. They have proposed a Pre-Charge Sense Amplifier (PCSA) consisting of seven MOS transistors and a reference MTJ, which could provide a low power and high speed read operation while maintaining a low error rate. Figure 7 shows the PCSA circuit which includes four PMOS transistors connected to the VDD, two NMOS transistors which connects the PMOS transistors to the select trees and data storage cells, and one NMOS transistor which connects the circuit to ground (GND). Moreover, a TG-based reference tree including four TGs in series configuration is utilized in our designs to compensate for the select tree resistance. Reference MTJ dimensions are designed in a manner such that its resistance value in parallel configuration is between low resistance, R Low, and high resistance, R High, of the SHE-based MTJ cells as shown in Fig. 8 and elaborated by below equations: R P reference MTJ 1 2 (R Low + R High ) = (R AP LUT MTJ + R P LUT MTJ )/2 + R HM /2 where, R Low = (R P LUT MTJ + R HM /2) R High = (R AP LUT MTJ + R HM /2) (15)

8 7 Read Circuit Pre-Charge Sense Amplifier VDD CLK R OUT MP0 MP1 MN0 CLK R MP2 MP3 OUT MN1 Select Tree C B A C A B B C A B C Reference Tree EN EN D D D D Reference SHE-MTJ SHE-MTJ 0 SHE-MTJ 15 CLK W0 CLK W0 CLK W15 CLK W15 CLK Wref CLK Wref BL CLK R SL Write Circuit GND Fig.7. Circuit level design of proposed SHE-LUT. I I Read R MTJ I Read Sensing with PCSA requires two operating phases which could be performed in a single clock (CLK) period: pre-charge phase and discharge phase. During the pre-charge phase, CLK signal is equal to zero, therefore MP0 and MP3 transistors, shown in Fig. 7, are ON and the drains of the MN0 (OUT) and the MN1 (OUT ) transistors are charged to VDD. In the discharge phase, CLK is equal to VDD and all the PMOS transistors are OFF. Consequently, the voltage source (VDD) is disconnected from the circuit and the pre-charged nodes, i.e. OUT and OUT, begins to discharge. The discharge speed in each of the branches of the PCSA is different due to the difference between the resistances of the resistive storage elements, and the reference SHE-MTJ. For example, assume that SHE-MTJ0 with AP configuration is the storage element that is being sensed. Since it has higher resistance than the reference MTJ, the branch connected to it discharges slower than the reference SHE-MTJ branch, thus the voltage drops faster in OUT node. Since OUT is connected to the gate of the MP1 transistor, the voltage drop results in a voltage difference between source and gate of the MP1 transistors that is higher than threshold voltage. Consequently, MP1 will be ON and the OUT node which is connected to gate of the MP2 transistor will be charged to VDD. This causes the MP2 transistor to remain OFF, and as the result OUT node will be completely discharged to GND. In practice, an external synchronizer circuit can be utilized to ensure that the input signals are synchronous to the local clock signal of the SA. The synchronizer circuit for an n-input LUT includes n flip-flops that samples the inputs at each clock cycle. The pre-charge state of the SA should be sufficiently long to meet the required setup and hold times of the flip flops to avoid metastability. The probability of synchronization failure caused by staying of a flip-flop in the metastable state exponentially decreases with time. Detailed design and analysis of the synchronizer circuits are provided in [52]. B. Write Circuit I Write Fig. 8. SHE-MTJ read and write path equivalent resistances. In this paper, we have utilized a TG in the SHE-MTJ write circuit, as shown in Fig. 9(a). TGs are composed of one NMOS and one PMOS transistor, and characterized by their near optimal full-swing switching behavior. TG-based write circuit provides a symmetric switching behavior, i.e. the generated write current amplitude for P to AP switching equals the current amplitude produced for switching from AP to P state. Moreover, TGs are capable of producing a current amplitude larger than the switching critical currents of both 2-terminal MTJ and SHE-MTJ devices, which are listed in Table I. The produced current amplitude is sufficiently large to ensure the complete switching of the MTJ devices utilized in this paper. Figure 9(b) shows the TG-based write I Write R HM /2 R HM /2

9 Out2 Reference Tree Out1 Reference Tree 8 (a) CLK (b) BL SL CLK BL SL CLK CLK Fig. 9. (a) Proposed Transmission Gate-based Write Circuits. (b) TG-based write circuit layout view. (c) Three-dimensional (3D) cross-sectional schematic of SHE-MTJ integration at the back-end process of TG fabrication. circuit layout view. To address the feasibility of integrating SHE-MTJ with TGs, the three-dimensional (3D) cross-sectional view is provided in Fig. 9(c), which depicts the SHE-MTJ integration at the back-end process of CMOS fabrication. The required current for switching the SHE-MTJ passes through the heavy metal structure, which is built in the second metal layer. The MTJ stack is integrated between the second and forth metal layers, and occupies the space for the third via and metal layer as well as the fourth via [45]. Although, TG-based designs necessitate the availability of both CLK and inverse CLK signals, it is common and reasonable to assume access to both signal conditions within typical integrated circuits. C. Fracturable 6-input SHE-LUT design SHE-MTJ The proposed 4-input SHE-LUT circuit can be readily extended to LUT designs with greater number of inputs. Most contemporary FPGAs, especially XILINX products such as Virtex-5 [53] and Spartan-6 [54], utilize fracturable 6-input LUTs in their design. These LUTs have six independent inputs and two separated outputs. The fracturable 6-input LUT can implement any six-input Boolean functions, as well as two five-input Boolean functions with common inputs [55]. Herein, we have designed a fracturable 6-input LUT using SHE-MTJ devices, in which two PCSAs and two reference trees are utilized to ensure the independency of the outputs. Five NMOS transistors and two select signals, i.e. S5 and S6, are added to the LUT circuit to control the 5-input and 6-input operation modes of the SHE-based fracturable LUT. The structure of the proposed 6-input SHE-based structure LUT is shown in Fig. 10. It provides significantly higher functional flexibility at the expense of slightly more area and power consumption as studied in the next section. A. Simulation Results in Absence of Clocking Limitations VI. SIMULATION RESULTS AND COMPARISON p substrate N Well n+ diffusion p+ diffusion polysilicon contact via metal 1 metal 2 Cu Heavy Metal MTJ ferromagnetic layer MTJ oxide layer Figure 11 exhibits the functionality of the proposed SHE-LUT in the read phase for a 4-input NAND logic operation. The first set of inputs applied is ABCD= 1111, which selects SHE-MTJ15 with P configuration that denotes logic 0. While, the latter (c) OUT2 OUT1 PCSA2 VDD PCSA1 VDD CLK R CLK R CLK R CLK R OUT2 OUT1 S5 S5 S6 S5 S6 S5 EN EN Select Tree A A A EN EN B B B B C C C C D D D D E E E E Reference2 SHE-MTJ CLK W0 BL SL CLK W0 CLK W0 F SHE-MTJ 0 CLK W0 F CLK W63 SHE-MTJ 63 CLK W63 CLK WR CLK WR Reference1 SHE-MTJ Fig. 10. The structure of the 6-input SHE-based fracturable LUT. F F CLK R GND

10 9 V(v) 1.5 Pre-Charge State Discharge State Sense State input signal ABCD= 0000 output signal OUT= 1 Delay 72 ps input signal ABCD= 1111 output signal OUT= CLK frequency = 1 GHz t(ns) Fig. 11. Transient response for 4-input NAND operation for ABCD= 1111 (middle), and ABCD= 0000 (top). TABLE II: PERFORMANCE COMPARISON OF PROPOSED SHE-LUT VERSUS 2-TERMINAL MTJ-BASED LUT [16] FOR VARIOUS INPUT WIDTHS. Number of LUT inputs PDP = Power (µw) Delay (ps) LUT MTJ state = 0 LUT MTJ state = 1 PDP STT-based MTJ [16] SHE-based MTJ Improvement STT-based MTJ [16] SHE-based MTJ delay analysis for various input widths, as well as a comparison with a 2-terminal MTJ-based LUT previously proposed by the authors in [22]. Results show the SHE-LUT improvement in terms of power-delay product (PDP), ranging from 1.2% to 6.15%. Simulation results are obtained using SPICE circuit simulator in 90nm CMOS technology model developed by Arizona State University [56]. Herein, we have provided a comprehensive comparison between the read performances of our proposed 4-input SHE-LUT circuit, and previous performance-efficient 4-input MTJ-LUT designs introduced in [7, 9, 22]. Delay and power consumption for read operations are extracted for input values precipitating worst case condition for a NAND operation utilizing 1.2V nominal voltage (VDD) and 1GHz circuit clock (CLK) frequency. The obtained results are summarized in Table III. SHE-LUT provides high speed and low energy read operation with improved PDP values listed in the bottom row of Table III. Furthermore, a comparison between our proposed TG-based SHE-LUT and TG-based SRAM-LUTs [50, 57] is provided in Table IV. Simulation results are extracted for a NAND operation using 90nm CMOS technology and 1.2V nominal voltage. The obtained results show lower dynamic energy for SRAM-LUTs, however SRAM-based FPGA is challenged by the difficulty with power-gating LUTs which must retain the stored configuration. On the other hand, an MTJ-based LUT incurs zero standby energy, due to its non-volatility feature. The fabricated measurements indicates that typical value for power consumption can be reduced by 81% using MTJ-based LUT, in addition to a 56% reduction in area [21]. Based on the obtained results for SHE-LUT, further improvements can be anticipated. Finally, we have examined the reconfiguration operation of SHE-LUT and conventional 2-terminal MTJ-based LUTs, which involves write operation to switch the state of the MTJs. The STT and SHE switching behaviors are modeled using the relations provided in Section II.A and II.B, respectively. Table V provides a comparison between the reconfiguration operation of a 4-input SHE-LUT and a conventional MTJ-LUT. A 4-input MTJ-LUT includes sixteen MTJs having their magnetization directions aligned in a single reconfiguration operation. As listed in Table V, the proposed SHE-LUT provided at least 20% PDP improvement Delay 94 ps PDP Improvement = = % = = % = = % = = % = = % = = % = = % = = % = = % = = % (1) Simulation under CMOS 90nm Technology. (2) NMOS channel width = 90nm, PMOS channel width = 180nm TABLE III: PERFORMANCE COMPARISON FOR THE READ OPERATION OF 4-INPUT MTJ-LUTS. Zhao et Suzuki et Zand et SHE-MTJ Features al. [9] al. [11] al. [16] Based LUT NO. of MTJs NO. of MOSs Delay (ps) Active Power (µw) PDP (ps µw) PDP Improvement 67.8% 38.2% 6.15% (1) Simulation under CMOS 90nm Technology. (2) NMOS channel width = 90nm, PMOS channel width = 180nm

11 10 TABLE IV: PERFORMANCE COMPARISON BETWEEN SHE-LUT AND SRAM-LUT FOR FOUR-INPUT NAND OPERATION. Features TG-based SRAM-LUT TG-based SHE-LUT NO. of MTJs 0 17 NO. of MOSs Delay (ps) Static Power (µw) Active Power (µw) PDP (ps µw) TABLE V: PERFORMANCE COMPARISON FOR THE RECONFIGURATION OPERATION OF 4-INPUT MTJ-LUTS INVOLVING 16 MTJS. STT-MTJ SHE-MTJ Features Based LUT Based LUT Delay(ns) P to AP AP to P Power Consumption(mW) P to AP AP to P PDP (ns mw) P to AP AP to P Average PDP (ns mw) Average PDP Improvement 20.1% TABLE VI: SWITCHING CHARACTERISTICS OF A SINGLE MTJ CELL INCLUDING CLOCKING REQUIREMENTS. Features STT-MTJ SHE-MTJ Switching P to AP Delay (ns) AP to P Maximum CLK Frequency 140 MHz 250 MHz Switching P to AP Energy (fj) AP to P TABLE VII: RECONFIGURATION ENERGY OF 4-INPUT MTJ-LUTS INCLUDING CLOCKING REQUIREMENTS. Features STT-MTJ based LUT SHE-MTJ Based LUT Maximum Operating CLK Frequency 140 MHz 250 MHz Average Energy (pj) Energy Improvement 21.4% compared to 2-terminal MTJ LUTs. The clocking limitations in reconfigurable fabrics may change the results provided in Table V. Thus, in following sub-section we analyze the performance of proposed SHE-LUT in presence of clocking requirements. B. Simulations Results Including Clocking Requirements Table VI provides a comparison between the STT and SHE write schemes in terms of the switching delay and energy consumption for a single MTJ cell. Assuming the typical 50% duty cycle, the maximum operating clock frequency based on which each of the circuits can ensure complete switching of the MTJ states is listed in Table VI. We have examined the SHE-LUT reconfiguration energy according to the clocking requirements illustrated in Table VI. Obtained results listed in Table VII show that SHE-MTJ based LUT can operate at 78% higher clock frequency while realizing a 21.4% improvement in terms of reconfiguration energy, compared to 2-terminal MTJ-LUTs. Finally, to investigate the effect of MTJ scaling on the performance of the MTJ-based LUTs, a comprehensive comparison between a 4-input SHE-LUT and a 4-input STT-LUT is provided herein. Figure 12(a) shows the obtained results for the read operation of LUTs including the PDP values for sensing both P and AP states. The performance of the SHE-LUT and STT-LUT are comparable for the read operation, while there is a significant difference for the reconfiguration operation, as shown in Fig. 12(b). The obtained results exhibit the superiority of the SHE-LUT in terms of PDP for different MTJ dimensions. Moreover, LUTs with smaller MTJs have lower PDP values for both read and reconfiguration operations. During read operations, this is mainly achieved due to the increase in the resistance of MTJs by decreasing its dimensions, as elaborated by Equation (2). Since the supply voltage is fixed, higher resistance of MTJs results in lower read current, and consequently lower power consumption. For write operations, although a decrease in the produced write current leads to lower power consumption, it can also result in higher switching delay. This decrease in the switching speed is compensated by the significant decrease in the required switching critical currents, as shown in Equations (4), (5), and (11). Eventually, smaller MTJ dimensions results in higher switching speed, as well as lower switching power, as shown in Fig. 12(b). C. Fracturable 6-input SHE-LUT Simulation Results As mentioned in previous section, fracturable 6-input SHE-LUT circuit can operate in two different modes: 5-input and 6-input. In 5-input mode, the fracturable LUT can simultaneously implement two different five-input Boolean functions, as long as they

12 11 (a) (b) Fig. 12. The effect of MTJ scaling on SHE-LUT and STT-LUT performances. (a) Read operation, and (b) reconfiguration operation comprised of 16 write transactions to the corresponding bit-cells. V(v) Pre-Charge State Discharge State Sense State SHE-MTJ 63 input signal ABCDEF= X11111 OUT1= 1 Delay 90 ps SHE-MTJ 31 Delay 125 ps input signal ABCDEF= X11111 OUT2= CLK frequency = 1 GHz t(ns) Fig. 13. Transient response for fracturable 6-input SHE-LUT. 5-input NAND operation for ABCDEF= X11111 (middle), and 5-input AND operation for ABCDEF= X11111 (top). TABLE VIII: PERFORMANCE COMPARISON FOR THE READ OPERATION OF 6-INPUT FRACTURABLE SHE-LUT. 5-input 6-input Features Delay (ps) Active Power (µw) Regular Fracturable Regular Fracturable share common inputs. Figure 13 shows the functionality of the proposed 6-input SHE-LUT while operating in 5-input mode. The truth table of a 5-input NAND logic operation is stored in the least significant 32 bits of the LUT circuit, while the most significant 32-bits implement a 5-input AND Boolean function. The applied input is ABCDEF= X11111, which selects SHE-MTJ63 and SHE-MTJ31 with AP and P configurations, respectively. Table VIII lists the power consumption and delay of the 6-input fracturable LUT read operation for different operating modes under worst case conditions. The reconfiguration operation in a fracturable LUT is similar to that of the regular LUTs, as identified in this Section.

13 12 Reconfiguration Read Reconfiguration Read LUT output 0.4 I(mA) -0.4 Bit-Line (BL) signal Source-Line (SL) signal WRITE enable signal READ enable signal Write current Pre-charge I (P to AP) 149 µa I (AP to P) 154 µa CLK READ = CLK WRITE = 250 MHz Discharge t(ns) Pre-charge Discharge Fig. 14. SHE-MTJ based LUT functionality using a unique clock for both read and reconfiguration operations requiring 16ns termination time. OUT = 1 OUT= 0 Termination Time = 16ns TABLE IX: SHE-LUT OPERATING CLOCK FREQUENCIES BASED ON DIFFERENT DIMENSIONS FOR TRANSISTORS USED IN WRITE CIRCUIT. Features Width/90nm Ratio NMOS=1X NMOS =2X NMOS=4X PMOS=2X PMOS=4X PMOS=8X Current P to AP Amplitude (µa) AP to P Switching P to AP Delay (ns) AP to P Maximum CLK Frequency 250 MHz 450 MHz 750MHz Reconfiguration P to AP Power (µw) AP to P VII. ADVANCES IN CLOCKING SCHEMES FOR MTJ-BASED LUTS As illustrated in Section IV, clocking limitations may have a significant effect on the performance of an MTJ-LUT. The obtained results extracted in previous section are related to isolated read and reconfiguration operations. Since each of the LUT operations have different clocking limitations, more comprehensive clocking and signaling mechanisms are sought to control these operations in an MTJ-LUT. In this section, we have investigated two potential clocking schemes supporting both read and reconfiguration operations for SHE-LUT. First, we consider the use of a single clock signal for both read and write operations. Figure 14 shows the control signals, e.g. READ/Write enable signals, as well as the 250MHz clock signal which is utilized for both read and write operations. The clock frequency has been designed to ensure the complete switching of a single SHE-MTJ device. As it was illustrated in Table III and Table VI, the required time for switching the state of a SHE-MTJ cell is significantly greater than the time needed for read operation. Thus, if a single clock signal is utilized for both operations, its period must be long enough to ensure a complete reconfiguration operation. Although using a single clock reduces the complexity of the design, it incurs an excessive delay in read operation, which is the predominant operation by several orders of magnitude in reconfigurable fabrics. The clock frequency can be increased by amplifying the write current to reduce the MTJ switching delay. Enlarging the transistors widths in the write circuit increases the amplitude of the produced write current. Table IX lists the maximum possible operating clock frequencies for SHE-LUT, based on the different dimensions chosen for the transistors in the write circuit. As listed in Table IX, increasing the operating clock frequency is achieved at the expense of higher power consumption for reconfiguration operations. Figure 15 shows the second approach investigated herein for controlling the functionality of a SHE-LUT circuit, in which two distinct clock signals are utilized for read and write operations. The use of separate clock signal for read operations avoids the

14 13 Reconfiguration Read Reconfiguration Read LUT output OUT = 1 OUT= 0 I(mA) Write current I (P to AP) 149 µa I (AP to P) 154 µa Bit-Line (BL) signal Source-Line (SL) signal WRITE enable signal READ enable signal CLK READ = 1 GHz CLK WRITE = 250 MHz Termination Time = 10ns t(ns) Fig. 15. SHE-MTJ based LUT functionality using distinct clock signals for read and reconfiguration operations achieving 10ns termination time. excessive delay existed in the previous clocking method caused by being restricted to the write clock frequency. In this approach, the clock frequency for read operation is limited to the sensing delay of the read circuit. For instance, as listed in Table III, the sensing delay for a 4-input SHE-LUT is approximately equal to 100 picoseconds. Therefore, the clock frequency for read operation can be designed up to 5GHz assuming the 50% duty cycle. Figure 15 shows the control signals required for a 4-input SHE-LUT design, in which the clock frequencies for reconfiguration and read operations are equal to 250 MHz and 1GHz, respectively. This significant increase has been made possible by using a differentiated read clock rate that can substantially boost FPGA throughput, due to the prevalence of LUT read operations while performing logic functions. VIII. CONCLUSION In this paper, we have developed a novel energy-efficient non-volatile LUT using SHE-MTJ devices. The behavior of SHE- MTJ and STT-MTJ devices have been modeled in Verilog-A based on precise physical equations established in the literature using experimental parameters. The models were leveraged via SPICE circuit simulation tools to validate the functionality of the designed circuits. First, we compared the performance of our developed 4-input SHE-LUT with previous MTJ-based LUT designs. For read operations, our proposed design could achieve a significant improvement in terms of PDP, ranging from 6.15%, 38.2%, and 67.8%, compared to the recent works introduced in [16], [11], and [9], respectively. Next, the reconfiguration operation of the proposed SHE-LUT has been investigated in consideration of clocking requirements. The obtained results exhibited 21% and 67% reconfiguration energy improvement over LUT designs based on STT-MTJ. We have introduced and analyzed the design tradeoffs of two possible clocking schemes for controlling the read and reconfiguration operations in the proposed SHE-LUT, which can significantly increase the throughput of the non-volatile resistive LUTs in general. Finally, the design of the fracturable 6-input LUT demonstrates the flexibility and extensibility of SHE-MTJ based LUTs. REFERENCES [1] A. Alzahrani and R. F. DeMara, "Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics using Design Disjunction," IEEE Transactions on Computers, vol. PP, pp. 1-1, [2] R. A. Ashraf and R. F. DeMara, "Scalable FPGA refurbishment using netlist-driven evolutionary algorithms," Computers, IEEE Transactions on, vol. 62, pp , 2013.

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He also received his M.Sc. degree in Digital Electronics at Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran, in He is currently working toward the Ph.D. degree in Computer Engineering at the University of Central Florida, Orlando, USA. His research interests are in Reconfigurable and Adaptive Computing Architectures with emphasis on spintronic devices. Arman Roohi received B.Sc. degree in computer engineering in 2008 from Shiraz University, Shiraz, Iran. He also received his M.Sc. degree in computer architecture at Department of Computer Engineering, Science and Research Branch of IAU, Tehran, Iran, in He is currently working toward the Ph.D. degree in computer engineering at the University of Central Florida, Orlando, USA. His research interests include beyond CMOS computing with emphasis on Spintronics and QCA, and Reconfigurable Computer Architectures. Deliang Fan (M'15) received his B.S. degree in Electronic Information Engineering from Zhejiang University, China, in He received M.S. and Ph.D. degree in Electrical and Computer Engineering from Purdue University, West Lafayette, IN, USA, in 2012 and 2015, respectively. He joined the Department of Electrical and Computer Engineering at University of Central Florida, Orlando, FL, as an Assistant Professor in His primary research interest lies in Ultra-low Power Brain-inspired (Neuromorphic), Non-Boolean and Boolean Computing Using Emerging Nanoscale Devices like Spin-Transfer Torque Devices and Memristors. His other research interests include nano-scale physics based spintronic device modeling and simulation, low power digital and mixed-signal CMOS circuit design. Ronald F. DeMara received the Ph.D. degree in Computer Engineering from the University of Southern California in Since 1993, he has been a full-time faculty member at the University of Central Florida where he is Professor and Computer Engineering Program Coordinator. His research interests are in Computer Architecture with emphasis on Evolvable Hardware and emerging devices, on which he has published approximately 180 articles. He is a Senior Member of IEEE and has served on the Editorial Boards of IEEE Transactions on VLSI Systems, ACM Transactions on Embedded Systems, Journal of Circuits, Systems, and Computers, the journal Microprocessors and Microsystems, various conference program committees, and is currently an Associate Editor of IEEE Transactions on Computers. He received the Joseph M. Bidenbach Outstanding Engineering Educator Award in 2008, the highest educational honor from IEEE in the Southeast United States.