Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications

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1 Analyi and Deign of Monolithic, High PSR, Linear Regulator for SoC Alication Vihal Guta, Student Meber, IEEE, Gabriel A. Rincón-Mora, Senior Meber, IEEE, and Praun Raha 2, Meber, IEEE Eail: Georgia Tech Analog and Power IC Deign Lab, Georgia Intitute of Technology, 2 Texa Intruent Inc. ABSTRACT Linear regulator are critical analog block that hield a yte fro fluctuation in uly rail and the iortance of deterining their Power Suly Rejection (PSR) erforance i agnified in SoC yte, given their inherently noiy environent. In thi work, a ile, intuitive, voltage divider odel i introduced to analyze the PSR of linear regulator, fro which deign guideline for obtaining high PSR erforance are derived. The PSR of regulator that ue PMOS outut tage for low dro-out (LDO), crucial for odern lowvoltage yte, i enhanced by error alifier which reent a uly-correlated rile at the gate of the PMOS a device. On the other hand, alifier that ure the uly rile at their outut are otial for NMOS outut tage ince the ource i now free fro outut rile. A better PSR bandwidth, at the cot of dc PSR, can be obtained by interchanging the alifier in the two cae. It ha alo been roved that the dc PSR, it doinant frequency breakoint (where erforance tart to degrade), and three ubequent breakoint are deterined by the dc oen-loo gain, error alifier bandwidth, unity-gain frequency (UGF) of the yte, outut ole, and ESR zero, reectively. Thee reult were verified with SPICE iulation uing BSIM3 odel for the TSMC 0.35 µ CMOS roce fro MOSIS. I. INTRODUCTION The cloe roxiity of analog and digital circuit in SoC environent can caue the to be overwheled by uriou witching noie ignal roagated through uly line, interface node, and ubtrate injection [], [2]. In thee VLSI and ULSI circuit, voltage regulator for an indienable coonent of the ower anageent yte. They generate table voltage while ulying a wide range of current to a variety of circuit. They alo filter the fluctuation in the ower uly, thereby hielding their load circuit fro uly rile. Thu, in circuit like DRAM [3], PLL [4], [5], and EPROM [6], where ower uly noie directly tranlate to degradation in yte erforance, ower uly rejection i a key figure of erit for a voltage regulator. It i therefore ierative to analyze the PSR of linear regulator over a large frequency range with the ai of etablihing deign guideline and rincile for high PSR erforance. Further, a yte aggreively advance towa integration, thee tate-of-the-art regulator rely increaingly on on-chi caacitor (0-200 F) for frequency coenation [3]-[7]. Thee caacitor do not conue exenive board-ace and are not aociated with a ignificant equivalent erie reitance (ESR). Since the regulator do not ue an external caacitor to etablih the doinant low-frequency ole, they are tered internally coenated regulator. It ut be noted, however, that the effect of ESR till warrant dicuion, ince they becoe iortant when the connectivity to the late of the caacitor i liited by the dene routing requireent of the chi. II. PSR OF A TYPICAL LINEAR REGULATOR V ref G -A R o-a ERROR AMPLIFIER V out-a C o-a V dd PASS DEVICE Fig.. Block diagra of tyical linear regulator (a device ay be PMOS or NMOS). Fig. deict the block diagra of a tyical regulator coniting of an error alifier, a a device and an outut caacitor, [3]-[0]. The regulator ulie a variable current to the load circuit through the a device while aintaining a contant outut voltage due to a feedback loo fored by the otential divider created by reitor and (β /( )) and the alifier. The alifier i characterized by it tranconductance G -A, high outut reitance, R o-a (R o-a /G o-a ), and correonding ole, o-a (f -oa /2πR o-a C o-a ). The large erie a device (NMOS or PMOS) ha a tranconductance g and low drain-ource reitance r (r /g ). Bia reitor, and, that for the feedback network through a otential divider, are tyically very large ( >> r /I load λ) for low quiecent ower conution. Though thi odel i a very accurate rereentation of a linear regulator, it doe not offer an intuitive icture into the origin of the PSR frequency reone a eaure of the uly rile tranferred to the outut. A. Sile Model for PSR of Linear Regulator In it ilet for, the PSR tranfer function (a ratio of the outut to the uly rile) can be viewed a the effect of a voltage divider caued by an iedance between the uly and the regulator outut and an iedance between the outut and ground. An intuitive and inightful odel for analyzing the PSR of a tyical linear regulator i reented in Fig. 2. Thi odel conit of an iedance ladder coriing of the channel reitance of the a device (r ), and a arallel cobination of the oen-loo outut reitance to ground (z o ) and the hunting effect of the feedback loo (z o-reg ). Hence, referring to Fig. and Fig. 2, we can ee that ( zcout ) ( R ), () and, V out I load

2 reg. (2) Aolβ The odel i reented in Fig. 2. Thu, by ilifying the odel in Fig. to the one in Fig. 2, the PSR can be een to be v ) out ( reg PSR. (3) vdd ( reg) vout ( reg) PSR vdd ( reg) zcout R ( ) ( ) z o reg r Aolβ z o r z o-reg Effective when loo gain high (low to oderate frequencie) Effective when loo gain low (oderate to high frequencie) Fig. 2. Intuitive odel for PSR in action at variou frequencie. B. Model in Action over Wide Frequency Range Fig. 3 deict the ketch of a tyical PSR curve and how the intuitive odel allow u to deterine the PSR erforance of a linear regulator over a large range of frequencie, ily by accounting for the frequency deendence of z o and z o-reg. z o-reg r r r R o-reg PSR /v in [db] LOW z BW A PSR dc (A ol β) Frequency [Hz] MODERATE HIGH UGF 2 out If ESR negligible z 2 /2π r vout Fig. 3. Sile odel in action over wide frequency range. r ) DC and Low Frequencie At low frequencie, the high loo gain (A ol-dc β) allow z o-reg to hunt z o, and ince r i, for the ot art, ignificantly lower than, the following ilification can be derived: ( R R2) Ro reg. PSRdc Ro reg ( R R2) β Aol dc (4) Conequently, the PSR of the regulator i intiately related to the oen-loo gain of the yte. 2) Moderate Frequencie The hunting effect of the feedback loo, however, deteriorate at frequencie beyond the bandwidth of the alifier, BW A (or doinant ole, o-a ), thereby cauing an increae in the regulated outut iedance, z o-reg. Thi lea to a rie in the outut rile and, conequently, the doinant PSR breakoint in the for of a PSR zero (z ). The reultant degradation in the PSR can been obtained by relacing A ol-dc in (4) with the bandwidth-liited reone of the loo at frequencie where A ol-dc i greater than one i.e. between dc and the unity-gain frequency (UGF) of the yte. Thi lea to r vout f UGF reg reg (Aol β) r r Aol dc β r o A r o A BWA. (5) ( β ) ( Aol dc β) Aol dc ( A β) UGF ol dc o A The reence of a PSR ole ( ) at the unity-gain frequency, a redicted by (5), can be eaily undertood when we note that the deterioration of the PSR due to increaing cloed-loo outut reitance ceae at the UGF. At thi tage, the hunting effect of the feedback loo no longer exit and the PSR i deterined ily by the frequency-indeendent reitive divider between the channel reitance of the a device (r ) and bia reitor ( ). The PSR i given by R f UGF. (6) R At thee frequencie, the PSR of the yte i the weaket ince the cloed loo outut reitance i not decreaed by the feedback loo and the outut caacitor cannot hunt the outut rile to ground. 3) High Frequencie When the outut caacitor tart hunting ( ) to ground, a aller rile aear at the outut, thereby cauing an iroveent in the PSR (ince z o decreae with increaing frequency) and the econd PSR ole ( 2 ). Thu, zcout f > UGF. (7) zcout The effectivene of the outut caacitor i, however, retricted by it ESR. At very high frequencie, ince thi caacitor i an ac hort, z o i deterined by the ESR, which liit PSR to f >> UGF, (8) thereby leading to the foration of an effective PSR zero at z 2 /2π. Fig. 3 how a ketch of the ole and zero of a tyical PSR curve redicted by thi odel. Though the ile odel deicted in Fig. 2 rovide an intuitive undertanding of the relationhi between PSR and the oen-loo gain of the regulator, it doe not take into account the effect of the conduction of the uly rile through the alifier itelf. Thi rile feedthrough ha ignificant ilication for high PSR deign and i critical for deterining the otial alifier toology for a articular tye of outut tage. Before analyzing the PSR of the error alifier, let u dicu the echani of rile conduction through the outut tage, or erie a device of the regulator. Then, the deign of the alifier will be conidered. III. DESIGNING FOR HIGH PSR A. Serie Pa Device In alication where low dro-out i not a riary concern, the outut tage of the regulator i often an NMOS device. Deite the relatively large voltage headroo required to drive

3 the gate due to it gate-ource voltage dro, the NMOS device, acting a a ource follower, offer an inherently low outut iedance, aking the coenation of the regulator eaier than it low dro-out counterart [6], [7]. It i evident that in thi follower configuration, the NMOS device will conduct the rile reent at it gate directly to it outut, the ource. Hence, to kee the rile at the outut node low, it i crucial to deign the receding error alifier uch that the rile at the gate of the NMOS device i a all a oible. In ot low voltage alication today, however, a PFET tranitor i ued a the outut erie a device [8]-[0] becaue of the driving requireent of it gate. In thi configuration, the gain fro the ource of the device (connected to V dd ) to it drain, ha the ae agnitude a the gain fro it gate to it drain, i.e., g r. However, the two gain ath are out of hae. Hence, in order to cancel the feedthrough of the ower uly rile fro the ource, the receding alifier hould rovide a correlated rile at the gate of the PMOS device (V SG V S V G δ δ 0). In other wo, the uly rile hould aear a a coon-ode ignal at the gate and the ource. B. PSR of the Error Alifier Mot error alifier that have a ingle-ended outut ue a current-irror load to erfor double-to-ingle-ended converion and add the ac ignal obtained fro the inut differential air to a ingle-ended ignal. Thi irror ay be ileented in the for of PMOS device connected to the uly or NMOS device connected to ground []. Let u claify the forer PMOS-irror toologie a Tye-A toologie, and the latter a Tye-B. In the following analyi, it will becoe aarent that the ileentation of the currentirror i critical in deterining the PSR of the error alifier, and therefore the regulator. In thi analyi, and are the ac rile at the uly and the outut of the alifier, reectively. The internal caacitance of the alifier have been ignored for ilicity and ince they are negligible when coared to the high device caacitance of the large outut ower device. The analyi alo aue that tranconductance of all the device (g ) i uch greater than their channel conductance (g ), which i tyical in analog IC deign (channel length are larger than the iniu). ) Tye-A Toologie Conider a tyical exale of the Tye-A architecture, naely, the conventional error alifier a hown in Fig. 4(b), which conit of an NMOS inut differential air and a PMOS current-irror load connected to the uly. The all ignal PSR odel of thi circuit i reented in Fig. 4(a). The odel i obtained by grounding the two inut to the alifier and alying a all ignal ource at the inut uly ( ). and rereent the channel reitance of the PMOS and NMOS device, reectively. The current-deendent current ource (i R2 ), which reflect the current flowing through reitor into the outut, odel the effect of the current irror. Auing the /g reitance (of the diode-connected PMOS device) i uch aller when coared againt, which i tyically the cae, the uly rile i entirely reflected at the outut, vout A vdd i R ( ) vdd R vdd vdd. (9) A iilar reult i reorted in [2], where it wa found that, for thi alifier toology, the entire uly rile wa tranferred to the outut over a wide frequency range. /g ir2 V MP4 MP3 V- (a) MP MC (c) MP2 v y i R2 Fig. 4. (a) Sall ignal odel for PSR of Tye A error alifier, (b), (c), and (d) Exale of Tye A error alifier. Fig. 4(c) and 4(d) reent two other exale of Tye-A tructure of the folded tye with PMOS current-irror loa. Noting that the ignal at and v y are both coon-ode with reect to the differential air, they cancel out and the effect of the inut differential air i therefore nullified. Hence, the all ignal PSR odel of thee error alifier correon to the ae odel reented in Fig. 4(a), which wa analyzed earlier and decribed with (9). The device rereented by reitor and are deicted in dahed boxe in Fig. 4(b)- (d). Thu, fro Fig. 4 and (9), it can be etablihed that the uly rile aear at the outut unattenuated for Tye-A toologie. 2) Tye-B Toologie Fig. 5(b) illutrate a conventional error alifier coniting of a PMOS differential inut air and an NMOS current-irror load connected to ground. Thi i a tyical exale of a Tye-B toology. A in the odel for Tye-A toologie dicued earlier, the all ignal PSR odel of thi circuit can be contructed by grounding the inut, neglecting the (/g ) reitance of the diode-connected NMOS device (when coared againt the channel reitance of the PMOS device), and odeling the current-irror a a current-deendent current ource connected between the outut and ground. Thi odel i reented in Fig. 5(a). The derivation of the tranfer-function / reveal that no ac rile aear at the outut, theoretically iolating the outut fro the inut uly rile, MP MP2 MN MN2 V V- (b) V MN MN2 V- MP (d) MP2 MC vy

4 vout A vdd ir R ( ) vdd R vdd 0. (0) R V MP MP2 V- i R Vout-A /g i R MN MN2 (a) (b) fabrication. Towa thi ai, the value of the axiu allowable total caacitance of 50 F ha been choen. TABLE 2. CIRCUIT AND PROCESS PARAMETERS FOR A LOW DROP-OUT REGULATOR DESIGN. Circuit Paraeter Value Proce Paraeter Value VDD 3.3 V K 65 µa/v 2 V out.2 V K n 85 µa/v 2 dc -70 db V t 0.74 V MHz -20 db V tn 0.6 V I load 20A 300 V C ox 4 ff/µ 2 < 50 F λ n λ 0. V dd MC MN4 MN3 V V- v y MC V MP MP2 V- MN MN2 MP (0/) MP2 (0/) C (25F) V out-a MOUT (2500/0.35) MN (c) MN2 Fig. 5. (a) Sall ignal odel for PSR of Tye A error alifier, (b), (c), and (d) Exale of Tye A error alifier. Fig. 5(c) and 5(d) deict two other exale of the Tye-B toology of the folded tye uing NMOS current-irror loa. A in Tye-A toologie, on oberving that the ignal at and v y are coon ode with reect to the inut differential air, it can be een that their all ignal PSR odel correon to the odel reented in Fig. 5(a). Hence, fro Fig. 5 and (0), it i evident that Tye-B toologie hield their reective outut fro rile in the uly. C. General Deign Guideline for High PSR Mot LDO toologie ue a PMOS a device at the outut becaue it exhibit a low forward dro (and conequently a low ower lo acro the device). Tye-A error alifier, a it turn out, conduct nearly the entire rile at the uly to their outut. Having the rile at the gate and ource equal in agnitude and hae ake the uly rile coon-ode, thereby canceling any feedthrough. Tye-B alifier in ource follower tye ower device hield the gate and therefore the ource and outut fro any uly rile. IV. RESULTS FROM SAMPLE DESIGN The deign rincile fro Section II and III were ued to deign a onolithic low dro-out regulator having the ecification reented in Table 2. The roce technology i 0.35µ TSMC CMOS. The outut voltage of.2v i tyical of any low-voltage alication. Many of thee alication, like EPROM and DRAM, do not require large current and hence a tyical value for the axiu outut current of 20A ha been choen. Since a coletely integrated deign i required, the value of the required caacitance hould lend itelf eaily to (d) (g G o A) C gd G o A g PSR () 2 C gd (G o A ( C gd) (g g G A) C gd) G A g G o A g 200uA (0/) MN (0/) MN2 (0/) M (0/) V ref (.2V) R (30K) V out (.2V) (00F) Fig. 6. Scheatic of LDO uing PMOS outut device and conventional OTA. The low dro-out voltage ecification neceitated the ue of a PMOS outut tage, and hence a Tye-A alifier. For the ake of ilicity, the conventional alifier of Fig. 4(b) wa choen. The cheatic of the LDO deign i reented in Fig. 6. The all ignal equivalent of the circuit wa then analyzed for PSR, in a anner iilar to []. Only the large device caacitance of the outut device were conidered in the analyi. If A dc-a and G o-a are the dc gain and outut conductance of the alifier, reectively, and C gd i the total gate-drain caacitance, including coenating Miller caacitor C, the PSR tranfer function i given by (). The dc gain, zero, and ole of thi tranfer function are Go A g g PSR dc, (2) G A Adc A Adc A Aol dc Go A g z o A BWA, (3) Cgd Ro A( Cgd) G A Go Ag G A UGF, (4) Go A(Cout Cgd) (g G A)Cgd C gd and Go A (Cout Cgd) (g G A)Cgd 2, (5) out Cout Cgd Cout The aution ade in the analyi above are that g i uch

5 greater than g for all device, g i uch greater than G o-a, and g C gd i uch greater than g C g, G o-a (due the large ize of he erie a device). Thee aution are reaonable for a tyical low-ower regulator uing a large erie a device and large coenating caacitor relative to device caacitance. PSR [db] E0 E03 E05 E07 E frequency [Hz] Aol [db] PSR (Si) PSR (A nal.) PSR (Si. 0F) frequency [Hz] E0 E02 E03 E04 E05 E06 E07 E08 E09-20 Fig. 7. PSR erforance coarion of iulated and analytical reult for PSR for regulator uing PMOS a device (inet how oen loo gain). Fig. 7 illutrate both the iulated and the analytical PSR, along with the iulated oen-loo gain of the regulator. The SPICE iulation, which ued BSIM3 odel, how a trong correlation between the oen-loo gain and the PSR of the regulator and agree very well with the analytical reult, which were obtained through MATLAB. Fig. 7 alo how the iulated PSR in the abence of the degradation in the PSR at high frequencie can eaily be noted through the abence of the econd PSR ole, 2, the outut ole. TABLE 3. ANALYTICAL EXPRESSIONS FOR POLES AND ZEROS OF THE PSR OF TYPICAL REGULATOR TOPOLOGIES IN TERMS OF THEIR OPEN LOOP CHARACTERISTICS (P UGF AND P 2 P OUT FOR ALL TOPOLOGIES) Pa Device PMOS NMOS Error alifier Tye-A Tye-B Tye-A Tye-B dc z High dc PSR G A Ro A g o-a High PSR BW G A Ro A o A G A Ro A o A G A Ro A o-a Table 3 coare the reult of the analyi erfored in the reviou ection to the reult of a iilar analyi erfored for regulator coniting of a PMOS outut tage with a Tye B Error alifier and an NMOS outut tage with Tye A and Tye B alifier. It i evident that Tye-A (Tye-B) alifier rovide uch higher dc PSRR than their Tye-B (Tye-A) counterart for PMOS (NMOS) device. Another way to view thi reult i a follow: the Tye-A alifier can eet the dc PSRR ecification of an LDO regulator with a lower gain than a Tye-B toology. Thi would ake the Tye- A alifier a referred choice in any CMOS alication, where low voltage headroo ake the deign of high-gain alifier a challenge [8]-[0]. It ut be noted, however, that in alication where a high PSRR bandwidth i required at the exene of dc PSRR, the Tye-B alifier i a ore uitable choice ince it doinant PSRR breakoint (zero) lie at a higher frequency (z o-a g r ) than for the conventional error alifier cae (z o-a ). V. CONCLUSIONS A ile, intuitive voltage divider odel for the PSR of a tyical linear regulator i ued to accurately decribe the PSR erforance of linear regulator. The PSR at low frequencie, the doinant PSR breakoint where erforance tart to degrade, and three ubequent breakoint are deterined by the dc oen-loo gain, the error alifier bandwidth, the unitygain frequency, the outut ole of the regulator, and the ESR zero, reectively. A cloer exaination of the PSR of a regulator reveal that alifier that eloy irror connected to uly to roduce a uly-correlated rile at the gate of the PMOS outut device (thereby aking the rile coonode) are bet uited for LDO alication with high PSR erforance, while alifier that ue irror connected to ground to attenuate the uly rile at their outut are otial for driving an NMOS outut tage (ince the gate, and hence, ource, i now free fro outut rile). A better PSR bandwidth, at the cot of dc PSR, can be obtained by interchanging the alifier in the two cae. A trong relationhi between the PSR and oen-loo gain of a linear regulator ha been etablihed fro which deign rincile critical to obtaining high PSR erforance have been rooed. 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