Categories and Subject Descriptors [Data Converter]: Delta-sigma, RSD-cyclic, algorithmic architecture. General Terms Algorithms, Design, Verification

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1 Hybrid RSD-yclic-Sigma-Delta Analog-to-Digital onverter Architecture Youef H. Atri Motorola Inc 1645 W Baele Rd #134 Mea Az r43451@motorola.com Larry D. Paarmann Deartment of Electrical and omuter Engeerg Wichita State Univerity aarmann@ece.wichita.edu ABSTART In thi aer the deign of a hybrid RSD-cyclic and igma-delta analog-to-digital converter architecture will be troduced. Firt the advantage of ug uch a toology a comared to either RSD-cyclic or igma-delta toology alone will be furnihed. Then a to-down deign aroach will be dicued and the requirement on the ecific analog block uch a oerational amlifier mimum caacitor ize etc (Given certa erformance requirement) will be derived. Matlab model baed on the given toology will be develoed and imulation will be dicued. A comlete deign examle will be dicued ug thi to-down aroach cludg the circuit imlementation. The difficultie tryg to imlement the given deign examle ug either and RSD-cyclic or igma-delta aroach will be highlighted. ategorie and Subject Decritor [Data onverter]: Delta-igma RSD-cyclic algorithmic architecture General Term Algorithm Deign erification Keyword Over-amlg RSD-cyclic algorithm analog-to-digital converion 1. INTRODUTION In thi ection the benefit of ug a hybrid architecture will be dicued more eed and higher accuracy for a lower overamlg ratio. Plu the toology itelf will be troduced. Given a et of requirement on an analog-to-digital converter thee requirement can be tranlated to et of requirement on the analog comonent after an aroriate architecture ha been choen. A there can be a variety of requirement on an analog-todigital converter deendg on the alication it i gog to be ued for we will focu on two major requirement eed and reolution. RSD_yclic A/D erformance For an RSD cyclic analog-to-digital converter architecture hown figure 1 [1] ug one tage would require n-cycle to get an accuracy of n-bit reolution. For each additional bit an additional cycle i required. However a higher accuracy will ut additional contrat on comonent mimatch for the actual imlementation a will be derived the next ection. For examle the jum from 10-bit reolution to a 1-bit reolution require an creae the mimum caacitor ize ued for the amlg circuit. Increag the caacitor ize might not be an otion an alication where die area i an exenive real etate. Another imlication of creag the reolution for thi architecture i the creae on the oerational amlifier ga and the bandwidth requirement of the oerational amlifier. An creae the reolution mean a lower converion time if the ame clock frequency i ued. If the clock frequency i creaed we would get even tougher requirement on the oerational amlifier deign a well. Sigma-delta A/D erformance For nd -ordera igma-delta architecture a hown figure which will be ued for the uroe of our dicuion here without any lo of generality ce any other igma-delta toology could have been ued tead the bit reolution i directly aociated to the over-amlg ratio ued [3 4]. Technique for ug multi-bit quantization tead of ug one bit quantization will decreae the over-amlg ratio. However general creaed reolution i obtaed at the cot of higher amlg frequencie. Thi ut a limit on the maximum ignal bandwidth that can be converted. Hybrid RSD-cyclic-igma-delta A/D erformance The new rooed hybrid RSD-cyclic-igma-delta architecture hown figure 3 i a combation of the two dicued architecture RSD and igma-delta which will be referred to from thi ot on a hybrid architecture. The reolution obtaed with thi architecture i n MSB RSD + LSBSDL where n 1 MSBRSD tand for the mot ignificant bit obtaed from the RSD_cyclic art of the toology and n LSB SDL tand for the leat ignificant bit obtaed from the igma-delta block of the toology. The maximal bandwidth of the ignal that can be converted i determed by the igma-delta block. Sce the igma-delta art i required to achieve only a reolution of LSBSDL the over-amlg ratio would not be a high a if the reolution i given by n MSB RSD + LSBSDL. Which mean we have achieved a higher reolution with a maller over- amlg ratio. Alo the requirement on the RSD-cyclic block are only the requirement

2 Recycled Signal Reidue oltage Feedback amle witch Inut ignal Samle witch Add offet baed on Deciion omarator P ontrol Signal omarator Q Digital code Figure 1: RSD-yclic A/D baic oeration Inut Signal Figure : Simlified block diagram of the econd order igmadelta modulator MSB to achieve RSD -bit reolution. Which mean that the requirement on the on the analog buildg block for the RSDcyclic art are much more relaxed cludg the mimum caacitor ize requirement and the oerational amlifier ga and unity-ga frequency. The converion time required i till MSBRSD -clock cycle. However thi number doe not go to the fal time required ce it i done while the igma-delta block i dog it art of the converion. The followg numeric examle will hed ome light on thee ot. Aume we would like to deign a 1-bit analog-to-digital converter that can convert Eq ignal of 500 khz bandwidth ug the hybrid architecture. We can chooe our deign uch that the RSD-cyclic art of the hybrid toology i ued to obta the firt 6-bit and the igma-delta art i ued to obta the other 6-bit. The requirement on both block would be a if we were dog each block for only the required number of bit 6-bit for the RSD and 6-bit for the igma-delta. The over-amlg requirement of the igma-delta block are much lower for a 6-bit reolution than thoe for a 1-bit reolution which mean we can do converion for ignal with a much higher bandwidth than thoe for the ame over-amlg ratio. So ummary we have ubdivided the n-bit reolution deign for a given bandwidth ignal to a n1-bit deign of the RSD-cyclic A/D and n-bit reolution deign of the igma-delta A/D for the ame ignal bandwidth requirement where nn1+n. The oeration of the hybrid architecture a can be een from figure 3 i a follow: Firt the RSD-tage will take a amle and tart an n1-bit converion. After n1-cycle the firt n1 MSB are obtaed then a digital to analog converion i erformed for thee MSB. The obtaed outut i ubtracted from the origally amled ut and thi i fed to the n-reolution caable igmadelta block where the converion i gog to be erformed on thi difference. Before that a 10 time multilication will be erformed on the difference. The range for the RSD-cyclic i the ame a the full range for the hybrid A/D denoted here by FS. The range for the igma-delta converter i given by SDL FS 10 1 n FS. So the igma-delta block i dog an n-bit converion on thi reduced range. After the converion i comleted the bit are gathered together the digital correction

3 M-MSB bit Reduced Full Range (n-m)lsb bit N-bit ode Digital ontrol Signal Figure 3: Simlified Hybrid RSD-yclic-Sigma-Delta A/D Toology b RSD_ yclic( { beg reidue ( 1) ; For( i 1 n 1 i + + ) { ref If reidue( then 4 P com 1 Qcom 0; b ( 1; reidue( i + 1) reidue( ref ; ref eleif reidue( then 4 P com 0 Qcom 1; b( 0; b(1: b(1: 1; reidue( i + 1) reidue( + ref ; ele P 0 Q 0; com return ( b); end } com ref b ( 0; ( i + 1) ( ; reidue n) reidue Figure 4: RSD-yclic A/D algorithm block to obta the n-bit reolution of the analog ut. When deigng the reference for the igma-delta the ame block that roduce the 10-ga hould be ued. Thi aroach guarantee that the error obtaed from the 10-ga will have the ame effect on the reference. Alo care hould be taken the deign of the reference for the igma-delta which hould be derived from the reference for the RSD-cyclic block and the deign of the ga-10 block. Another imortant ot i uttg together all the bit obtaed from the RSD-cyclic block and the igma-delta block where care hould be taken about the timg of uch event after all the filterg ha been done. Here we will not go to the detail of thi oeration a thi i the toic of another aer and the ma ot here i to troduce thi new toology.. DERIATION OF ANALOG BLOK REQUIREMENTS AND MODELS Aumg an imlementation for the RSD-cyclic block and for the igma-delta tegrator block a hown figure 5 and 6 reectively we will derive the requirement on the comonent that make u thee block to meet the deired eed and reolution ecification. RSD-yclic Requirement The RSD-cyclic algorithm i ummarized figure 4. The baic te of thi algorithm can be ummarized a follow:

4 Figure 5: Simlified oible RSD-yclic imlementation Given an ut range for the analog ut and a requirement of n- bit reciion of the bary code we tart with. If where 0 ref th and ref ref then the [ ] and the reult of the reidue voltage i re ref comarion i a 1. If th then re + ref and the reult of the comarion i 1. Otherwie re and the reult of the comarion i 0. The ame rocedure i reeated n-time each time the next i the reidue value from the reviou te. After n-te a code of 1-1 and 0 i obtaed which till need to be tranlated to a bary code. Lookg at the oible circuit imlementation for the RSD block hown figure 5 we can ee non-ideal behavior of the circuit comonent will troduce ome error ource. Source of thi non-ideal behavior are among other - Fite oerational amlifier ga - aacitor mimatch - Fite ettlg time - Oerational amlifier lewg If we clude all thee non-idealitie the derivation of the reidue voltage tranfer curve for the RSD th toology which i obtaed by tatg the charge conervation law at the virtual ground node of the oerational amlifier we get out where 1+ e t τ 1 AF DA ref ; if ( P 1 Q 0); + ref ; if ( P 0 Q 1); 0; if ( P 0 Q 0); DA 1 F + F S 1+ F S F i the caacitor ued A i the amlifier ga and τ i the ettlg time. From the above equation and followg tediou algebraic maniulation we can obta the followg firt order aroximation formula for the deign arameter of the circuit: Oerational Amlifier mimum n n+ 1 Ga: Am α α

5 Figure 6: Simlified Integrator chematic that can be ued igma-delta imlementation Oerational Amlifier Ga- * f Bandwidth: GBW ( ln( ) + ( n 1) ln ) Slew Rate: F FullScale SR 1 σ T Mimum aacitor Size: aacitor Mimatch Error: m γ < n kt ( ) n where α σ and γ are arameter between 0.1 and 0.4 f i the amlg (or clock) frequency and i the eak-to-eak ignal. Thee deign arameter can be ued to imlement the n1- bit RSD-cyclic block of the hybrid architecture. Of coure ome additional marg hould be added on thee arameter to allow for error marg comg from other unaccounted for ource. Now for the igma-delta block we can bae our calculation on the tegrator block circuit imlementation a hown figure 6 which make u the mot imortant art of the modulator. Firt of all we have to fd out the mimum over-amlg ratio required baed on the required reolution that can be achieved by a nd - order igma-delta modulator. The over-amlg ratio OSR i defed a follow: f OSR f B where f i the amlg frequency ued and f B i the maximum ignal bandwidth. Doublg the amlg frequency for a nd -order igma-delta architecture with 1-bit quantization creae the reolution caability of thi converter by.5 bit [34]. However alo non-ideal behavior of the circuit comonent hould be accounted for when derivg the equation for the deign arameter. A for the RSD-cyclic imlementation contributor to thi non-ideal behavior are: fite oerational amlifier ga aacitor mimatch fite ettlg time oerational amlifier lewg. Similar equation a for the RSD-cyclic circuit can be derived [3.4]. However for the uroe of our dicuion here we would like to determe the over-amlg ratio for the hybrid architecture to achieve the required bit reolution and the cae of thi architecture it i lower than the one required for the igma0-delta block only. Now we can combe the requirement for the two block: n1-bit reolution for the RSD-cyclic block and n-bit reolution for the igma-delta block where nn1+n to get the the requirement for the hybrid architecture n-bit reolution. Matlab model ha been ued that are rereented by the imlified chematic figure 3 to verify thi new architecture. Matlab code and imulk model have been develoed a well to calculate the different deign arameter. 3. POSSIBLE IRUIT IMPLEMENTATION A imlified verion of a oible circuit imlementation of the hybrid architecture i hown figure 7. Of coure a realitic imlementation would have to be a differential ended circuit for all the different block. However thi i a imlified chematic that how the baic idea. What i added to thi architecture i the n1-bit digital-to-analog block. Alo the difference amlifier a well a multily by 10 which erve to boot the difference between the amled analog ut ignal and converted n1-bit analog ignal. The deign requirement on thee block to achieve the required accuracy are a follow: Thee block erve a the connectg block between the RSDcyclic and igma-delta block. So the drawback of thi architecture i the added comlexity that the imlementation require. However it i the author believe that the advantage are much more ignificant if the alication require the converion high accuracy at moderate eed. The over-amlg ratio for the deign of the igma-delta block i reduced ignificantly thi aroach. The higher the number of bit obtaed the RSD-cyclic block the lower i the over-amlg ratio required. 4. DESIGN EXAMPLE USING NEW ARHITETURE A numeric deign examle will be ued here to how how thi new architecture can be ued to get the deign requirement for the block at hand a uggeted by figure 7. Aume an alication require the deign of a 14-bit analog-todigital converter that i caable of convertg ignal u to eed of 500kHz bandwidth. We can deign thi converter by ug the hybrid architecture a follow: Deign the RSD-block to get the 6 mot ignificant bit. So n16. Thi mean that the nd -order igma-delta ha to be able of at leat 8 bit reolution for the ame bandwidth ignal. To leave ome room for error marg we can chooe the igma-delta block to give 9 bit of reolution. We need to calculate the requirement on the deign arameter to achieve thi reolution for a 500kHz ignal a ecified above. Firt we have to not that we will ue

6 6. OMPARISON: NEW DESIGN AND ND ORDER SIGMA-DELTA ARHITETURE We have calculated the over-amlg ratio for the nd -order igma-delta block for the hybrid architecture the deign examle of ection 4 to be 16. If we ued a nd -order igma-delta block only to realize an analog-to digital converter we would need an over-amlg ratio of at leat 64 [34] which verifie the advantage of ug the hybrid architecture. Figure 7: Simlified oible hybrid architecture Imlementation our calculation for the RSD-cyclic block requirement the ame amlg frequency a determed by the igma-delta block even though thi i not required. The requirement can be calculated to fd that we need: GBW 180 Am 66dB MHz SR 60 m ff and 1.5% µ f i 8MHz and 1 we aumed and added alo ome error marg on thee calculation. To achieve 9 bit reolution on the nd -order igma-delta converter we need to ue an over-amlg ratio OSR of at leat 16 which i 8MHz for a 500kHz bandwidth ignal. 7. ONLUSIONS In ummary we have troduced a new hybrid architecture that ue the RSD-cyclic and igma-delta architecture. The deign requirement to meet a ecified erformance have been derived. It ha been hown that thi new toology ha the otential to reduce the over-amlg ratio and relax the RSD-cyclic block requirement and till obta a high reolution for an creaed ignal bandwidth. Future work hould attemt refg the digitalto-analog block deign a well a tryg to dicu the different oible imlementation of the digital control correction and DSP block the igma-delta block. Alo of great value would be the tability analyi of thi deign and thorough dicuion of the different oible igma-delta toologie that can be ued thi new architecture. 8. REFERENES [1] B. Genetti P. Jeer and A andemeulebroecke A MOS 13 bit yclic RSD A/D onverter IEEE J. Solid-State ircuit ol. 7 NO. 7 July [] D. Garrity P. Raker A 10 bit 0M/ Pieled A/D onverter Motorola LATG SST 1994 [3] J. andy G. Teme Overamlg delta-igma data converter theory deign and imulation 199 IEEE Pre Picataway N.J. [4] Steve R. Norworthy R. Schreier G. Teme Deltaigma data converter theory deign and imulation 1997 IEEE Pre Picataway N.J. 5. OMPARISON: NEW DESIGN AND RSD ARHITETURE Here baed on the deign examle of the reviou ection we will comare analog block requirement of an RSD-cyclic architecture only a comared to the new hybrid architecture. We can do the ame calculation a the reviou examle and ue the ame aumtion to get: Am 11dB GBW 66MHz SR 60 m 0. F and 0.01%. µ By comarg both et of arameter we can verify that the requirement on the hybrid architecture are more relaxed and can be eaier achieved.