Switched-Capacitor Charging System for an Implantable Neurological Stimulator. Draft 2. Group 2: Orlando Lazaro Diego Serrano Jose Vidal ECE 6414

Transcription

1 Switched-Capacitor Charging System for an Implantable Neurological Stimulator Draft 2 Group 2: Orlando Lazaro Diego Serrano Jose Vidal ECE 6414 March 2, 2009

2 I. INTRODUCTION Integrated medical stimulators have been around for almost six decades, beginning with the development of the cardiac pacemaker and gaining momentum with the miniaturization of integrated circuit technologies. Year by year, researchers strive to make such devices smaller, more accurate, and more capable while consuming less power. Hence, wireless power and efficient stimulation techniques have been popular topics of research. The goal of this design is to focus on the latter. Typically, neural stimulation is accomplished via voltage controlled stimulation (VCS) or current controlled stimulation (CCS). While VCS has proved to be very efficient, complex safety measures must be implemented to avoid tissue damage. Conversely, CCS is much safer, but boasts a much lower efficiency. However, work has been done on the development of a third technique, named switched-capacitor stimulation (SCS), which uses a capacitor bank to store charge and stimulate tissue [1,2]. By utilizing efficient capacitor charging techniques [3], an SCS device could provide high power efficiency with minimal safety overhead. Below, Figure 1 exhibits a block diagram of our design. Note that the elements outside of the box are inputs and outputs of the system. Figure 1. Switched-capacitor stimulator system diagram. II. SYSTEM ARCHITECTURE Start-Up Rectifier: In order to enable true autonomy, the SCS system must be able to generate its own supply voltages. To that end, a start-up rectifier must be designed to charge two supply capacitors passively. Once the voltages reach a modest level, the entire system will come online and will maintain the supply caps more efficiently. Since the supply capacitors will experience a constant drain, the system will periodically switch from charging stimulator capacitors to charging the supply capacitors. The topology for the start-up rectifier has been implemented in [4,5] for use on an active rectifier and is shown in Figure 2.

3 Figure 2. Passive rectifier for supply generation during start-up. AC-DC Converter and Driving Circuitry: These functional blocks are responsible for efficiently converting the AC input signal, which comes from the inductive link, into a DC voltage to be stored in the stimulation capacitors. A half-diagram of the topology during positive input voltage phase is shown in Figure 3. In its basic form, the AC-DC acts as an active rectifier with switching capacitive loads. The driving circuitry currently consists of a comparator, whose inputs are the drain and source nodes of the switch, M PASS, and output is the gate of M PASS. MPASS Figure 3. Implementation of active rectification circuitry (positive phase). A comparator is being used to sense a positive voltage across M PASS. This type of switching is known as zero-voltage switching (ZVS). When the comparator trips, the gate of pass transistor is driven low forcing M PASS into its triode region and allowing current to flow into the capacitor. Because the input v LC has a frequency on the order of 1 MHz a high-speed comparator is required. Ideally minimizing the delay required to open M PASS will reduce reverse discharge of the capacitors to the low impedance source. The comparator is required to have an ICMR of {V THP,V CAP } in order to drive M PASS. The ICMR is accommodated for using a folded-cascode input as shown in Figure 4. The current driven into the latch uses positive feedback to trip the output high or low. The use of the complimentary differential amplifier allows for large switching currents, compared to its quiescent current, to be used to drive the output stage as well as minimize power consumption. The differential amplifier then feeds the latched decision to a push-pull inverter to drive the load. A similar approach was taken in [6]

4 Figure 4. High-speed comparator with wide ICMR using a pre-amp, latch, diff amp, and inverter to drive rectifying pass transistor. Two other techniques are being considered for use in this topology. The first is the use of a current sensor to decide when to switch the gates, known as zero-current switching. The benefits of ZVS over ZCS are not obvious, but will be determined as the design proceeds. The second technique is given in [7] and suggests using an op-amp to drive your switches. The author claims that if the current flowing through the switch is small, the gain of the op-amp is large, and the output does not saturate, the op-amp will maintain the V DS of your switch at the offset voltage of the amplifier. This may be an excellent option, but it is not sure that the SCS system can meet these criteria. Accuracy of the driving circuitry will greatly determine charging efficiency. In terms of performance, this block must be able to operate near 13.56MHz, be able to charge two complementary capacitors with 1.8uC in less than 1.25ms, and boast an efficiency of at least 60% [8]. Digital to Analog Converter (DAC): An extensive literature survey was performed to find the appropriate topology for a digital to analog converter (DAC) that fits the SCS specifications. The first step in finding the right architecture for this block was to define its main performance parameters. Various factors limit the efficiency of a data converter, including speed, resolution, and linearity among others [9]. Since the amount of charge to be delivered to the tissue limits both the frequency and pulse width to the kilohertz range, speed is not a key factor for this application. Likewise, linearity plays a limited role since the output of the DAC is programmed and stays fixed for a period of time. Resolution, power consumption, and area are crucial to the design of the SCS DAC. Power consumption and area are obvious constraints given that this system is targeted for implantable devices. Higher resolution gives a finer step size in charging the capacitors. However, non-idealities in the AC-DC circuitry limit the minimum detectable voltage change. If, for example, the maximum voltage desired on the capacitors is 1.8V, an 8-bit DAC could provide 7mV resolution. This would mean that the AC-DC should be able to filter AC ripple to less than 7mV, an unnecessary task. Therefore, what is needed for the SCS DAC is an adequate number of steps to effectively compensate for charge imbalance. To that end, a Binary Weighted Current (BWC) DAC and a Charge Scaling (CS) DAC seem like good topologies. Figures 5 and 6 show the BWC and CS DAC, respectively. The BWC DAC consists of current sources configured using only N switches and N sources. It has small area consumption and can be modified to have high power efficiency by shutting off current sources when not in use [10, 11]. The CS DAC uses the exact same configuration as the BWC DAC, using capacitors instead of current sources. Since no static current flows through the circuit, it is ideal for low-power applications. The two main drawbacks of using this design are the possible large area consumption (which is definitively not as large as for resistive DACs) and the offset and non-linearities introduced by mismatches in the capacitors. Proper layout takes care of these two problems [12, 13]. Between the two of them, the Binary-Weighted DAC seems to be a better option since it requires less space, and a simple modification of the original topology could allow high power efficiency.

5 Figure 5. Binary weighted current DAC. Figure 6. Charge scaling DAC Comparator and Monostable: The voltage comparator is a part of the discharge control loop of the capacitors. Its job is to compare the voltage of each one of the stimulation capacitors with the reference voltage and trigger a signal whenever these two voltages are equal. This process allows the digital controller to know when to switch and charge an empty capacitor. Since there are only two capacitors on each branch in the prototype, it was decided to simply use this signal as the selection signal for the multiplexer and demultiplexer. This reduces the number of pins needed for the test chip. If this system were to be expanded, the digital controller would have to determine the selection signals of the muxes and demuxes. The monostable would allow the control signal to stay active for a certain period of time to ensure it is latched by the digital control. As a safety measure, a watchdog timer is included to trigger the monostable in case the capacitor s voltage never reaches V REF. There are no critical performance criteria for these blocks. Multiplexers: A series of multiplexers will serve as bridges between the capacitor bank and, either, the output of the AC-DC converter or the stimulation electrodes. Ideally, switch resistances should be as low as possible to reduce power loss, but this will be a trade-off with area. Transmission gates are most often used for multiplexers, but it may be reasonable to utilize pass transistors if the voltage variations are not large. Notice the muxes to Site A and Site B have an enable signal. This has been implemented in order to provide more control over when the stimulation capacitor is connected to the electrode. Without this enable signal, a capacitor would always be connected to the electrode. Charge Balance Circuit: In stimulation circuitry, charge imbalance is a serious problem. Given the biphasic nature of this stimulator, the system has a propensity to dump unequal amounts of opposite charge onto the stimulation site. If this is allowed to continue, the polarity of the tissue will become much larger than desired and electrolysis of the tissue can occur. Therefore, it is essential to ensure that the SCS system maintains zero net charge at the stimulation site. The charge balance system begins at the switch between the mux and demux to each site. The system is designed to alternate. During a positive stimulation, the Site A switch connects to the capacitor while the Site B switch connects to a voltage-controlled resistor. This resistor generates a voltage proportional to the return current from the stimulation site. An integrator will integrate the generated voltage. During negative stimulation, the switches connect to the other terminal and the process is repeated. At this point, a sample and hold circuit will sample the net voltage. It is here that the voltage travels off-chip into an ADC and digital controller. Depending on

6 the polarity and magnitude of the output, the digital controller will adjust the input DAC commands to compensate V REF. The accuracy of the integrator and sample and hold will determine the effectiveness of the charge balance system; therefore, it must be very accurate and robust. Also, this feedback loop ought be faster than the capacitor charging in order to effectively compensate the imbalance. Therefore, the speed of these blocks should be greater than 5kHz for the largest allowable charging time. A standard topology will most likely be chosen for the integrator, but that decision has not been made. However, our likely sample and hold topology is shown below. For the sample and hold, a closed-loop topology with a transconductance amplifier was chosen. In this architecture the addition of an input buffer allows better decoupling from the input and output voltages. The circuit also makes the charge injection independent of the switches threshold voltage, so the injected charge only adds an offset value at the output, which can be compensated [14]. Figure 7. Standard bandgap reference with corrective amplifier. Digital Control: The digital controller will be an off-chip microcontroller. As input, it will receive the net voltage value (Qint) and a sequence of stimulation commands. Based on Qint, the controller will generate the switching signals of the multiplexers (SA and SB) and the 8-bit number to the DAC (DACin). Depending on the stimulation commands, the controller will output two enable signals (ENA and ENB). By leaving this block offchip, there will be a large amount of flexibility in testing and characterization, which is preferred for such a prototype. Support Blocks: A voltage reference generator will be needed to provide a reference for the DAC to generate its voltages. The chosen topology is shown in Figure 8. This type of reference uses a negative feedback amplifier to match the V DS of the PMOS transistors, making their currents very close to each other, and making the output voltage more accurate. Since fewer transistors are needed to match the currents, the supply can be smaller, making this topology ideal for low voltage applications. The drawback of this architecture is the increased power consumption due to the inclusion of the amplifier, but is well worth the increase in accuracy [13]. Figure 8. Standard bandgap reference with corrective amplifier. A clock generator will be used as the timing reference for all the clocked signals in the system; however, this can most likely be an external signal as well. These blocks are not shown in the diagram because they serve as support blocks to the rest of the components in the IC.

7 III. SYSTEM SIMULATIONS To test the functionality of the SCS prototype, system-level simulations were performed in Cadence. Below, Figure 9 exhibits the Cadence system-level schematic. Figure 9. Cadence schematic for system simulations. All on-chip components are in the dashed boxes. In the orange box is the AC-DC converter with the capacitor bank selection muxes and demuxes. In the blue box, the stimulation path and charge balance circuitry are shown. The green box shows the DAC and V REF generator. For simulation purposes, this was done in two parts; however, this will be done solely by the DAC in our completed system. Finally, the red box encloses the selection switching circuitry, which selects the capacitor to charge and discharge. Figure 10. Capacitor voltages during charging and discharging.

8 Figure 11. Charge imbalance loop functionality. Figures 10 and 11 show the transient operation of the SCS system. In Figure 10, the voltages of all four capacitors are plotted. One can see the capacitors charge up to the positive and negative reference voltage. At that time, the demuxes switch to the empty capacitors and continue charging. As they are charging up, a discharge command is sent to the full capacitors, at which point they discharge close to zero. The cycle continues. One possible unconsidered dilemma may occur when all capacitors are full. One would assume that at this point, the capacitors would switch at each cycle, but the end result is not clear. This scenario will be tested as design continues. Figure 11 shows the operation of the charge balance circuitry during two biphasic stimulations. The uppermost graph is of the discharge enable signals (active low). The second graph is of the current and voltage through the voltage-controlled resistor. The third graph depicts the integrated (net) voltage from the stimulations and the fourth exhibits the variation in V REF to compensate the imbalance. While the gain from the net voltage to the change in V REF must still be optimized, it is evident that the loop is working and that the SCS technique is viable. Figure 12 shows the power conversion efficiency of the system from input to capacitor.

9 Figure 12. Power conversion efficiency from secondary inductor to capacitors. IV. CONCLUSION The design is well on its way and schematic design has been ramping up since Draft 1. The group has been reduced to Orlando, Diego, and Jose; therefore, the work has been divided equally among the three. Diego is still leading the DAC design, while Orlando and Jose work on the AC-DC converter and driving circuitry. Blocks currently in schematic design are the DAC, the comparator, the start-up rectifier, and the possible development of a high gain, high bandwidth op-amp. Other blocks will be divided among the members according to the progress made in each area. Due to the limited size and number of pads, it was decided to implement a minimal proof of concept design, which could be readily expanded. Overall, low power consumption and high frequency operation govern each block. Based on the simulated results, it seems that the SCS system is very promising.

10 IV. REFERENCES [1] J. Simpson and M. Ghovanloo, "An Experimental Study of Voltage, Current, and Charge Controlled Stimulation Front-End Circuitry," Proc. IEEE Intl. Symp. On Cir. And Sys., pp , May 2007 [2] M. Ghovanloo, Switched-Capacitor based implantable low-power microstimulating systems, Proc. IEEE Intl. Symp. On Cir. And Sys., [3] P. S. Schlaffer et al., Optimal charging of capacitors, IEEE Transactions on Circuits and Systems I, Vol. 47, no. 7, pp , July [4] G. Bawa and M. Ghovanloo, "Active High Power Conversion Efficiency Rectifier with Built-In Dual- Mode Back Telemetry in Standard CMOS Technology," IEEE Trans. On Biomedical Cir. and Sys., vol.2, no.3, pp , Sept [5] G. Bawa, U. Jow and M. Ghovanloo, A high efficiency full wave rectifier in standard CMOS technology, IEEE Midwest Symp. Cir. and Sys., pp , Aug [6] P. E. Allen, CMOS Analog Circuit Design, Oxford University Press, [7] V. Bottarel, E. Dallago, G. Frattini, D. Miatton, G. Ricotti, G. Venchi, "Active Self Supplied AC-DC Converter for Piezoelectric Energy Scavenging Systems With Supply Independent Bias", IEEE Intl. Symp. on Cir. And Sys, [8] A.M. Kuncel and W.M.Grill, Selection of stimulation parameters for deep brain stimulation, J. of Clinical Neurophysiology, pp , [9] W. Kester and A. Devices, Data conversion handbook, Newnes, [10] J. Schoeff, "An inherently monotonic 12 bit DAC," IEEE Journal of Solid-State Circuits, vol. 14, no. 6, pp , 1979, [11] J. Deveugele and M. Steyaert, "A 10-bit 250-MS/s binary-weighted current-steering DAC," IEEE Journal of Solid-State Circuits, vol. 41, no. 2, pp , [12] J. Bruce, Nyquist-rate digital-to-analog converter architectures." IEEE Potentials, vol. 20, no. 3, pp , [13] R. Baker, CMOS: circuit design, layout, and simulation, Wiley-IEEE Press, [14] L. Dai and R. Harjani, "CMOS switched-op-amp-based sample-and-hold circuit." IEEE Journal of Solid- State Circuits, vol. 35, no. 1, pp , [15] E. Dallago, G. Frattini, D. Miatton, G. Ricotti, G. Venchi, "Self-Supplied Integrable High Efficiency AC- DC Converter for Piezoelectric Energy Scavenging Systems", IEEE Intl. Symp. on Cir. And Sys., 2007, pp [16] S. K. Kelly, and J. Wyatt, A power-efficient voltage-based neural tissue stimulator with energy recovery, IEEE Intl. Solid State Circuits Conf., 2004, vol. 1, pp [17] M. Bazes, Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers, IEEE Intl. Journal of Solid-State Circuits, vol. 26, no. 2, pp , [18] W. Kester, Analog Digital Conversion, Analog Devices, [19] M. Kennedy, "On the robustness of R-2R ladder DACs," IEEE Transactions on Circuits and Systems I:

11 Fundamental Theory and Applications, vol. 47, no. 2, pp , [20] B. Razavi, Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters, [21] L. Svensson and J.G. Koller, Driving a capacitive load without dissipating fcv 2, IEEE Symp. On Low Power Electronics, pp , [22] LT3468 Photoflash Capacitor Charger, Available: productdetail.do?navid=h0,c1,c1003,c1042,c1098,p2385 [23] S.K. Moore, Psychiatry's shocking new tools, IEEE Spectrum, Vol. 43, Issue 3, pp , Mar