TSEK38 Radio Frequency Transceiver Design: Project work, Testbench examples for transmitter design

Transcription

1 1(17) TSEK38 Radio Frequency Transceiver Design: Project work, Testbench examples for transmitter design Course home page: Course responsible: Ted Johansson LINKÖPING UNIVERSITY

2 2(17) Contents 1 Introduction Testbench Example QPSK Modulation Test Signal Generator Upconversion Mixer Transmitter Signal Processing Testbench Example 16-QAM Modulation Circuit Elements Performances LNA VCO Mixer... 16

3 3(17) 1 Introduction In the project work of the receiver part, much of the performance verification could be carried out by only evaluating the input intercept points, NF, and SNRs. These aspects have already been covered by the preceding part of the Laboratory Exercise manual. In the transmitter section, a modulated signal is expected to evaluate the performance of the design in terms of ACPR and EVM. The presented testbenches use QPSK and 16-QAM modulation, but can be modified to be used for other modulation schemes by changing data rate, bits per symbol, and modulation scheme. In section 2, the QPSK modulation testbench is described, and in section 3, the 16- QAM testbench is provided in order to demonstrate how two different modulation schemes can be used for the same testbench setup. To save the lab time and also facilitate the project work, an ADS archived testbench workspace can be downloaded from the course home page To unarchive it, use the File, Unarchive... function in ADS 2015 main window.

4 4(17) 2 Testbench Example QPSK Modulation The design example, Lab1_Tx_Ptolemy describes how to set up a testbench for a QPSK-modulated signal with raised cosine shaping. The testbench is similar to the one developed for the receiver in the laboratory exercise, chapter 8, but it uses a different set of simulation components. The overall transmitter testbench is divided into several sections as seen in Figure 1, which will now be discussed in more detail in the following sections. Figure 1. Transmitter testbench 2.1 Test Signal Generator The test signal generator is based on a Bits component to randomly generate the data sequence to be transmitted, ones and zeros, Figure 2. The bits are then fed to a Mapper component with a ModType setting of QPSK, which also covers other modulation schemes. The mapper/modulator is a generic box, which can map the bits to several modulation schemes, as shown in Figure 3.

5 5(17) Figure 2. Test Signal Generator Figure 3. Modulator

6 6(17) 2.2 Upconversion Mixer The output signal from the Mapper is connected to the input of the CxToRect component to extract the I and Q signals, which are then filtered with a raised cosine filter. The average input power to the transmitter is measured with a TkPower meter where the true input power has to be compensated by the specified loss (in db) in the MatchedLoss component. Figure 4. Upconversion Mixer

7 7(17) 2.3 Transmitter The Transmitter section only contains the simulation model of the transmitter, where Pin / VI / VQ and Pout represent the input and output signals of the transmitter model, which is similar to the receiver designed in in the laboratory exercise, chapter 8. Figure 5. Transmitter section In the testbench, the transmitter has been put as a black box providing the performance and amplification for the signals to be transmitted. The input signal of the transmitter is defined as a quadrature signal filtered at baseband. It is upconverted to RF frequency by two mixers and then combined and amplified as illustrated in Figure 6 (also called one-step transmitter).

8 8(17) Figure 6. Model of one-step transmitter Figure 7. Input signals of the transmitter

9 9(17) Compared to the receiver model, here the port Pin is no longer used for excitation. Instead, two separate (quadrature) input signals, VI and VQ are used, which are connected to ports with number 3 and 4, respectively. In one of the LO paths, a phase shift of 90 is introduced to support quadrature upconversion. The phase shift blocks, necessary in the IQ signal paths of the receiver, are now removed, and all filters as shown in Figure 6 are currently disabled. Notice that the time step variables previously used in the schematic are now removed and replaced by the variables defined in the Ptolemy schematic. To make sure that the cosimulation of an Analog/RF schematic with more than one input signal (we have two, VI and VQ ) works, we need to disable fast cosimulation in ADS. For this purpose double-click on the Envelope controller in the schematic, go to the Fast Cosim tab and uncheck the box labeled Enable fast cosimulation. The schematic is now ready for simulation in the Ptolemy schematic. Note that in your project work the Transmitter component should be replaced by a transmitter, which fulfills the design specifications.

10 10(17) 2.4 Signal Processing Figure 8. Signal Processing The output of the transmitter is connected to the splitter (S11) to the left. The signal then goes to the SpectrumAnalyzerResBw component and a raised cosine demodulator to get the I and Q signals. After the demodulator, two NumericSink components with the labels Q_out and I_out are added. The IQ signals are then combined again and fed to an EVM_WithRef component and a sink labeled Complex_signal. Signal generated in the Test Signal Generator section is delayed in time and then fed into to the second pin of the EVM component and a sink labeled Complex_ref. The amount of delay introduced in the Test Signal Generator and the Signal Processing sections have to be adjusted so that the signals are aligned in time. Note how the IQ signals are routed. Incorrect connections will lead to a high EVM. Signal verification can be done by plotting the real and imaginary contents of the Complex_ref and Complex_signal sinks. For the EVM calculation, we need to make sure that EVM is not based on the initial data as the signal has not reached the output yet. So we start to calculate EVM after the first 21 symbols, and then the EVM is computed over 20 symbols (in practice at least 200 symbols are necessary). To relax the requirement on the timing of the received signal, the EVM component synchronizes the symbols within 10 symbols time.

11 11(17) Name Value StartSym 21 SymBurstLen 20 SampPerSym sam_per_sym SymDelayBound 10 In the simulation, a number of parameters have been specified for the different components as seen in Figure 9. Figure 9. Parameters used in simulation In the specific example a data rate of 800 kb/s is assumed. Consequently, the symbol rate is 400 ks/s (800e3/2 since 2 bits per symbol). The number of samples per symbol (sam_per_sym) is set to 32. The total number of symbols (num_symbols) is 140. The IFfreq is set to GHz (1 MHz) and cannot be set to 0. It must be larger than 0, but can be set to 1 Hz if desired, which acceptable for a Zero-IF receiver. The RFfreq is set to GHz and is the frequency of the resultant output signal after the Transmitter. If an IF of 1 MHz is used together with an LO of GHz, the two resultant (among others) frequencies are and GHz. In this case we assume that the frequency at is filtered out. Consequently, the LO of the Analog/RF Transmitter component must have an LO operating at GHz to make this simulation work. The Envelope simulation controller in the Analog/RF Transmitter component must be set accordingly, as described previously in this manual to capture the input and output signals of the Transmitter. Note that no input power is specified; the input is adjusted by setting the VarLoss parameter used in the MatchedLoss components after the raised cosine filters. Next to the variable box QPSK_parameters there is a variable box called QAM_parameters, which set the simulation details for the 16-QAM simulation. After the simulation is completed, the following spectrum is achieved, see Figure 10, where the power in the adjacent and alternate channels can be computed as

12 12(17) described before. However, a data display with pre-defined equations and plots of the transmitted symbols, received symbols, received I and Q data and so on, is already prepared and called Lab1_Tx_Ptolemy.dds. Figure 10. Simulated spectrum Note: The final simulation to extract the power spectrum may take a very long time, and therefore during the initial simulation only very few symbols, num_symbols, should be simulated to align the transmitted and received data. As the testbench is designed in a very generic way with a flexible modulator, several modulation schemes can be used. The modulator parameters to be changed are the ones in Figure 9. The settings of Mapper must be changed as well. The Analog/RF schematic of the transmitter should be replaced according to the specifications of the assigned project, and if the pin names and structure are kept the same as described in this section, the testbench can easily be integrated in the project.

13 13(17) 3 Testbench Example 16-QAM Modulation The 16-QAM testbench uses the same schematic as prepared for the QPSK simulation. Two changes need to be introduced in the QPSK example: - In the Mapper component, change the modulation scheme to QAM16. - Enable the QAM_parameters and disable the QPSK_parameters VAR box. The 16-QAM modulation simulation assumes a data rate of 500 kb/s. Since each symbol represents 4 bits, the symbol rate is 125 ks/s. The testbench is ready to be simulated once these two changes are made. Figure 11. QAM parameters

14 14(17) 4 Circuit Elements Performances In the project work realistic values of gain, noise figure, compression point, and other parameters should be used. In this section, the performances of several LNAs, mixers, and VCOs (LO) are given, together with the sources so that a specific circuit can be tracked and investigated if necessary. 4.1 LNA LNA ref Freq (MHz) Tech (um) VDD (V) Power Gain (db) NF (db) IIP3 (dbm) P1dB (dbm) Pdc/Idc (mw/ma) Input return loss (db) Output mw ma return loss mw ma 5a ma b ma (db) S11 (db) [1] G. Gramegna, M. Paparo, P. G. Erratico and P. De Vita, A sub-1-db NF ±2.3-kV ESD-Protected 900-MHz CMOS LNA, IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp , July [2] X. Wu, L. Sun, Z. Wang, Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID, International Conference on Microwave and Millimeter Wave Technology, pp. 1-4, April [3] Z. Jie, H. Qi, A 1GHz low power CMOS LNA, International Conference on Microwave and Millimeter Wave Technology, pp. 1-3, April [4] F. Gatta, et al., A 2-dB Noise Figure 900-MHz Differential CMOS LNA, IEEE J. Solid-State Circuits, vol. 36, pp , Oct [5] W. Cheng, J. Ma, K. Yeo, M. Do, Design of a Fully Integrated Switchable Transistor CMOS LNA for 2.1 / 2.4 GHz Application, The 1 st European Microwave Integrated Circuits Conference, pp Sept

15 15(17) 4.2 VCO VCO ref Freq (MHz) Tech. (um) PN (dbc/hz) Offset Freq. (MHz) Pdc (mw) Idc (ma) VDD (V) [1] A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE J. of Solid State Circuits, vol. 34, pp , May [2] N. Seshan, J. Rajagopalan, K. Mayaram, Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range, IEEE International Symposium on Circuits and Systems, vol. 4, pp , May [3] J. Gil, S. Song, H. Lee, and H. Shin, A dbc/hz at 1MHz, 1.5mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors, IEEE Microwave and Wireless Components Letters, vol. 13, pp , Nov [4] P. Andreani and A. Fard, More on the 1/f2 phase noise performance of CMOS differential-pair LC-tank oscillators, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp , Dec [5] A.D. Berny, A.M. Niknejad, and R.G. Meyer, A wideband low-phase-noise CMOS VCO, in Proc. Custom Integrated Circuits Conf., pp , [6] P. Andreani and H. Sjoland, A 2.2 GHz CMOS VCO with inductive degeneration noise suppression, in Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, May 2001, pp [7] Y. Wu and V. Aparin, A monolithic low phase noise 1.7GHz CMOS VCO for zero-if cellular CDMA receivers, IEEE Int. Solid-State Circuits Conf., San Diego, pp , Feb [8] S. J. Cheng, Y. Zheng, C. H. Heng, "1.1 to 1.9GHz CMOS VCO for Tuner Application with Resistively Tuned Variable Inductor," IEEE RFIC Symposium, pp , June [9] F. Svelto, S Deantoni, R. Castello, A 1.3 GHz Low-Phase Noise Fully Tunable CMOS LC VCO, IEEE J. Solid-State Circuits, vol. 35, pp , March 2000.

16 16(17) 4.3 Mixer Mixer ref Freq (MHz) LO Freq. (MHz) LO power LO power (dbm) Tech (um) VDD (V) Conv Gain (db) NF (db) IIP3 (dbm) IIP2 (dbm) P1dB (dbm) / Pdc/Idc (mw/ mw) < > / / / (SSB) / / (DSB) (DSB) 9a (SSB) 9b (SSB) (SSB) (DSB) /5-3 -/ / / /- 3 [1] W. Cheng, C. Chan, C. Choy, K. Pun, A 1.2 V 900 MHz CMOS mixer, IEEE International Symposium on Circuits and Systems, vol. 5, pp , May [2] Belkhiri, C., Toutain, S., Razban, T., Wide bandwidth and low power CMOS mixer with high linearity for multiband receivers using direct conversion implementation, European Microwave Conference, vol. 3, pp. 4-6, Oct [3] Deguchi J., Miyashita, D., Hamada, M., A 0.6V 380µW 14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner, IEEE International Solid-State Circuits Conference, pp , Feb

17 17(17) [4] J. Cui, Y. Lian, M. Li, A low voltage dual gate integrated CMOS mixer for 2.4GHz band applications, IEEE Proceedings of the International Symposium on Circuits and Systems, May [5] H. C. Wei, R. M. Weng, and K. Y. Lin, A 1.5V high linearity CMOS mixer for 2.4GHz applications, Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'04), pp , May [6] Y. Liu, W. Lu, S. Cheng, S. Cao, X. Zhou, A 0.18um 3.3mW double-balanced CMOS active mixer, International Conference on ASIC, pp , Oct [7] Pihl, J., Christensen K.T., Bruun E., Direct downconversion with switching CMOS mixer, IEEE International Symposium on Circuits and Systems, vol. 1, pp , May [8] S. K. Alam and J. Degroat, A 2 GHz Highly Linear Downconversion Mixer in 0.18-um CMOS, 12th NASA Symposium on VLSI Design, Coeur d Alene, Idaho, USA, Oct. 4-5, [9] V. Vojkan, V.D.T. Johan, L. Arjan and V.R. Arthur, A High Gain, Low Voltage Folded-Switching Mixer with Current-Reuse in 0.18μm CMOS, IEEE J. Solid-State Circuits, vol. 40, pp , June [10] C.C. Tang, C.H. Wu, W.S. Feng, and S.I. Liu, "A 2.4 GHz low voltage CMOS down-conversion double-balanced mixer," IEICE Trans. Electron., vol.e84-c, no.8, pp , Aug